TW451214B - High efficiency CMOS pump circuit - Google Patents

Abstract

In this invention a booster circuit is driven with two complimentary boost signals. The two boost signals produce two complimentary boosted signals that are connected to a pump circuit output by means of two pass gate circuits. The transistors in each pass gate are controlled such that one pass gate circuit conducts in a first half of a clock cycle and the second pass gate circuit conducts in a second half of a clock period. Each pass gate is driven such that the full boosted signal is transferred to the output of the pump circuit and is not diminished by a threshold voltage of the pass gate circuit. The efficiency of this design keeps the output capacitor charged to a value close to the average value of boosted signal.

Description

Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (/) Detailed description of the invention: (1) Technical field of the invention: The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor memory circuit. High-efficiency CMOS pump circuit for components. (II) Background of the Invention: Generally speaking, the pump circuit is a very important function in semiconductor memory. It is used to provide an internal voltage that is higher than the voltage applied to the memory chip. The high internal voltage generated by the pump circuit is used for specific functions that cannot operate at low chip voltages. The provision of such an internal high voltage enables low voltage to be applied to the memory chip and utilizes most of the functions to reduce power consumption and improve chip integration. One important application of the pump circuit is to boost the "word line" (word ine) drive circuit bias voltage. The word line driver circuit needs a high voltage to increase the read and write current of the memory cell. Commonly used pump circuits include a booster circuit and a "pass gate". The booster circuit generates a high voltage, and the "pass gate" has several types, and its function is to connect the circuit. The charge from the capacitor of the boost circuit to the output load includes an integrated capacitor on the output load to smooth the voltage generated by the pump. In U.S. Patent No. 5,222,042, a step-up circuit for a dynamic random access memory (DRAM) word line is disclosed, which uses two step-up circuits to boost the word line signal and reduce the capacitor Leak effect. In U.S. Patent No. 5,134,317, a charge pump circuit for dynamic random access memory is disclosed, which reduces the charge of the boost capacitor when --------- ' Γ Packing --- order (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 1214 1214 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System A7 __B7_ V. Description of the invention (>). In U.S. Patent No. 4,673,829, a pump circuit is disclosed for programming a memory array, which can reduce the leakage current of "unselected" memory cells. Among the related technologies, there is an IEEE Journal of Solid-state Circuits technical journal. In March 1998, Volume 33, Volume 3 disclosed "High Efficiency CMOS Voltage Multiplier" by Pierre Favrat, which describes The voltage doubler uses a charge pump unit and a modified string switch. Integrated charge pumps with 75% efficiency, while using external capacitors can achieve up to 95% efficiency. In addition, the IEEE Journal of Solid-state Circuits in April 1991, Volume 26, Volume 4, disclosed Nakagome's "Experimental 1. 5V 64Mb Dynamic Random Access Memory", of which high-density dynamic The low-voltage circuit technology used in random access memory includes a word line driver with a charge pump circuit to achieve a high boost ratio. One problem with pump circuits is the threshold voltage of the "pass gate" transistor, which reduces the amount of charge transferred to the output of the pump circuit. However, the "pass gate" transistor, which is not fully turned on, has a high threshold voltage. To solve this problem 'the gate of the pass gate transistor can be driven to a high voltage, 3 times VCC' but driving the gate of the pass gate transistor to an extremely high voltage 'will cause The problem of circuit breakdown that drives the gate of a "pass gate" transistor. As for other ways to reduce the high gate voltage, it is difficult to maintain the "pass gate", the (pass gate) transistor is fully turned on, and the self-boost circuit is transferred to the output I .._ L --.----, J equipment ------ Booking (please read the notes on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) 8 4 Lin (210X297 mm) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 1 2 1 4 A7 __B7___ V. Description of the invention ()) The low conductivity of the charge. Because the well bias cannot maintain the highest voltage, it may cause the circuit to latch up. Ο See FIG. 1A is a circuit diagram showing a simple pump circuit of a conventional technique. The booster circuit is composed of an N-channel transistor 10 and a capacitor C1. The gate and the drain of the N-channel transistor 10 are common. The ground is connected to VCC, and the capacitor Cl is driven by a boost signal Bl. The boosted vo 1 tage at node 11 is connected to Vout13 by an N-channel transistor 12. It is connected to ¥ 0111: 13 Capacitor C0 stores the charge 40 Utl3 from the boosted voltage on node 11. The effect of the threshold voltage of the crystal 10 and the transistor 12 reduces the amount of charge transferred to the pump circuit, which causes the efficiency of the pump circuit to be reduced. Please refer to FIG. 1B, which shows a pump of another conventional technique. The circuit diagram of the circuit. The first voltage boosting circuit is composed of transistor 10 connected in parallel with the second transistor 20. The gate of the second transistor 20 is connected by a second boost signal B2 via a second capacitor. Driven by C2. The second signal booster circuit is the same as the first signal booster circuit. It is composed of two transistors 21 and 22 between V0 and capacitor C2, connected in parallel. The second transistor 21 The gate is driven by the first boost signal Bl through the first capacitor Cl. The feedback circuit generated by the interactive coupling of the transistors 20 and 21 drives the transistors 20 and 21 to turn on completely, eliminating the rise of node 11 Threshold voltage effect of transistors 20 and 21 on the voltage and voltage. The transistor 23 forms a "pass gate" (pass This paper size applies Chinese National Standard (CNS) A4 specification (21 OX 297 mm) —-L --- ---- Equipment ------ Order gland · '(Please read the back first Please fill in this page again.) Printed A7 B7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (+) gate), which connects the DC component of the boosted voltage to V〇utl3 and the output capacitor. CO. The 3 times Vcc booster circuit 14 is used to drive the 3 times Vcc driver 15, and the 3 times Vcc driver 15 is connected to the gate of the "pass gate" transistor 23 to generate about 2 times the Vcc output voltage Voutl3 The high voltage of the 3x Vcc booster 14 and the 3x Vcc driver 15 may cause the circuits of the booster 14 and the driver 15 to collapse. Please refer to FIG. 1C ', which is a circuit diagram of a conventional pump circuit. This pump circuit does not use 3 times the Vcc pump voltage to generate output 13. This booster circuit is the same as the booster circuit shown in Figure 1B except that the boosted signal (boosted si gna l ·) from the circuit node 16 is connected to the "pass gate" 29. booster signal) The two boosted signals 11 and 16 generated by Bl and B2 have AC components for biasing VB (5 generator 28 and "pass gate" 29. Vw The generator two transistors 23 and 24 are used to establish a voltage to bias the N-wells for the P-channel transistors 23, 24, 25, and 26. The source of the transistor 25 is connected to the voltage from node 11 , The initial boost is about 2 times the Vcc level, and the voltage from the node 16 connected to the gate of the transistor 25 is initially pulled down to about the Vss level. This fully turns on the "pass gate" transistor 25. After the initial voltage appears on the source and gate of transistor 25, the charge of C1 begins to share CO via transistor 25, and the transistor 10 and 20 'C2 begin to precharge to Vcc level. From circuit node 16 The gate voltage on the transistor 25 starts to increase, and the source voltage from the circuit node 11 starts to decrease. Body --L --.---- Ί1 ^ ------, 1T ----- J line (read the note on the back of the first cabinet, and then fill out this page) This paper size applies to Chinese national standards (CNS) A4 specification (210X 297 mm) 451214 A7 £ 7 _____ 5. Description of the invention (_?) 25 is not fully turned on, the conductivity of transistor 25 is reduced, and the charge C0 is longer. The transistor 26 is similar, causing the pump The efficiency loss of the circuit. (3) Brief description of the invention: Therefore, in the present invention, a high-efficiency CMOS pump circuit is provided, which includes: a booster circuit, which is driven by two boost signals to generate A first boost voltage and a second boost voltage; the first boost voltage is connected to a first complex "pass gate" transistor; the second boost voltage is connected to a second complex "pass gate" ( pass gate) transistor; controlling the first complex "pass gate" transistor to generate a high conductance during a first half clock period to conduct charge current from the first boosted voltage To the output of the pump circuit; and controlling the above-mentioned second complex "pass gate" transistor so that During the second half clock period, two high conductances are generated to conduct a charge current from the second boosted voltage to the output of the above-mentioned pump circuit. Preferably, the gate of the "pass gate" transistor is controlled The voltage is the highest output voltage of the above-mentioned pump circuit plus a threshold voltage of the above-mentioned "pass gate" transistor to fully turn on the above-mentioned "pass gate" transistor. A plurality of "pass gate" transistors and the above-mentioned second plurality of "pass gate" transistors include a parallel-connected NMOS transistor and a PM0S transistor to generate a high conductance when it is completely When turned on, the power supply self-boosting voltage is allowed to effectively connect the above-mentioned output of the above-mentioned pump circuit. This paper size is applicable to China National Standard (CNS) A4 specification (21〇 × 297 mm) ---------- One ^ Binding Travel (please read the precautions on the back before filling this page) Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau 1512 14 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention description (ς) Better, the above PMOS transistor system is in the N well, and its bias voltage is the highest circuit voltage. To prevent circuit latch up. Preferably, the output voltage of the pump circuit is about twice the circuit bias voltage. In the present invention, a CMOS pump circuit is provided, which includes: a booster circuit connected to two "pass gate" circuits; the booster circuit is composed of two complementary (comp 1 imentary) boost signals (boost signa 1); the complementary boosted signals generate two complementary boosted signals; the first boosted signal of the two complementary boosted signals connects the two "pass gates" (pass gate) ) The first "pass gate" circuit of the circuit; the second boosted signal of the two complementary boosted signals is connected to the second "pass gate" of the two "pass gate" circuits ( pass gate circuit; the second boosted voltage is connected to a second plurality of "pass gate" transistors; the first and second "pass gate" circuits are controlled to connect the first and second The boosted signal is output to the pump circuit to generate an output voltage higher than the bias voltage of the boost circuit. Preferably, the first and second "pass gate" circuits are controlled to compensate for the threshold voltage of the "pass gate" transistor to fully turn on the "pass gate" circuit. Crystal. Preferably, the first "pass gate" circuit and the second "pass gate" circuit described above include a NM0S transistor and a PM0S transistor which are connected in parallel and controlled separately. Generate a high conductance "pass gate, (pass gate) ° (Please read the precautions on the back before filling this page)

This paper size applies the Chinese National Standard (CNS) M specification (210 X 297 mm) 2 1 4 A7 B7 Five 'invention description (7) Preferably, the above output voltage is approximately the same as the circuit bias voltage of the above booster circuit 2 times the amplitude. In the present invention, a voltage boosting method is provided, which includes: connecting two complementary boosting signals to one of a voltage boosting circuit; and connecting a first boosting signal from the boosting circuit to A first "pass gate" circuit; connecting a second boosted signal from the booster circuit to a second "pass gate" circuit; a first half cycle at one clock, Controlling the first "pass gate" circuit to turn on 'having high conductance; conducting the current from a first boosted signal to the output of the pump circuit during the first half cycle of the clock; The first "pass gate" circuit has a high conductance, and a capacitor connected to the output of the pump circuit has a high clock ratio; during the second half cycle of the clock, the second "pass gate" is controlled. " (pass gate) circuit is on and has high conductance; in the second half cycle of the clock, the current from the second boosted signal conducts current to the output of the above-mentioned pump circuit; through the second "pass gate" (pass gate) High conductance of the circuit, efficiently charging the capacitor connected to the output of the pump circuit; and generating a pump circuit output voltage that is higher than the voltage bias of the pump circuit. Preferably, the first The "pass gate" circuit and the above-mentioned second "pass gate" circuit are connected to each of the above-mentioned first "pass gate" circuit and the above-mentioned second "pass gate" circuit The gate voltage of the transistor is approximately equal to the above output voltage plus the threshold voltage of the above transistor. (Please read the precautions on the back before filling out this page.) The printed paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) 451 2 1 4 A7 ____B7__ 5. Description of the invention (K) The better, the signal from the first boost and the signal from the second boost The conduction current is synchronously conducted by controlling the N-channel transistor and the P-channel transistor in the first "pass gate" circuit, and generates a high conductance during the first half period of the clock, By controlling the N-channel transistor and the P-channel transistor in the second "pass gate" circuit to conduct synchronously, a high conductance is generated during the second half cycle of the clock. For your review The members can further understand and recognize the features, purpose, and effects of the present invention, and they are explained in detail with the drawings as follows: (4) Brief description of the drawings: Figure 1 is a circuit diagram showing a conventional pump circuit Figure 2 is a circuit diagram of a pump circuit according to an embodiment of the present invention. Figure 3 is a waveform diagram of a pump circuit according to an embodiment of the present invention. FIG. 4 is a block diagram of a word circuit driver connected to a pump circuit according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating a method for boosting a voltage using a pump circuit according to an embodiment of the present invention. The same drawing numbers in the drawings represent the same parts. Drawing number description: CO, Cl, C2 'C3, 27-capacitor

Bl, B2-Boost signal 10, 12, 20 ~ Transistor 11, 16, 31, 32-node: ________Q_______ This paper size adopts China National Standard (CNS) M specification (210X297 mm) (read first) Note $ on the back and fill in this page again), install A7 B7 printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention description (y) 13, 45-output voltage 14-3 times Vcc booster (please first Read the notes on the back and fill in this page again) 15- 3x Vcc driver 28- VB (; generator 29- "pass gate" 30- boost circuit 33, 34- "pass gate" Circuit 35 ~ 44-Transistor 46-Clock circuit 47- Control logic 48- Vph pump circuit 49- Vpp pump circuit 50- Limit circuit 51- N2a voltage is Vph value 52a, 52b-Nla voltage

53- N2b voltage is 0V

54- N2b voltage is Vph value 55_N2a voltage is 0V The 56a, 56b-Nlb voltage (5) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy is described in detail in the following: Best embodiment. Please refer to FIG. 2, which is a circuit diagram of the Vpp pump circuit 49 of the present invention. The clock circuit 46 provides control logic 47 timings, which are produced by _; _ίο_; _ This paper size uses the Chinese National Standard (CNS) A4 specification (210X297 mm) 5 2 ί 4 · Α7 Β7 V. Description of the invention ((Ό) (please read the precautions on the back before filling this page). The complex control signals N2a, N2b, P2a and P2b. Booster circuit 30 is the same as the booster circuit of the conventional technology in Figure 1C. It uses two boosted signals to connect a "pass gate" transistor. The boosted signal Nla on node 31 and the boosted signal Nlb on node 32 are connected to two. "Pass gate" circuits 33 and 34, and Nla and Nib have the highest voltage value of about 2 times Vcc. The boost circuit is composed of transistors 35, 36, 37 and 38 and capacitors C1 and C2. Booster signal B1 is applied to capacitor C1 and to the source of transistors 35 and 36. Booster signal B1 is a clocked pulse, which has a minimum voltage of zero volts and The highest voltage is about Vcc, and the high voltage Vcc accounts for about 50% of the duty cycle. The boosted signal B2 is applied to capacitor C2 and to the source of transistors 37 and 38. The boosted signal B2 is a clock wave which is complementary to the boosted signal B1 and has a minimum voltage of zero volts and The highest voltage is about Vcc, and the high-voltage Vcc accounts for about 50% of the working cycle. The printed circuit 36 and 37 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs are interactively coupled to provide feedback to each other, eliminating the effects on the boosted voltage on nodes 31 and 32 The threshold voltage effect of the transistor of amplitude. The gate of transistor 36 is connected to the source and node 32 of transistor 37, and the gate of transistor 37 is connected to the source and node 31 of transistor 36. The gate system of transistor 36 Driven by the boosted signal Nib on node 32, the gate of transistor 37 is driven by the boosted signal Nla on node 31. When the boosted signal Nib is high, the boosted signal Nla is low , Drive __: ____11 _ This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 cm): > 4 δ 4 Printed by the Intellectual Property Bureau Staff Consumer Cooperatives 2 14214 A7 __B7_ V. Description of the invention ( (/) The power transistor 36 is fully turned on, The boosted signal on node 31 is approximately equal to the voltage level of Vcc. After the voltage on node 31 is about Vcc voltage, the boosted signal B1 is high, and the voltage Ma on node 31 is increased to approximately twice the value of Vcc And close transistor 36. Then, the boosted signal B1 drives Nla on the node 31 high, the boosted signal Nib is low, and the drive transistor 37 is fully turned on, so that the boosted signal on the node 32 reaches a voltage level approximately equal to Vcc. After the voltage at the node 32 is about Vcc, the boost signal B2 is high, the voltage Nib at the node 32 is increased to approximately twice the value of Vcc, and the transistor 37 is turned off. The boosted signal Nla on node 31 is connected to a "pass gate" circuit 33, and the boosted signal on node 32 is connected to a "pass gate" circuit 34. The "pass gate" circuits 33 and 34 connect the output Vout of the pump circuit and the capacitor C3 the pass gate circuit 33 includes transistors 39 and 40, which respectively connect the signal on node 31 to Vout 45 ° "The transistor 39 that passes through the (pass gate) circuit 33 is an N-channel transistor, and its gate is driven by the signal N2a, where N2a = Vph = Vpm + Vth, Vpm is the maximum amplitude of Vout, and Vth is N Threshold voltage of the channel transistor 39. Transistor 40 is a P-channel transistor in N-well. Its gate is driven by signal P2a, where P2a = Vph = Vpm + Vth. The N-well bias voltage Vph of the transistor 40 is equal to the voltage of the maximum amplitude of Vout plus the threshold voltage of the transistor 'to prevent the problem of circuit latch-up. "Pass gate, circuit 34 includes transistors 43 and 44, (#Read the precautions on the back before filling this page). Install. The size of the paper is applicable to China National Standards (CNS) A4 specifications ( 210X297 mm) A7 B7 451214 V. Description of the invention (丨 less) It connects the boosted signal Nib to Vout 45 on node 32 respectively. The transistor 34 of the "pass gate" circuit 44 is N Channel transistor, whose gate is driven by "pass gate" circuit signal N2b, where N2b = Vph = Vpm + Vth. Transistor 43 is a P-channel transistor in N-well, and its gate is "pass gate" ( Pass gate) circuit signal P2b driver, where P2b = Vph = Vpm + Vth 〇 N-well bias voltage Vph of transistor 43, the voltage equal to the maximum amplitude of Vout plus the threshold voltage of the transistor, to prevent the problem of circuit latch-up. Referring to the voltage waveform shown in FIG. 3, the amplitude and timing control of the gate signals N2a, N2b, P2a, and P2b enable the transistors 39 and 40 of the “pass gate” circuit 33 to be in a clock period. One half is fully on, and the transistors 44 and 43 of the "pass gate" circuit 34 The other half of the clock period is fully turned on. The gate control signals N2a, N2b, P2a, and P2b have a voltage of Vph or 0 volts, so that the "pass gate" transistor provides a high conductance. The preferred embodiment uses N-channel transistors and P-channel transistors in "pass gates" 33 and 34. Any number and type of transistors can be used to provide high conductance and connect the boosted signals Nla and Nib to output 45. For example, a single N-channel transistor or a single P-channel transistor can also be used. For higher conductance, two or more N-channel transistors or P-channel transistors can be used. See also Figure 3, which shows a waveform diagram according to an embodiment of the present invention. The timing boost signals B1 and B2 are complementary to each other and have 13 (please read the precautions on the back before filling this page). Printed by the Intellectual Property Bureau Staff Consumer Cooperatives This paper is printed in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumer Assets Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___ B7 V. Description of invention (1 to date) 1 Pulse voltage from 0 volts to Vcc. Boost signal B1 drives node 31 to generate voltages Nla 52a and 52b 〇 When boost signal B1 is high, Nla 52a is a positive voltage greater than Vcc, and the charge is passed through The gate) circuit 33 distributes the output to the capacitor C3, generates a pump circuit output 45, and has a rising voltage, such as Vout 57 shown in -3. The positive rise in Vout 57 continues until the voltage is reached, at which point the pump circuit stops pumping current to the output capacitor C3. When the boost signal B1 is low, the "pass gate" circuit 33 is closed, and the node 31 is precharged to Nla = Vcc 52b. The boost signal B2 drives the node 32 to generate voltages Nib 56a and 56b. When the boost signal B2 is high, Nib 56a is a positive voltage greater than Vcc, and the charge is distributed to the output capacitor C3 via a "pass gate" circuit 34 to generate a pump circuit output 45 with a rising voltage, as shown in the figure. Vout 57 shown in three. The positive rise in Vout 57 continues until the voltage reaches the target level, at which time the pump circuit stops pumping current to the output capacitor C3 »When the boost signal B2 is low, the" pass gate "circuit 34 is closed, and the node 32 is preset. Charge to Nib = Vcc 56b. The node voltages Nla and Mb are controlled by the "pass gate" control signals N2a, N2b, P2a and P2b connected to the "pass gate" transistors 39, 40, 43 and 44. “Pass gate” circuits 33 and 34 are connected to the pump circuit output 45. When N2a = Vph 51, P2a = 0 V 53, “pass gate” N channel transistor 39 and P channel Transistor 40 conducts high conductance and connects current from node 31, Nla 52a, to output capacitor C3 to produce output voltage Vout 57. When N2a = 0V 55, P2a = Vph 54, "pass the gate" (pass _gai: e) 33 N-channel transistor —. — ^ --_------- i ------- " (Please read the precautions on the back before filling this page) This paper size applies China National Standard (CNS) A4 specification (210X297 mm) 4 A7 __B7_ V. Description of the invention (body) The body 39 and the P-channel transistor 40 are turned off, and the voltage on the node 31 is charged to Vcc 52b. When N2b = Vph 54, P2b = 0 V 55, the N-channel transistor 44 and P-channel transistor 43 pass through the pass gate 34 to generate high conductance, and connect the current 'Nib 56a' from node 32 to the output Capacitor C3 'to generate an output voltage Vout 57. When N2b = 0V 55, P2b = Vph 54 ', the N-channel transistor 44 and P-channel transistor 43 of the "pass gate" 34 are closed, and the voltage at node 32 is charged to Vcc 56b. When the gate signal N2a is a high level, the level is Vph 51, and the source Nla connected to the transistor 39 is also high 52a, the N-channel transistor 39 of the "pass gate" 33 is turned on. When the gate signal P2a is a low voltage of 0 volts 53 and the Nla of the source connected to the transistor 40 is high 52a, the P-channel transistor 40 of the "pass gate" 33 is turned on. When the gate signal N2b is at a high level, the level is Vph 54, and the source Nib connected to the transistor 44 is also high 56a, the N-channel transistor 44 of the "pass gate" 34 is turned on. When the gate signal P2b is a low voltage of 0 volts 55 and the source Nib connected to the transistor 43 is 56a high, the P-channel transistor 43 of the "pass gate" 34 is turned on. Please refer to FIG. 4 again, which shows a block diagram of a plurality of Vpp pump circuits 49 connected to a complex digital line driver according to an embodiment of the present invention. The Vpp pump circuit provides the driver with high voltage, about 2 times Vcc, allowing the design and operation of the semiconductor memory to have an appropriate noise margin. Connected to the Vpp pump circuit is a Vph pump circuit 48 for providing a bias to the Vpp pump circuit 49. The output of the Vph pump circuit generates the voltage Vph = Vout i Vth, where Vout is the paper size and applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (谙 Please read the precautions on the back before filling in this K ·) -Installation. -Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 451214 A7 B7 V. Description of the invention (θ) (Please read the precautions on the back before filling this page)

The output voltage of the Vpp pump circuit 49 is about 2 times Vcc, and Vi: h is the threshold voltage of the N-channel transistors 39 and 44 “pass gates” 33 and 34, as shown in FIG. The output voltage of the Vph pump circuit 48 enables the Vpp pump circuit to pass the N-channel transistors of pass gates 33 and 34 fully open, and provides the N-well bias voltage of the P-channel transistors 40 and 43 to prevent the circuit Latch problem. The limiting circuit 50 is connected to a Vph pump circuit 48. The limiting circuit 50 detects the output voltage of the Vph pump circuit 48. If the output voltage of the Vph pump circuit 48 is less than Vph, the limiting circuit 50 is turned on so that the Vph pump circuit 48 is enabled, otherwise the Vph pump circuit is controlled to be turned off. The VPP pump circuit 49 is a high-efficiency circuit that generates an output voltage Vout = Vpp, which is about 2 times Vcc, and is connected to provide power to the word line driver of the memory array. The circuit configuration shown in Figure 4 provides the required voltage-biased multi-digital line driver and requires the only high-voltage Vph pump circuit 48 β. Several efficient Vpp pump circuits 49 utilize the Vph pump circuit 48 The output generates voltage to drive the multi-digital line driver. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics Please refer to Figure 5 again for a flowchart of a method for generating a high-efficiency pump voltage. 60 is two typical complementary boost signals connected to the boost circuit to generate two complementary boost signals. 61 is a first boosted signal connected to a first "pass gate" circuit. 62 is a second boosted signal connected to a second "pass gate" circuit. 63 is the first half cycle of one clock, which controls the first "pass gate" to fully open, resulting in high conductance. 64 is the first half cycle of one clock, the signal conducting current from the first boosted signal passes the first "pass gate" to Pudian's paper standard, using China National Standards (CNS> A4 specification ( 210X297 mm)

V. Description of the Invention The output of the (/ L) circuit '65 is to make the first "pass gate" pass conductance to charge the output capacitor with high efficiency. 66 is the second half cycle of the clock, which controls the second "pass gate" to be fully turned on 'to generate high conductance. 67 is the second half cycle of the clock, and the signal conducting current from the second boosted signal passes through the second "pass gate," (pass gate) to the output of the pump circuit. 68 is the second "pass gate" ( The high conductance of the pass gate) is charged to the output capacitor with high efficiency. In order to generate a high clock ratio of the output voltage of the pump circuit, it is about 2 times Vcc. The above shows that the purpose and efficacy of the present invention are deep. The "progressive implementation" has great industrial use value, and is a new invention not seen in the market. It fully complies with the requirements of the invention patent, and applies according to law. Only the above mentioned ones are only a comparison of the present invention. Only the best embodiment, when the scope of the present invention can not be limited. That is to say, all equal changes and modifications made in accordance with the scope of the patent application of the present invention should still be within the scope of the invention patent, please ask your review committee Ming Jian, and praying for the right, is the most prayer. II --.---- ΓΤ 装 丨-./ 'Qing beg exhausted yellow 疔 & the master of the dream capture guide page ----

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A Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper uses the Chinese National Standard (CNS) A4 size (210X297 mm)

Claims (1)

ί Shoulder A8 '' 1 Β8 C8 _ D8 VI. Application for Patent Scope Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1. A voltage pump circuit including: a boost circuit, which is boosted by two boost signals (boost signal) to generate a first boost voltage and a second boost voltage. The first boost voltage is connected to a first complex "pass gate" transistor; the second boost voltage is connected to a first Two complex "pass gate" transistors; controlling the first complex "pass gate" transistor to generate a high conductance during a first half clock period from the first A boosted voltage conducts the charge current to the output of the pump circuit; and controls the second complex "pass gate" transistor to generate two high conductances during the second and second half clock periods, from the second The boosted voltage conducts the charge current to the output of the pump circuit. 2. The voltage pump circuit as described in item 1 of the scope of patent application, wherein the gate voltage of the above-mentioned "pass gate" transistor is the highest output voltage of the above-mentioned pump circuit plus one of the above-mentioned "pass gates" (Pass gate) threshold voltage of the transistor to fully turn on the "pass gate" transistor. 3. The voltage pump circuit as described in item 1 of the scope of patent application, wherein the first plural number The "pass gate" transistor and the above-mentioned second plural "pass gate" transistor include a NM0S transistor and a PM0S transistor connected in parallel to generate a high conductance when it is fully turned on '(Please read the note on the back before writing this page concisely.) Binding-Binding. This paper size applies to Chinese National Standard (CNS_) A4 specification (2100297 mm) 451 21 4 A8 B8 S______ 6. Allowable current for patent application The self-boosting voltage is effectively connected to the above-mentioned output of the above-mentioned pump circuit. (Read the notes on the back and then fill in this page) 4. The voltage-pump circuit described in item 3 of the scope of patent application, in which the above PMOS circuit crystal It is in the N well and its bias voltage is the highest circuit voltage 'to prevent circuit latch-up. 5. The voltage pump circuit as described in item 1 of the scope of patent application' wherein the above output of the above-mentioned pump circuit The voltage is about 2 times the circuit bias voltage. 6. A CMOS pump circuit includes: a booster circuit connected to a "pass gate" circuit; the booster circuit consists of two complementary ( comp 1 i mentary) driven by a boost signal; the complementary boost signals generate two complementary boosted signals; the first boost signal connection of the two complementary boost signals The above two, the first "pass gate" circuit of the "pass gate" circuit; the second boosted signal of the two complementary boosted signals is connected to the consumption of the employees of the intellectual property bureau of the two Ministry of Economic Affairs The cooperative prints a second "pass gate" circuit of the "pass gate" circuit; the second boosted voltage is connected to a second plurality of "pass gate" transistors; and controls the first And second " A “pass gate” circuit 'connects the first and second boosted signals to the output of the pump circuit' generates an output voltage that is higher than the bias voltage of the boosted circuit. -------- -:-This paper size adopts Chinese National Standard (CNS) A4 (210X297 mm) ABCD VI. Patent Application 7. The CMOS pump circuit described in item 6 of the scope of patent application, which controls the above The first and second "pass gate" circuits compensate for the threshold voltage of the "pass gate" transistor to fully turn on the "pass gate" transistor. 8. The CMOS pump circuit described in item 6 of the scope of patent application, wherein the first pass gate circuit and the second pass gate circuit include parallel connection, respectively Control one Li0S transistor and one PM0S transistor to generate a high-conductance "pass gate" 〇9. The CMOS pump circuit described in item 6 of the patent application range, wherein the output voltage is about It is twice the amplitude of the bias voltage of the circuit used in the above booster circuit. 10 · A method of voltage boosting, including: a. Connecting two complementary boosting signals to one of a voltage boosting circuit, and b. Connecting a first boosting circuit from the boosting circuit; Signal to a first "pass gate" circuit; printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs c. Connect a second boosted signal from the above booster circuit to a second "pass gate" (pass gate) circuit; d. control the first "pass gate" circuit to open with a high conductance during the first half cycle of one clock; e. from the first half cycle of the clock, The first boosted signal conducts current to the above-mentioned output of the above-mentioned pump circuit; this paper is fully compliant with the national standard (CNS) A4 specification (2104 such as 7 mm) 'A8 BS C8 D8 F. Charge the capacitor with a high clock ratio to the above-mentioned output of the pump circuit via the high conductance of the first "pass" circuit; g. During the second half of the clock, Controls the opening of the above-mentioned second "pass gate" circuit Has high conductance; h. Conducts current from the second boosted signal to the above-mentioned output of the above-mentioned pump circuit during the above-mentioned second half period of the clock; i. After the above-mentioned "pass gate" (pass gate ) High conductance of the circuit, efficiently charging the capacitor connected to the above output of the above pump circuit; and j. Generating a output voltage of the pump circuit, which is higher than the voltage bias of the above pump circuit. The method described in item 1G of the scope, wherein the first "pass gate" circuit and the second "pass gate" circuit are controlled to connect the first "pass gate" circuit and The gate voltage of each transistor of the second "pass gate" circuit is approximately equal to the output voltage plus the threshold voltage of the transistor. 12. The method described in item 10 of the scope of patent application The conduction current from the first boosted signal and the second boosted signal is synchronously conducted by controlling the N-channel transistor and the P-channel transistor in the first "pass gate" circuit, The first half cycle of the clock described above generates a high conductance, and by controlling the N-pass transistor and the P channel in the second "pass gate" circuit, the Chinese paper standard ( CNS) A4 specification (210) ¾ 97 mm) ~ ~ (Please read the note on the back before filling in this page): __Order. Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economy 451214 H C8 D8 VI. Application Patent scope The transistor conducts synchronously, and in the second half cycle of the clock, a high conductance is generated. (Please read the precautions on the back before filling this page) Moderate ruler printed by quasi-standard bidder j Guoguo I in the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _Paper I SNCA Epidemic ~ 7 9 * 2 -X ο twenty one