TW447077B - Method for improving the characteristics of dielectric layer with a low dielectric constant formed by chemical vapor deposition - Google Patents
Method for improving the characteristics of dielectric layer with a low dielectric constant formed by chemical vapor deposition Download PDFInfo
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447 077 五、發明說明α) 發明領域: 本發明係有關於一種化學氣相沉積(CVD)之低介電常 數介電層(LOW K)以經稀釋之含氧電漿處理以改善其與形 成於其上之膜層接合性(a d h e s i ο η )之方法,例如碳化梦層 或氮化矽層、氮化钽層或氮矽氧化層其中之一和上述CVD LOW Κ材料接合性》 發明背景: /447 077 V. Description of the invention α) Field of the invention: The present invention relates to a chemical vapor deposition (CVD) low-k dielectric layer (LOW K) treated with a diluted oxygen-containing plasma to improve its formation. The method of film adhesion (adhesi ο η) on it, such as one of the carbonized dream layer or silicon nitride layer, tantalum nitride layer or silicon nitride oxide layer and the above CVD LOW κ material adhesion "Background of the invention: /
V 積體電路之製程除了使得晶片内元件的體積小,以達 到高密度及降低單位成本之目的之外,元件之最後的性能 更是關鍵’而除了電晶體元件本身之設計外,最後之内連 接金屬導線乃至内連線間介電層都是重要影響元件速度表 現的重要因素,這是因導線之阻值R,與上、下層導線及 相鄰導線之間會有電容C存在,一如熟悉相關技術之人士 所共知,此RC值愈低代表較低之時間延遲,因此目前内連 線銅製程已有逐漸取代鋁製程之趨勢,此外,將内連線間 介電層改用低介電常數之介電層以使寄生電容降低,以提 高速度,也是目前半導體業處理RC延遲的共識。 \ 有機旋塗式玻璃(spin on glass; S0G)是已知具有低 -介責-常-奮-之-材-料_具-有-食之-間隙-填-補-能-力--。一ittr-夕卜-—如 以化學氣相沉積法沉積之LOW K材料,例如正甲基矽院In addition to the process of making the integrated circuit of the V chip small, in order to achieve high density and reduce unit costs, the final performance of the component is more critical. In addition to the design of the transistor component itself, the final The dielectric layer between the metal wires and even the interconnects is an important factor that affects the speed performance of the device. This is because the resistance value R of the wire, there will be a capacitor C between the upper and lower wires and adjacent wires, as Those familiar with related technologies know that a lower RC value represents a lower time delay. Therefore, the current copper interconnect process has gradually replaced the aluminum process. In addition, the dielectric layer between interconnects has been changed to a lower level. A dielectric layer with a dielectric constant to reduce parasitic capacitance to increase speed is also the current consensus in the semiconductor industry to handle RC delays. \ Organic spin-on glass (spin on glass; S0G) is known to have low-responsibility-often-fee-of-materials-materials_with-food-gap-fill-fill-energy-force-- . An ittr- Xibu --- such as LOW K material deposited by chemical vapor deposition, such as n-methyl silicon
^ 447 077 五、發明說明(2) (tetramethylsilane)由於不致於一如S0G有吸水性的問 題,且其介電常數不到3,僅2.95而已,因此更是廣範使 用於雙鑲嵌製程中之金屬内連線介電層。447 077 V. Description of the Invention (2) (tetramethylsilane) is not widely used in SOG as it has the problem of water absorption, and its dielectric constant is less than 3, only 2.95, so it is widely used in the dual damascene process. Metal interconnect dielectric layer.
然而,由於如圖一所示,雙鑲嵌製程中,通常都需要 一層厚約100n m之膜層2 0形成於金屬内連線介電層3 0之 中,以做為上層導線溝渠之蝕刻終止層2 0 »其中廣為使用 之蝕刻終止層有氮化矽層,或碳化矽層。不管是那一種, 當形成於上述CVD LOW K介電層30上時其接合性都不佳, 特別是當需要進行化學/機械式研磨的製程時,更明顯可 以發現,接合性不好的嚴重性。 基於上述問題與傳統解決方法的不理想’本發明 '將提 供一嶄新之方法。 為此’傳統方法通常都會以〇 2電漿處理以改善蝕刻終 止層和金屬内連線介電層之間的接合性問題,不過,習知 技術’雖解決了上述接合性問題,但卻會對金屬内連線介 電層之介電常數造成衝擊。通常處理過之介電常數會由2, 95上升至3.1-3.15。換言之’傳統方法會犧牲了金屬内連 線介。電層之介電常數。此外,如果以較高的溫度,例如 400C處理約120秒後’常會造成過度氧化,接合性又.會變 差° ^些問題急待加以解決。However, as shown in FIG. 1, in the dual damascene process, a film layer 20 of about 100 nm in thickness is usually formed in the metal interconnect dielectric layer 30 to stop the etching of the upper wire trench. Layer 2 0 »Among the widely used etch stop layers is a silicon nitride layer or a silicon carbide layer. Regardless of which type, the bonding properties are not good when formed on the above-mentioned CVD LOW K dielectric layer 30. Especially when a chemical / mechanical polishing process is required, it is more obvious that the bad bonding properties are serious. Sex. Based on the above-mentioned problems and the unsatisfactory of traditional solutions, the present invention will provide a new method. For this reason, the traditional method is usually treated with a 02 plasma to improve the bondability between the etch stop layer and the metal interconnect dielectric layer. However, although the conventional technology solves the above bondability problem, it will Impact on the dielectric constant of the metal interconnect dielectric layer. Normally, the dielectric constant will be increased from 2, 95 to 3.1-3.15. In other words, the traditional method sacrifices metal interconnects. The dielectric constant of the electrical layer. In addition, if it is treated at a higher temperature, such as 400C for about 120 seconds, it will often cause excessive oxidation and the bonding will deteriorate. Some problems need to be solved urgently.
第5頁 447077 五、發明說明(3) 發明目的及概述: 本發明目的係提供一種具有改善化學氣相沉積之低介 電常數介電層與形成於其上之碳化矽層或氮化矽層或氮矽 氧化層其中之一之接合特性之方法,更特別的是本發明之 方法處理後也不會提高該介電層之介電常數。因此,對於 不管是雙鑲嵌製程,或者是銅製程,或者兩者皆是,都可 有效改善其阻值也可以降低因接合不佳造成剝落或電阻急 遽升高之問題。Page 5 447077 V. Description of the invention (3) Purpose and summary of the invention: The purpose of the present invention is to provide a low-k dielectric layer with improved chemical vapor deposition and a silicon carbide layer or a silicon nitride layer formed thereon. Or the method of bonding characteristics of one of the nitrogen-silicon oxide layers, and more particularly, the method of the present invention does not increase the dielectric constant of the dielectric layer after processing. Therefore, whether it is a dual damascene process, a copper process, or both, it can effectively improve the resistance value and reduce the problems of peeling or sudden increase in resistance caused by poor bonding.
I 本發明揭露一種化學氣相沉積之低介電常數介電層接 合特性法改善的方法,特殊是與碳化矽層或氮化矽層或氮 矽氧化層或氮化钽其中之一種之接合特性之改善。本發明 之方法,對於具有化學氣相沉積之低介電常數介電層有碳 摻雜的介電層,都有明顯改善之效果。例如二甲基矽烷 (dimethylsilane)、三甲基石夕烧(trimethylsilane)及正 甲基石夕烧(tetramethylsilane)其中之一種。首先是將介 電層先經過電漿處理後再形成碳化矽層或氮化矽層或氮矽 氧化層其中之一種於底材上。本發明係藉由N2、Ar及He 其中一種降低氧濃度或N 20濃度之氣體混合做為電漿氣體 處理該介電層以改善接合特性。上述混合氣體可以適用於 4 0 0°C的處理環境。此外,若以純氧氣體處理時,必須要 降低電漿處理之溫度,例如1 7°C附近,也可以達到接合性 提高之效果。I The present invention discloses a method for improving the bonding characteristics of a low dielectric constant dielectric layer by chemical vapor deposition, in particular, bonding characteristics with one of a silicon carbide layer, a silicon nitride layer, a silicon nitride oxide layer, or a tantalum nitride. Its improvement. The method of the present invention has a significant improvement effect on a carbon-doped dielectric layer having a low dielectric constant dielectric layer having chemical vapor deposition. For example, one of dimethylsilane, trimethylsilane and tetramethylsilane. First, the dielectric layer is treated with a plasma before forming one of a silicon carbide layer, a silicon nitride layer, or a silicon nitride oxide layer on the substrate. In the present invention, the dielectric layer is treated by using a gas mixture of one of N2, Ar, and He to reduce the oxygen concentration or the N20 concentration as a plasma gas to improve the bonding characteristics. The above mixed gas can be used in a processing environment of 400 ° C. In addition, when treating with pure oxygen gas, it is necessary to lower the temperature of the plasma treatment, for example, around 17 ° C, and the effect of improving the bonding can also be achieved.
第6頁 447077Page 6 447077
五、發明說明(4) 發明詳細說明: 有鑑於如發明背景所述,做為金屬内連線介 CVD LOW K材料雖然可以改善RC延遲的問題,層^V. Description of the invention (4) Detailed description of the invention: As described in the background of the invention, although the CVD LOW K material can be used to improve the problem of RC delay as a metal interconnector, the layer ^
潛藏著對製程不利的問題,例如在進行雙鑲嵌製:瞎部: 於進行雙鑲嵌製程時必須形成姓刻終止層,以;::思由 和導線溝渠同時形成時避免過度蝕刻的指標。然:= 是常用的CVD LOW K金屬内連線介電層··例如正甲基碎貌' (tetramethy lsi Une)等具有碳摻雜的介電層卻對二 : 石夕層或氮化矽層或氮矽氧化層等常用之蝕刻終止層有 性(adhesion)不良的問題。 α 發明人發現,為解決上述接合問題,實有必要了解造 成接合性不佳的原因’以及何以傳統以〇2電漿處理時會^ 成介電層之介電常數升高的原因。圖二所示之曲線1〇〇^ 以傅利葉轉換遠紅外線分析(FT I R)頻,譜分析未經任何特'別 處理的正甲基矽烷介電層(例如〇2電漿處理或本發明之處 理時)結果’在波數分別為2 950 cm—1、1 250cm-1、80 處分別有一個峰值對應於C -Η鍵、Si-CH鍵及Si -C鍵的鍵 結。相同的介電層經過傳統之〇 2電漿處理後,FT I R頻譜分 析曲線11 0中新增加一山丘波形,對應於S i - 〇 Η鍵的形成及 另一出現於1 530 cnr對應於〇0(碳氧雙鍵)的位置,同時 對應於C-Η鍵、Si-CH鍵及Si-C鍵的峰值則明顯降低。There are hidden disadvantages to the manufacturing process, such as in the dual-damascene system: blind parts: when the dual-damascene process is carried out, a last name engraving termination layer must be formed in order to avoid over-etching when thinking about the formation of the wire trenches. However: = is a commonly used CVD LOW K metal interconnect dielectric layer, such as carbon-doped dielectric layers such as tetramethy lsi Une, but the second: Shi Xi layer or silicon nitride Layer or silicon nitride oxide layer and other commonly used etch stop layers have poor adhesion. α The inventors have found that, in order to solve the above-mentioned bonding problems, it is necessary to understand the reasons for the poor bonding properties' and the reason why the dielectric constant of the dielectric layer is increased when conventionally treated with a 02 plasma. The curve shown in Fig. 2 is analyzed by Fourier transform far infrared analysis (FT IR) frequency, and the n-methyl silane dielectric layer (such as the 02 plasma treatment or the When processing) Result 'At the wave numbers of 2 950 cm-1, 1 250 cm-1, and 80, there is a peak corresponding to the C-C bond, Si-CH bond, and Si-C bond respectively. After the same dielectric layer was treated with traditional 〇2 plasma treatment, a new hill waveform was added to the FT IR spectrum analysis curve 110, corresponding to the formation of the Si-〇Η bond and another appeared at 1 530 cnr corresponding to The position of 〇0 (carbon-oxygen double bond), meanwhile, the peaks corresponding to C-Η bond, Si-CH bond, and Si-C bond were significantly reduced.
第7頁 447077 五'發明說明(5) 根據以上的事實,發明人認為傳統〇2電漿處理CVD L 0 W K金屬内連線介電層所產生的碳氧雙鍵及si-〇 鍵可能 係造成介電常數上升的原因。而對應於C - η鍵、S i - C Η鍵 及S i - C鍵的鍵結的峰值則可能是破壞接合性的原因之—。 換言之,CVD LOW K金屬内連線介電層中的碳含量過高是 使得接合性變差的主要原因。除此之外,傳統方法中以含 氧電漿在較尚溫的環境產生過度氧化的碳氧雙鍵也會使接 合性變差。因此,本發明嗜試以降低氧漠度對cyp LOW K 金屬内連線介電層進行處理,以第一較佳的實施例為例, 係以Nz/0羅合氣體做為電漿處理氣體,其中〇2/n疯量比控 制在小於4 ’在約3 0 0 - 4 0 Ot:,射頻功率控制於5 〇 〇至1 〇 〇 〇 瓦以進行處理,為防止過度氧化,約2〇_6〇秒即可。 依據本發明之方法電漿處理介電層,再形成蝕刻終止 層材料或阻障層材料都可以顯著改善上述二層材料之間的 接合性。圖示之F T I R頻譜分析曲線1 2 0,即為依據本發明 之方法電槳處理後的介電層之分析結果。在對應於c_H 鍵、Si-CH鍵及si-C鍵峰值強度都明顯降低。其次對應於 Si-0H鍵的峰值及另一出現於153〇 cm-對應於c = 〇(碳氧雙 鍵)的峰值則已消失β再檢驗經本發明方法處理過的介電 層和f化梦層或氮化矽層或氮矽氧化層之間的接合特性則 已顯著改善’更重要的是由於沒有si_〇H鍵的峰值及另— 對應於C = 〇(碳氧雙鍵)的峰值,介電常數都不會增加。Page 7 447077 Five 'invention description (5) Based on the above facts, the inventor believes that the carbon-oxygen double bond and si-〇 bond produced by the conventional plasmon treatment of CVD L 0 WK metal interconnect dielectric layer may be Causes of dielectric constant rise. The peaks of the bonds corresponding to the C-η bond, the Si-C S bond, and the Si-C bond may be the cause of the deterioration of the bondability—. In other words, the excessively high carbon content in the dielectric layer of the CVD LOW K metal interconnect is the main cause of the deterioration in bonding properties. In addition, the traditional method uses oxygen-containing plasma to generate excessively oxidized carbon-oxygen double bonds in a relatively warm environment. Therefore, in the present invention, the dielectric layer of the cyp LOW K metal interconnect is treated by reducing the oxygen inertia. Taking the first preferred embodiment as an example, Nz / 0 Luo gas is used as the plasma treatment gas. In which, the 〇2 / n crazy amount ratio is controlled to be less than 4 ′ at about 300-400 Ot :, and the RF power is controlled at 5000 to 1,000 watts for processing. In order to prevent excessive oxidation, about 2〇 _60 seconds. Plasma treatment of the dielectric layer according to the method of the present invention, followed by the formation of an etch stop layer material or a barrier layer material, can significantly improve the bondability between the above two layers of materials. The F T I R spectrum analysis curve 12 shown in the figure is the analysis result of the dielectric layer processed by the electric paddle according to the method of the present invention. The peak intensities corresponding to the c_H bond, Si-CH bond, and si-C bond were all significantly reduced. Secondly, the peak corresponding to the Si-0H bond and another peak at 1530 cm-corresponding to c = 0 (carbon-oxygen double bond) have disappeared. Layer or silicon nitride layer or silicon nitride oxide layer has significantly improved the bonding characteristics' more importantly because there is no peak of the si_〇H bond and the other — corresponding to the peak of C = 0 (carbon-oxygen double bond) , The dielectric constant will not increase.
第8頁 447077 五、發明說明(6) 此外’本發明之方法不只是適用於正曱基矽烷,其他 具有碳摻雜之CVD LOW K介電層也適用,例如對於二甲基 矽烷(dimethylsilane)、三甲基矽烷(trimethylsilane) 等利用CVD方法沉積的介電層也同樣適用β且可以擴大使 用於例如銅製程,常用以隔絕銅和CVD LOW Κ介電層接觸 的阻障層TaN的接合性不佳的問題。 除了上述實施例中以N2/〇禺合氣體做為電漿處理氣體 外’其他電漿氣體凡可以降低〇濃度的Ar/Ο緙合氣體、 心/0滿合氣體、1^/]^20混合氣體、41'/1^0混合氣體等等氣 體都可以。 發明人更發現,以純0 2電漿處理氣體,一定要避免使 用商溫例如約4 0 0 C的環境’以一較佳的實施例而言,約 3 5°C以下’在1 7至3 5°C以下的低溫處理更為理想。當以〇 2 為主要氣體而Ar或He為攜帶氣體,則〇釣濃度都應降低, 例如0和上述攜帶氣體流量比值應降至4以下^此外,以 N 2〇為主要氣體而He或A r為攜帶氣體時也都是不錯的選 擇。其t Νβ為主要氣體而“或ne為攜帶氣體,則n2〇的濃 〇 度和上述攜帶氣體流量比值應降至4以下。 以上所述僅為本發明之較佳實施例而已,並非用以限 定本發明之申請專利範圍;凡其它未脫離本發明所揭示之 ir- 4 4 7 0 7 7 五、發明說明(7) 精神下所完成之等效改變或修飾,均應包含在下述之申請 專利範圍内。Page 8 447077 V. Description of the invention (6) In addition, the method of the present invention is not only applicable to n-fluorenyl silane, but also other CVD LOW K dielectric layers with carbon doping, such as dimethylsilane Dielectric layers deposited by CVD, such as trimethylsilane, trimethylsilane, etc., are also suitable for β and can be expanded to be used in copper processes, for example. The barrier properties of the barrier layer TaN that is commonly used to isolate copper from CVD LOW κ dielectric layer contact Poor question. In addition to the above examples, N 2/0 mixed gas is used as the plasma processing gas. Other plasma gases can reduce the concentration of Ar / 0 mixed gas, heart / 0 full gas, 1 ^ /] ^ 20 Mixed gas, 41 '/ 1 ^ 0 mixed gas, etc. are all acceptable. The inventors have further found that when treating the gas with pure 02 plasma, it is necessary to avoid using an environment with a commercial temperature such as about 4 0 C. 'In a preferred embodiment, the temperature is below about 3 5 ° C' is between 17 and 3 Low temperature processing below 5 ° C is more ideal. When 〇2 is the main gas and Ar or He is the carrier gas, the concentration of 〇fishing should be reduced, for example, the ratio of 0 and the above-mentioned carrier gas flow rate should be reduced to less than 4 ^ In addition, N 2 0 is the main gas and He or A r is also a good choice when carrying gas. Where t Νβ is the main gas and “or ne is the carrier gas, the concentration of n20 and the ratio of the above-mentioned carrier gas flow rate should be reduced to less than 4. The above is only a preferred embodiment of the present invention and is not intended to Limit the scope of the patent application for the present invention; all other equivalent changes or modifications that do not depart from the ir-4 4 7 0 7 7 disclosed in the present invention (7) should be included in the following applications Within the scope of the patent.
liiB 第10頁 447077 圖式簡單說明 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述: 圖一係雙鑲嵌製程之半導體結構的橫截面示意圖。 圖二顯示以FT I R頻譜分析化學氣相沉積法沉積之正甲 基矽烷未經處理、以純氧電漿處理在4 0 0°C處理及以降低 氧濃度之電漿處理後三種情況下之頻譜分析結果比較圖。liiB Page 10 447077 Brief description of the drawings The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: Figure 1 is a schematic cross-sectional view of a semiconductor structure in a dual damascene process. Figure 2 shows the frequency spectrum of the three cases of n-methylsilane deposited by chemical vapor deposition using FT IR spectrum analysis, untreated, treated with pure oxygen plasma treatment at 400 ° C, and plasma treated with reduced oxygen concentration. Comparison of analysis results.
第11頁Page 11
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TWI424498B (en) * | 2006-03-31 | 2014-01-21 | Applied Materials Inc | Method to improve the step coverage and pattern loading for dielectric films |
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