TW432510B - Method for producing device having wavy titanium silicide - Google Patents

Abstract

A method for forming a semiconductor device of a wave titanium salicide on the surface of a gate electrode, source region and drain region, comprises at least: providing a silicon substrate formed with a semiconductor structure thereon, the semiconductor structure including a gate electrode, a source region and a drain region; forming a wavy polysilicon layer on the surface of the gate electrode, source region and drain region; sputtering a titanium metal layer on the whole wafer surface, particularly on the polysilicon layer; forming a titanium nitride layer on the titanium metal layer to prevent the titanium metal layer from oxidation; annealing the titanium metal layer to form a wave titanium salicide on the gate and the source/drain region; removing the titanium nitride layer, the unreacted titanium metal and the titanium reactant other than the titanium silicide; and further annealing the titanium silicide to convert it into a C54 phase structure.

Description

43 25 1ο V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor structure capable of forming titanium self-aligned silicide (titanium salicide). The present invention relates particularly to a method having The manufacturing method of the wave-type self-aligning semiconductor device for sanding can avoid thin line effect. 5-2 Background of the Invention: With the development of integrated circuit technology, the size of components is gradually shrinking, making the capacity per unit wafer area larger, at the same time speeding up the operation speed of components, and improving the performance of components. But when the process technology reaches below 0.25 microns, the time delay caused by the interconnect will become the most important factor affecting the operating speed of the component, the capacity of the unit area, the reliability of the product, and the yield rate. At a component size of 0.25 micron, a component speed delay of 50% ′ will come from the RC time delay. The time delay caused by the interconnection is the product of the resistance value (R) of the wire and the capacitance value (C) of the dielectric layer between the wires. Therefore, using a metal with a lower resistance value as the wire can reduce the interconnection The time delay of the line accelerates the operation speed of the component and improves the performance of the component. Current process technology uses self-aligned salicide to reduce the resistance of the wire. Self-aligned silicides are formed by reacting silicon with precious metals ’and are widely used. Especially in metal oxide semiconductor transistors,

Page 4 43 25 1 0 V. Description of the invention (2) Form a layer of self-aligned silicide on the polysilicon gate electrode, source region and drain region 'to increase the electrical contact between the silicon and the metal connection.

Metal drinks are currently the most commonly used in integrated circuit technology to form self-aligning silicide metals. However, when entering the element size or smaller generation of 0.18 microns, due to geometrical constraints, the self-aligned titanium silicide can no longer reduce the resistance values of the gate electrode, source region, and non-electrode region. Because the sheet resistance is inversely proportional to the gate length, when the line size is reduced to 0.18 microns or less, the sheet resistance will become very large, and this phenomenon is generally called " fine line effect ( thiη 1 ine effect) ". Please refer to the first figure, 'a conventional semiconductor element 10 is formed on the shixi substrate 12, and the thin line effect is generated at the gate electrode 6 and the source / drain region 18' After the titanium self-aligned silicide is formed on the semiconductor device, the semiconductor device 10 further includes an insulating region 20, a sidewall 22, and a gate oxide layer 24. The titanium self-aligns the curved portion of the silicide 14 to the conductive side and There is not much contribution 'when the line width is large', the effect of this curved part is not great, but when the line width enters the deep submicron, 'this curved part will seriously affect the effective line width of the device. The reduction of line width' Make the chip Value becomes greater, and increase the time delay, the speed reducing element.

In addition to the self-aligned titanium compound, the self-aligned sand compound has also been studied for gate electrode and source / dead regions to reduce chip resistance. When the line width is reduced to 0.18 micrometers, cobalt self-aligned silicide appears to be the best choice to replace titanium self-aligned silicide. However, the drill aligns itself with the hair product

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V. Description of the invention (3) Incompatible with the integrated circuit manufacturing process of Meizuru 11 5-3 Purpose and summary of the invention: The present invention provides a semiconductor which can increase the contact area between self-aligned titanium silicide and silicon layer. The device manufacturing method avoids the occurrence of thin line effects. The process of making plutonium self-aligned with silicide can continue to be applied to the deep sub-micron generation. An example of the present invention is to form a polycrystalline silicon layer on the surface of the gate electrode, the source region and the non-electrode region to form a wavy titanium self-aligned silicide. The effective line width of a device with a wavy titanium self-aligned silicide on the gate electrode is larger than the effective line width of a device with a conventional titanium self-aligned silicide on the gate electrode. Therefore, it is possible to solve the problems of the fine-line effect and high resistance of the self-aligned silicide. The silicon substrate structure of the upper and drain conductor elements includes: a gate, a conductive layer on the gate electrode, and a metal barrier layer is sputtered to remove the object; the invention provides a method for forming a wave on one side, and forming the same At least one semiconductor source region and one electrode region above the wafer table are not reacted. The above-mentioned one is provided for the half of the source region compound; forming one degree; and subsequently the manufacture of the watch region of the target region of the metal is described below. The upper electrode, the electrode, and the source layer are all on the barrier layer of the metal layer, and finally, return to the surface of the drain region, especially; tempering the metal and the metal silicon seed in the gate type include the following step structure , The surface of the drain region is at the metal-conducting layer and the metal silicide at the first alignment step: the first semiconductor; forming; a temperature other than the first temperature on the electrical connection layer

43 25 1 〇 5. Description of the invention (4). Figure 5-4 is a simple explanation: The first figure is a schematic cross-sectional view of a semiconductor structure with a conventional titanium self-aligned silicide. The second A to G diagrams are schematic cross-sectional flow diagrams of the preferred embodiment of the present invention. Representative symbols of main parts: 1 0 conventional semiconductor elements 12 silicon substrate 1 4 titanium self-aligned silicide 1 6 gate electrode 1 8 source / drain region 2 0 insulation region 2 2 sidewall 2 4 gate oxide layer 2 0 0 Semiconductor structure 2 1 0 Inter electrode 2 1 5 Source region 2 2 0 Drain region

4-3 25 1 〇 5. Description of the invention (5) ----- 2 2 5 Insulation area 2 3 0 Side wall 235 Gate oxide layer 240 Polycrystalline silicon layer 245 Titanium metal layer 2 5 0 Gasification layer 255 Phase state C49 The detailed description of the invention of the titanium silicide structure of the titanium silicide structure 260 phase C54: Please refer to the second diagram A to the second diagram G ', which is a schematic cross-sectional flow chart of a preferred embodiment of the present invention. These figures only show the main steps of the process of the present invention in sequence. '' Referring to FIG. 2A, the present invention first provides a Shixi substrate 200, on which a semiconductor structure 200 has been formed, and the semiconductor structure 20 () includes two polycrystalline stone gate electrodes 21 0 , A source region 2 15 and a drain region 22 o. The semiconductor structure 2000 further includes an insulating region 2 2 5, a sidewall 2 3 0, and a gate oxide layer 235. The insulation region 225 may be a field oxide layer or a shallow trench isolation (STI), and the entire circle is cleaned (pre_ciean) before proceeding to the next step.

43251 05. Description of the invention ⑹ After the wafer is cleaned, a polycrystalline silicon layer 240 is formed on the exposed surfaces of the polycrystalline silicon gate electrode 210, the source region 215, and the drain region 22 as shown in the second B diagram. on. Polycrystalline silicon layer 240 contains selective hemispherical grain (s ~ HSG) Shi Xi 'This selective hemispherical grain silicon 240 is produced by low pressure chemical vapor deposition (LPCVD) at 500 ° C to 600 ° C The temperature range of Fangyuan Park is formed by the conversion of amorphous silicon (polymorphous silicon) into amorphous silicon (poly-Si), and its thickness ranges from about 300 angstroms to 600 angstroms. Θ Please refer to FIG. 2C again. A titanium metal layer 245 is used on the entire surface of the wafer ', especially on the surface of the polycrystalline stone Xiguang 240. The titanium metal layer 245 is deposited by magnetron DC sputtering, and its thickness is between 200 and 1000 angstroms. Then, as shown in the second figure d ', a layer of titanium nitride 250 with a thickness between 500 Angstroms and 150 Angstroms is formed over the titanium metal layer 245, which is used to prevent the titanium metal layer 245 Carry out oxidation. In addition, the 'titanium nitride layer 250 is formed by a method of nitrided metal titanium or a reaction during a sputtering process. Please refer to the second figure E. The titanium metal layer 245 is subjected to the first rapid thermal process (RTP) treatment in a temperature range of 400 ° to 700 °. A titanium metal silicide structure 255 in a phase state of C49 is formed on the gate electrode 210, the source region 215, and the drain region 220. After the titanium metal silicide of C49 is formed, the titanium nitride layer is removed by dry etching. The reaction gas system of the dry etching method is selected from

Page 9 4325 1 Ο _ V. Description of the invention (7) Elements in the group consisting of BC13 / C1s, CC14 and SFe. Unreacted titanium metal and titanium reactants other than titanium silicide are also removed, but are performed by a wet etching method, and the etching solution includes a mixture of sulfuric acid and hydrogen peroxide. Thereby, the metal silicide structure 255 of the phase C49 can be exposed, as shown in the second F diagram. Finally, in the temperature range of 700 ° to 950 ° C, the titanium metal silicide of the phase C49 is subjected to a second rapid tempering step. The temperature of the second rapid tempering step is faster than the first rapid tempering step. Steps are high. In this way, the C49 titanium metal silicide with a higher resistance value is converted into a C54 phase titanium metal silicide structure 2 6 0 ′, which has a low resistance value, as shown in the second g diagram. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

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Claims (1)

6 'Application for Patent Scope 1. A method for forming a metal oxide semiconductor structure, at least comprising: providing a silicon substrate on which the semiconductor structure has been formed, the semiconductor structure including a gate electrode and a source region, And a conductive region forms a conductive layer on the exposed surfaces of the gate electrode, the source region, and the drain region; a blanket metal layer is sputtered on the entire wafer surface, especially on the surface of the wafer Forming a barrier layer over the blanket metal layer on the conductive layer; Tempering the blanket metal layer at a first temperature to form a metal silicide layer; removing the barrier layer; removing unreacted metal and metal reactants other than metal silicide; and tempering the metal silicide The layer is at a second temperature. 2. The method according to item 1 of the patent application, wherein the semiconductor structure further includes a sidewall, an insulating region, and a gate oxide layer. 3. The method according to item 1 of the patent application range, wherein the gate electrode mentioned above contains at least polycrystalline silicon. 4. The method according to item 1 of the patent application range, wherein the conductive layer includes at least selective hemispherical grain silicon. Page 11 ^ 325 1 〇 ------- VI. Application for Patent Scope 5 The method described in item 4 of the scope of patent application, in which the selective hemispherical grains mentioned above are photographed by chemical vapor deposition. Formed in a temperature range of 500 degrees to 600 degrees ". 6. The method according to item 4 of the patent application range, wherein the thickness of the selective hemispherical grain dream is about 300 angstroms and 60 angstroms. 7. The method of claim 1 in which the above-mentioned metal layer contains at least titanium. 8. The method according to item 7 of the scope of patent application, wherein the above-mentioned metal layer is deposited by magnetron DC sputtering method ', and the thickness of the metal layer is between about 2000 angstroms and 1000 angstroms. 9 · = The method according to item 丄 of the patent application range, wherein the above barrier layer includes at least titanium nitride and the thickness of the barrier layer is between about 500 angstroms and 1,500 angstroms. 1 0 _If the patent application scope number 9 is formed by a nitriding method. 11 · If the scope of application for patent No. 9 is formed by the reaction method. Item method, wherein the above-mentioned titanium nitride layer system Item method 'wherein the above-mentioned titanium nitride layer system Page 12 4325 1 〇 Sixth, the scope of patent application The method of item, wherein the range of the first temperature is 400 ° to 700 °. Among them, the above-mentioned second temperature 1 3. The method according to item 1 of the scope of patent application ranges from 700 ° to 950 °. 1) The method according to the 17th member of the scope of patent application, wherein the aforementioned metal silicide layer is formed above the inter electrode, the source region, and the drain region. 15. The method according to item 14 of the scope of patent application, wherein the step of tempering the metal lithotripsy layer described above is to convert the metal silicide from a high-resistance C49 phase to a low-resistance C54 phase. ~ 16. The method according to claim 14 of the patent claim, wherein the above-mentioned metal dream layer contains at least titanium and the value of X is an integer selected from the group consisting of 1, 2, 3, and 4. Page 13251 43. Application scope of patents --- 1 8. If the method of applying for the scope of the patent application item}, wherein the above-mentioned steps to remove unreacted metal, metal reactants other than metal silicide are wet The etching method is ordered, and the etchant of the wet etching method contains at least a mixture of hydrogen sulfate. Year 19 A method for manufacturing a semiconductor το device that can increase the contact area between the self-aligned titanium silicide and the silicon layer. It can also avoid the thin line effect and extend the application life of the self-aligned silicon. This method At least including: providing a broken substrate, a semiconductor structure has been formed thereon, the semiconductor structure includes a gate electrode, a source region, and a drain region; forming a wave-shaped polycrystalline silicon layer on the gate electrode, the source On the bare surface of the polar region and the non-polar region; forging a blanket-coated titanium metal layer on the entire wafer surface, especially on the wavy polycrystalline silicon layer; forming a titanium nitride layer on the blanket-type convergence Over the metal layer to prevent the wavy titanium metal layer from being oxidized; tempering the titanium metal layer at a first temperature to form a wavy titanium silicide on the gate electrode, the source region and the drain region Above; removing the titanium nitride layer; removing unreacted titanium metal and titanium reactants other than titanite; and tempering the titanium silicide at a second temperature which is higher than the first temperature Degree yet. Page 14 432510 6. Scope of patent application 20. According to item 19 of the scope of patent application, the structure further includes a side wall, an insulating wire = method, wherein the semiconductor junction region and a gate oxide layer described above. 21. For example, please include at least the method of polysilicon range item 19, in which the above-mentioned gate electrode 22. If you apply for the patent range of item 19, the + ^ silicon layer contains at least selective semi- 埭 -shaped crystal grains Silicon /, the above wave-shaped multi-S-shaped profit range? The method of item 22, " The selectivity half-degree range mentioned above; ^ Learn the 4-phase deposition method at a temperature of 5GG to 600 degrees, and the method of item 22 of the patent scope, wherein the above-mentioned selectivity The thickness of the half-shaped 0a silicon particles ranges between 300 angstroms and 60 angstroms. =. The method according to item 19 of the patent application range, wherein the above-mentioned titanium metal layer is deposited by the magnetron DC sputtering method, and the thickness of the titanium metal layer ranges from 200 to 200 angstroms. And ι 0 0 0 Angstroms. • The method according to item 19 of Shenjing's patent scope, wherein the thickness of the above-mentioned titanium nitride layer is between about 500 angstroms and 15,000 angstroms. 27 The method as claimed in item 26 of the scope of patent application, in which the above-mentioned titanium nitride layer is applied on page 15 6. The scope of patent application is formed by nitriding. 28_ The method of claim 26 in which the above-mentioned titanium nitride layer is formed by a reactive sputtering method. 29. The method according to item 19 of the patent application range, wherein the first temperature range is 400 ° to 700 °. 30. The method according to item 19 of the patent application range, wherein the above-mentioned second temperature range is 700 ° to 950 °. 31. The method according to item 19 of the scope of patent application, wherein the step of tempering the titanite is to convert the titanium silicide (T is L) from a high resistance C4 9 phase to a low resistance The C 5 4 phase state. 32. The method of claim 19 in the patent scope, wherein the value of X of the titanium silicide is an integer selected from the group consisting of 1, 2, 3, and 4. 33. The method of item 19, wherein the step of removing the nitrogen 5: layer described above is performed by dry etching method. 1 The reaction of dry etching method 2 is derived from the group consisting of BCl3 / C12, CC14 and SF6 Page 16 4 3 2 5 1 〇 VI. Patent Application Range 3 4. The method of item 19 of the patent application range, wherein the above-mentioned step of removing titanium reactants other than the corresponding titanium metal and titanium silicide is wet The etching method is performed. The etching solution of the wet etching method includes a mixture of sulfuric acid and peroxide. Untrans-etched