TW420844B - Method for decreasing the removing rate of polishing for low dielectric constant material - Google Patents

Abstract

The present invention discloses a method for decreasing the removing rate of polishing for low dielectric constant material, comprising the steps of: depositing a low dielectric constant material on a semiconductor substrate so as to form a dielectric layer; performing a NH3 plasma, N2 plasma or Ar plasma process to increase the density degree of the dielectric layer thereby decreasing the removing rate of polishing. With the method of the present invention, the selectivity of the chemical mechanical polishing process is increased, so as to assist the integration of the low dielectric constant material and Cu damascene process.

Description

V. Description of the Invention (1) [Field of the Invention] The present invention relates to semiconductor process technology, and in particular, to a method for reducing the grinding removal rate of a low dielectric constant material, which can improve the grinding of the inlay copper process. The selectivity enables low-k dielectric materials to be directly tuned in the application of damascene copper processes without the need for additional protective layers to increase the parasitic capacitance of the intermetal dielectric layer. [Background of the Invention] With the increasing precision and complexity of integrated circuits, in order to be able to make enough metal interconnects on a limited number of Japanese film surfaces, 'there are currently three-dimensional architecture methods using multilayer interconnects' to complete the components. They are connected, and an intermetal dielectric layer (IMD: Inter-Metal Dielectrics) is used as a dielectric material to isolate the interconnections between the metals. Materials that are used as intermetal dielectric layers in conventional techniques include: plasma enhanced oxide (pE_0X; plasma enhanced oxide) 'plasma tetraethoxy cullet (叩 _ 丁 £ 〇5; plasma enhanced tetraethyl orthosilicate glass), spin-on glass, dielectric materials with low dielectric constant (such as F0x-1 5 produced by Dow Coring Co.). In recent years, the development of the reduction in the size of components and the need to improve the speed of operation of the components < seeking 'copper metal with low resistance constant and high electron migration resistance, have gradually been used as the material of metal interconnects, replacing the previous inscription Metal process technology. Among them, copper damascene (Cu dainascene) interconnect technology can not only reduce the interconnect size, but also solve the problem of difficult copper etching, so it has become the main development trend of multiple interconnects today. On the other hand, in order to

5. Description of the invention on page 4 (2) Capacitance should be reduced as much as possible 'At present, low dielectric constant materials such as FSQ, HSQ (hydrogen silses-quioxane), and MSQ (raethyi silsesquioxane) have been used as intermetal dielectric layers. In order to reduce cross talk and RC time delay. At the end of the damascene copper process, chemical mechanical polishing is required to remove excess copper and barrier metals from the dielectric layer. However, since such low dielectric constant materials usually have a microporous structure (such as HSQ), the removal rate of chemical mechanical polishing is much higher than that of ordinary oxide layers. Therefore, during the "oxide buffing" procedure, There will be serious losses, which makes it difficult for such low dielectric constant materials to be directly used in the copper damascene process. Please refer to Figure 1 'To avoid excessive grinding, in general, the dielectric constant materials must be used. (Such as HSQ), a plasma silicon oxide layer 14 is added for protection. However, this also increases the parasitic capacitance, which leads to the increase of the RC delay time of the component and affects the operation efficiency of the product. It is urgent to propose an effective improvement [Summary of the Invention] In view of this, the main object of the present invention is to provide a

Is to provide a method to reduce the low dielectrics ’to improve the mosaic copper process.

V. Description of the invention (3) The main steps of forming a protective effect include: depositing a dielectric layer; using a procedure to increase the hard surface of the dielectric rate 0; D; and applying a nh3 electrodeposition according to the present low dielectric constant material. The method invented by the degree of sensitization of the n2 electric layer, its main '' semiconductor substrate, and the plasma or Ar plasma treatment reduces its grinding and removal rate. The above electrolysis process can benefit S-plasma chemical vapor deposition The 'better implementation' is performed by high-density plasma chemical vapor deposition (HDP-CVD). Low dielectric constant materials suitable for the present invention include: HSQ (hydrogen silses-quioxane), MSQ (methyl silsesquioxane), H-PSSQ (hydrio polysilsesquioxane) > M-PSSQ (methyl polysilsesquioxane) 'P-PSSQ (phenyl polysilsesQuioxane) , FLARE (manufactured by Allied Signal or Microwave Materials), SILK (manufactured by Dow Chemical) 'Xerogel, Nanog 1 ass, and PAE-2 o The scope of the invention further includes a low dielectric constant material as the intermetal dielectric layer The mosaic copper process is characterized in that the grinding selection ratio of the copper process is improved by the above-mentioned plasma treatment process, and the process includes the following steps: Ca) A low dielectric constant material is deposited on a semiconductor substrate to form a dielectric (B) implement an NH3 plasma or N2 plasma or Ar plasma treatment process to increase the density of this dielectric layer and reduce its subsequent grinding removal rate; (c) define an opening in the dielectric layer (D) depositing a copper metal layer on the dielectric layer and filling the opening;

Page 6 ... '/ 1 4: 诏 V. Description of the invention⑷' — and (e) removing the copper metal layer other than the opening by a chemical mechanical polishing method; wherein the above plasma treatment procedure reduces the polishing removal rate of the dielectric layer , And increase the selection rate of this grinding process. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: [Simplified description of the drawings] Section 1 The figure is a cross-sectional view for explaining a conventional mosaic copper process using a grinding protection layer. Figures 2A to 2C are a series of scraped views' for explaining a mosaic copper manufacturing process according to a preferred embodiment of the present invention. [Symbol description] 10, 20 ~ substrate and semiconductor element; 12, 22 ~ low dielectric constant intermetal dielectric layer; 1 4 ~ protective layer; 2 4 ~ barrier layer; 26 ~ copper metal layer. [Embodiment] This embodiment is applied to the steel-metal interconnection process of the inlaid structure according to the method of the present invention. For the sake of convenience, only a single inlay process is described below as an example, but those skilled in the art can also apply On a dual damascene process. Please refer to FIG. 2A, which shows the initial steps of this embodiment. The part numbered 20 may include several layers of metal interconnects and several electrical interconnections.

Page 7 V. Description of Invention (5) For semiconductor elements, such as MOS transistors, resistors, logic elements, etc., to simplify the drawings, semiconductor substrates and integrated circuit elements below the intermetal dielectric layer 22 are only labeled 2 0 represents it. The dielectric layer 22 represents a dielectric material with a low dielectric constant, such as hsq (hydrogen si 1 ses-quioxane), MSQ (methyl si1sesquioxane) 'H-PSSQ (hydrio polysilsesquioxane)' M-PSSQ (methyl po1ysi1sesquioxane) 'P -PSSQ (phenyl polysilsesquioxane), FLARE (made by Allied Signal or Microwave Materials), SILK (made by Dow Chemical) 'Xerogel' Nanoglass, and PAE-2, etc. The dielectric constant of the above materials is generally around 3, but the range can be between B4. This dielectric layer can be deposited by chemical vapor deposition (CVD), or spin coating (Ug) on the substrate 'and then cured to form a dielectric film as shown in the figure. Next, the present invention uses a NH3 plasma or & plasma or Ar plasma treatment procedure to 'densify its surface by ion bombardment' to form a hard surface (about 300 angstroms) with a protective effect, as shown in Figure 22a. . According to the present invention, the plasma treatment process can be performed by a general plasma chemical vapor deposition method, but the better one is performed by a high-density plasma chemical vapor deposition method (HDP_CVD), which can achieve a higher degree of sensitization. . As mentioned in the foregoing, "Generally, in order to avoid excessive grinding of dielectric materials with low dielectric constant in the conventional manufacturing process, at this time, it must be deposited on it-a layer of oxidized oxide as a protection", but intermetallic interlayers have been increased. Parasitic capacitance of the electrical layer,

5. Description of the invention (6) It is against the original intention of using low dielectric constant materials. In contrast, after the method of the present invention forms a densified surface by the above-mentioned plasma treatment, it is not necessary to deposit an additional protective layer 'to avoid an increase in parasitic capacitance. Please refer to FIG. 2B. Next, according to the traditional damascene process, first use the lithography and engraving procedures to define the trenches for the metal interconnects in the dielectric layer 22, and then perform a comprehensive deposition 'to interconnect A barrier layer 24 is formed at the bottom and the sidewall of the wire trench. This barrier layer can help the subsequent metal adhesion and prevent its diffusion. For copper, the appropriate diffusion barrier material includes: group (Ta), nitrided chain (TaN), nitrided crane (WN) or Titanium gasification (TiN) and other commonly used processes. Next, a copper metal layer 18 is deposited on the barrier layer by a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), or an electroplating method, and the copper metal layer 18 is filled to fill the barrier ribs. groove. Preferably, an ionized metal plasma (IMP) can be first deposited on the substrate-a seed layer having a thickness of about 300 to 1500 angstroms, and then a copper conductive layer can be deposited by electroplating. Generally, the deposition process of the barrier layer and the seed layer can be completed sequentially in different chambers of the multi-chamber reaction chamber without breaking the vacuum, thereby improving the reliability and productivity of the process. After the deposition of the barrier layer and the copper metal layer is completed, it is planarized by a chemical mechanical polishing method, and the copper metal layer and the barrier layer other than the interconnect trenches are removed to obtain the structure shown in FIG. 2C. The grinding process includes: copper metal grinding, barrier layer grinding, and the last oxide buffing process, where each stage uses a different grinding slurry. To prove that the method of the present invention is indeed feasible,

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V. Description of the invention (7) The grinding rates of HSQ and two plasma-treated HSQs are listed in Table 1: Comparison of Table 1: 1 Materials to be polished CuCMP TaN CMP Ox CMP (30 sec) OxCMP (15sec) Rate (A / min ) Rate (A / miri) Rate (A / min) Rate (A / min) Cu 2857 49 268 — TaN 103 263 470 — HSQ + 127 858 5230 4903 HSQMH3 * 49 121 4 ^ 48 3448 HSQ / N2 ^ 37 2496 1044 T HSQ processed by electricity; 'HSQ processed by NH3 electricity;

** HSQ processed by HDP-CVD N2 electric mass processing

Cu CMP- HSQ: HSQ / NH3: HSQ / N2 = 3: 1: 1: TaN CMP-HSQ: HSQ / NH3 = 7: 1 Ox CMP 30 sec-HSQ: HSQ / NH3: HSQ / N2 = 5: 4: 2 Ox CMP 15 sec-HSQ: HSQ / NH3: HSQ / N2 = 5: 3: 1: 1 As can be seen from the above, the densified surface formed by plasma treatment can indeed effectively slow down the polishing rate of low dielectric constant materials, especially The HSQ of HDP-CVD N2 plasma treatment has reduced the grinding rate to 1/5 of the original, which is of great help to the integration of low dielectric constant materials and inlaid copper process 6

Page 10 np. A ^; ^ V. Description of the invention (8) Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the present invention. Within the spirit and scope, various modifications and retouching can be made. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

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Claims (1)

^ Month > 丨 Day «snn. ^ NQ, patent application scope ^ 1 'A method for reducing the grinding removal rate of a low dielectric constant material, including the following steps: Depositing a low dielectric constant material on a semiconductor A dielectric layer is formed on the substrate; and a NH3 plasma or Nz plasma or Ar plasma treatment procedure is performed to increase the density of the " electric layer and reduce its removal rate. 2. The method according to item 1 of the scope of patent application, wherein the low dielectric constant material is selected from the group consisting of: HSQ (hydrogen si1sesquiοχane) 'MSQ (methyl si 1 sesquioxane) x H-PSSQ (hydrio po1ysi1sesquioxane) ) 'M-PSSQ (methyl polysilsesquioxane), P-PSSQ (phenyl polysUsesquioxane)' FLARE, SILK 'Xerogel, Nanoglass, and PAE-2 ° 3. The method described in item 2 of the scope of patent application, wherein the low dielectric Constant materials are deposited on the substrate by chemical vapor deposition or spin coating. 4. The method according to item 1 of the scope of the patent application, wherein the low dielectric constant material is HSQ (hydrogen silsesquioxane). 5. The method according to item 1 of the scope of patent application, wherein the plasma processing procedure is performed by a plasma chemical vapor deposition method or a high-density plasma chemical vapor deposition method. 6. The method described in item 1 of the scope of the patent application, wherein the plasma treatment process is performed using a high density plasma chemical vapor deposition method of N2 plasma. 7. — A mosaic copper process using a low dielectric constant material as the intermetal dielectric layer, including the following steps: Page 12 __ Case No. 88110309 Six 'Shenjing Patent Scope Formed on a semiconductor substrate—dielectrically depositing a low dielectric constant material on the electrical layer and applying the -nh3 electropolymerization or n2 plasma or Ar electropolymerization process to increase the density of the dielectric layer and reduce its subsequent grinding Removal rate; defining an opening in the dielectric layer; depositing a copper metal layer on the dielectric layer and filling the opening; and removing a copper metal layer outside the opening by a chemical mechanical polishing method; wherein the plasma is The processing procedure reduces the polishing removal rate of the dielectric layer and increases the selection rate of the polishing procedure "8. The process as described in item 7 of the scope of patent application, wherein the low dielectric constant material is selected from the following composition Ethnic groups: HSq (hydr〇gen si 1 sesquioxane) 'MSQ (methyl si 1 sesquioxane)' H-PSSQ (hydrio polysiisesquioxane) 'M-PSSQ (methyl polysilsesquioxane)' P-PSSQ (phenyl polysiisesquioxane), FLARE, SILK, Xerogel, Nanoglass and PAE-2. 9. The process according to item 8 of the scope of patent application, wherein the low dielectric constant material is deposited on the substrate by a chemical vapor deposition method or a spin coating method. 10. The process as described in item 7 of the scope of patent application, wherein the low dielectric constant material is HSQ (hydrogen silsesquioxane). 11. The process according to item 7 of the scope of the patent application, wherein the plasma processing procedure is performed by a plasma chemical vapor deposition method or a high-density plasma chemical vapor deposition method. Page 13 Case No. 88110309 Amendment 6. Scope of patent application 12. The process described in item γ of the scope of patent application, wherein the plasma treatment process is performed by high-density plasma chemical vapor deposition (% V) plasma. 13. The process according to item 7 of the scope of patent application, wherein before depositing the copper metal layer, further comprising: depositing a barrier layer on the bottom and sidewalls of the opening. 14. The process according to item 13 of the scope of patent application, wherein the material of the barrier layer is selected from the group consisting of: titanium nitride (TiN), tantalum (Ta), nitride button (TaN), And tungsten nitride (WN).