TW426972B - Method of forming the extending junction of source/drain by using Si-B layer in fabricating complementary metal oxide semiconductor field effect transistor - Google Patents

Abstract

This invention is about the fabrication method of complementary metal oxide semiconductor (CMOS) field effect transistor and includes the following procedures. The gate pattern of a p-type metal oxide semiconductor field effect transistor (MOSFET) and the gate pattern of an n-type MOSFET are formed on p-type semiconductor substrate and n-type well region. An n<SP>-</SP>-type dopant is implanted in order to form an n<SP>-</SP>-type lightly doped source/drain. The first dielectric layer is deposited on p-type semiconductor substrate and n-well region. The second defined photoresist layer is formed on the first dielectric layer. After that, the first etching is performed onto the n-well region to etch one part of the first dielectric layer. During one part of the first etching process period for the first dielectric layer, a compensation spacer is formed on n-well region. A silicon-boron (Si-B) layer is deposited on n-well region and the first dielectric layer. The Si-B layer is oxidized to form the boron silicon glass layer. The first diffusion of boron atoms into n-well region is performed to form a p<SP>-</SP>-type lightly doped source/drain. The second dielectric layer is deposited on the boron silicon glass layer. The first layer of boron silicon glass spacer and the second layer of boron silicon glass spacer are formed by etching one part of the second dielectric layer and one part of the boron silicon glass layer, and the second etching of one part of the first dielectric layer. Then, an n<SP>+</SP>-type heavily doped source/drain is formed in p-type semiconductor substrate. A p<SP>+</SP>-type heavily doped source/drain is formed in n-well region. Finally, the first layer of boron silicon glass spacer is annealed. The second diffusion of boron atom into the region under the first layer of boron silicon glass spacer is performed to form an extending junction of source/drain into a p-type MOSFET.

Description

V. Description of the invention (1) 5-1 Field of the invention: 426972 * The present invention relates to a method for manufacturing a complementary metal-oxide-semiconductor field-effect transistor (CMOS), and more particularly to a method for manufacturing a complementary metal-oxide-semiconductor half-field-effect transistor. A method for forming a source / drain extension interface using a silicon-boron layer (Si-β iayer). 5-2 Background of the Invention:

Recently, as ultra-large scaU integration (ULSI) is formed on a semiconductor substrate with attractive semiconductor technology, the density of the integrated circuit on a single wafer has increased. As a result of the increase in the density of the integrated circuit, the size of individual components is reduced, and the density of the component group is increased. Recently, innovations in high-resolution lithography technology, non-equivalent technology, etching technology, and other semiconductor technologies have made significant progress. It is worse to reduce the size of components. However, higher electrical power is required in the future. Conductor technology and additional requirements for electronic components. Select and attack a metal-oxide-semiconductor field-effect transistor (M0SFET) ___ = Known ^ In general, on a relatively thin gated layer, put = silicon metal (p0lysUicOn) material to manufacture : of. After the polycrystalline silicon metal material and the thin oxygen q pattern are completed, a gate conductor is formed, and the gate conductor is adjacent to the source / ^

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V. Description of the invention (2) After wearing # 6U., Implant a material doped with impurities, ☆ gate conductor and source / drain electrode. If an impurity-doped material is used to form an n-type source / drain region, the resulting metal-oxide-semiconductor field-effect transistor is called an n-type metal-oxide-semiconductor field-effect transistor π (n-channel). In contrast, if impurity-doped materials are used to form a P-type source / drain region, the resulting gold-alloy half-field-effect transistor is called a P-type metal-oxide half-field-effect transistor element (ρ channel). The photolithography technique forms a gate conductor and adjacent source / drain regions. Through a thick field oxide layer, gate conductors and source / drain regions appear in the window. Those windows' forming the transistor are called active regions. Therefore, the range of the active region is between the field oxide layer. Above the field oxide layer, an internal interconnect is arranged to connect the polycrystalline silicon gate conductor and the source / non-electrode area, thereby forming a complete circuit structure. Gastric integrated circuits use η-channel elements, ρ-channel elements, or both components on a single substrate. When forming both types of elements, basically the elements must be implanted with source / drain regions of different doped impurities. Implanting n-type impurities in the source / drain region forms an n-channel element, and implanting p-type impurities in the source / drain region forms a p-channel element. The only problem is related to each element. Such an increase in density will make the problem worse. The component is found to be defective, and the process parameters and process steps can be adjusted. In most cases, due to the singularity of each type of component, the manufacturing process of the η channel is not

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V. Description of the invention (3) The process of the 4 channel ° First, the process of the n channel is discussed first, and then the process of the ρ channel is discussed. The η channel element is particularly sensitive to the so-called short channel effect. The distance between the source and ί and the electrode region is usually based on the actual channel length. However, the distance between the source and the drain region after the ion implantation and diffusion process becomes Less than the actual channel length. This is called the effective channel length (ef fee ti ve channel 1 en gth). In the design of very large integrated circuits, the actual channel becomes shorter, making the short channel effect a more obvious Problem 0 Generally speaking, the short-channel effect will affect the operation of the device, thereby reducing the threshold voltage (threshold vo 1tage) and increasing the sub-threshold current of the device. As the effective channel length becomes very short, the empty region opposite the source and drain regions can be extended forward to the other end, resulting in the actual channel region. Therefore, some channels will be partially empty, so there is nothing to the gate voltage. Effect 0 This result requires a lower gate charge to invert the channel with a short effective channel length transistor. Relative to the decrease of the critical voltage, the second critical current flow should also have this concept. Even when the gate voltage is lower than the threshold, the current between the source and the drain exists in the transistor ’, which has a relatively short effective channel length. However, the two main reasons for increasing the sub-5 current are the penetration.

Wu Ming (4) (drain-induced barrier in a wide drain empty area, at that time. The drain electric field may penetrate the potential barrier of the source surface. Through-current and relative to the through-current, the drain-conductive substrate surface. A drain voltage The result of this method is to control the short channel effect on the substrate surface near the channel. Fortunately, increasing substrate impurities is harmful to the Trouble, and the sigma drain leads to lowering of the barrier). The result of the penetration is derived from the supply of a reverse bias to the drain well diode region ', thereby reducing the source to substrate connection. The substrate material is connected below the substrate surface. The current caused by the barrier drop almost occurs in the application. It may cause the surface potential of the substrate to decrease. With a lower potential barrier, this will cause the subcritical current on the surface of the stone to increase. One is to increase the impurity concentration of the element substrate. It is necessary to ensure that the component increases the potential energy gradient. Increasing the potential energy gradient creates an additional effect, which is called the hot carrier effect. The phenomenon of heat carrier effect is to increase the kinetic energy of the carrier (electron or hole), accelerate through a large potential energy gradient, and then become a defect in the gate oxide layer. The maximum potential energy gradient is usually based on the maximum electric field, which occurs during near-saturation operation. In particular, the electric field effect is more pronounced 'at the lateral junction near the drain of the channel'. Taking the n-channel element as an example, the electric field generates the kinetic energy of the electrons at the drain, causing the electrons to enter the gate. Electron-electron kinetic energy is randomly scattered, making the electrons very "hot". These hot electrons have enough energy to generate electron hole pairs, which will affect the ionization of sand atoms. When the hole flows into the plate, a substrate current is generated in the component.

Page 8 is the first son of the color angle. The galvanic mass is the same as the base power of this board hole, except that the component routines are too manufactured. The Dentsu Bunsen P-based product of the elementary system is produced by XJ- 〇 ^ I (50Γ &gt; daughter body with §a off-load _ loud heat anti-extinction shadow phase ... the carrier effect occurs when some heat carriers shoot Into the drain junction = the free oxide layer 0, the heat carrier will destroy the closed electrode layer, resulting in an open electrode layer lacking k. Generally, the lack of L in the interlayer oxide layer, even though these electronic defects are initially electrical. Hole = branch; =: The accumulated time will affect the positive critical drift of the 0-channel element and the p-channel element: as far as we know, the mobility of the hot electron far exceeds that of the thermal hole. In the n-channel = and p-channel channels Among them, the heat carrier effect is caused by a huge critical oblique rod. Therefore, a P-channel element will experience a negative critical slope. In addition to modifying the structure of the transistor, sub-critical current and criticality, shift = problem, will cause The short channel effect and the heat carrier effect remain the same. For some problems, you must choose either of the drain structures to use a double-diffused drain (DDD) or a lightly doped drain (LDD). The two types of structures mentioned above have The same purpose 'is to absorb some of the poles Potential energy, with a low maximum electric field of 7. The popularity of the double-diffused drain structure has given way to a slightly doped non-polar structure. This is because the double-diffused drain can cause irreversible deep junctions and harmful junctions. Area capacitance β A traditional lightly doped drain electrode is self-aligned to a closed electrode by a low concentration of impurities, and then on two formed sidewall gaps, by

A higher quality self-aligns the gate electrode. Channels close to the edge of the gate, the use of the first implant dose produces a slightly doped cross section in both the source and drain regions. The space for the second implant dose is a distance from the channel by the thickness of the side wall gap. As a result of the first and second implants, an impurity gradient occurs at the junction between the source and the channel, as well as at the junction between the source and the channel. Properly defined lightly doped drain structures must have a minimal heat carrier effect without losing additional source / drain resistance. In addition, a simple change of the &gt; and the electrodes are implanted near the channel, unfortunately adding a resistor into the source / drain path. The added resistance, commonly called parasitic resistance, has many harmful effects. First, parasitic resistance may reduce saturation current. Second, parasitic resistance may reduce the speed of the entire transistor. Appropriately designing a lightly doped source / drain to overcome the above-mentioned problems is used to apply to n-channel transistors and p-channel transistors. However, one method will be used in the manufacturing process of complementary metal-oxide-semiconductor field-effect transistor (CMOS). Use existing process technology to manufacture complementary metal-oxide-semiconductor half-field-effect transistors. Based on many existing process technologies to 'improve complementary metal-oxide-semiconductor half-effect transistors' to achieve the desired low-resistance and ultra shallow junction complementary metal-oxide-semiconductor half-effect transistors 5-3 Purpose and summary of the invention:

Page 10 S 'V. Description of the invention (7 ^ In view of the above background of the invention, a complementary metal-oxide-semiconductor field-effect transistor (CMOS) with a low resistance (1 resistance) and an ultra shallow junction is provided. In addition, the structure of a typical complementary gold emulsion half field effect transistor includes a P-well complementary metal-oxide half-field-effect transistor (p-we 11 CMOS) and an n-well complementary metal-oxide half-field-effect transistor (p -we 1 1 CMOS), and twin-wel 1 CMOS half field effect transistor (twin-wel 1 CMOS). However, in this embodiment, only the ^ -well complementary CMOS half field effect transistor is described in detail, as for other The structures of two complementary metal-oxide-semiconductor field-effect transistors are also included. In this embodiment, the steps of this manufacturing method are as follows. First, a complementary crystal is provided on or in a single crystal silicon substrate of a P-type impurity. Region of a metal oxide half field effect transistor. Then, an n-type well region (nieli region) is formed in a p-type semiconductor substrate. Then, a p-type semiconductor substrate and a In some n-well areas, A relatively deep shallow trench isolation (STI) is formed to form a p-type metal-oxide-semiconductor field-effect transistor active region (PMOSFET active region) and an n-type metal-oxide-semiconductor field-effect transistor (= SFET active region). to? In the active region of the metal oxide semiconductor field-effect transistor and the active region of the n-type metal oxide semiconductor field-effect transistor, the shape is formed. Then, a gate oxide layer (e × 1de layer) is formed on the active region of the p-type metal-oxide-semiconductor half field effect transistor and the active region of the half-effect half transistor. Then, the gate is above the gate oxide layer (Cpolysilicon gate). Next, polycrystalline silicon gates, gates, and silicon wafers are formed, and the polycrystalline silicon gates, gates, and oxide layers are formed in the remainder of the year to form a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET gate pattern). Oxygen ρ 0 case (Rabbit Oxygen Oxide Active Crystal Active Area

Page 11 V. Above and II. Half field effect transistor gate pattern (NM0SFET gate pattern) It is said that the above half field effect transistor is above the active area. Above the p-type oxygen half field effect = $ active area and a part of the shallow trench isolation, a second layer has been formed: a photoresist layer. After that, the ⑯η-type metal-oxide half-field effect transistor is implanted in the active region and implanted with an η-type impurity, thereby forming a type 1 lightly doped source / drain. Then, the -th photoresist layer is removed. In shallow trench isolation, n-type metal-oxide-semiconductor gate pattern, p-type metal-oxide-semiconductor field-effect transistor gate pattern, n-type metal-oxide-semiconductor half-field transistor active region and p-type metal-oxide-semiconductor half-effect transistor active region Above, &gt; a first dielectric layer. A second defined photoresist layer is formed on the first dielectric layer. After that, a part of the &quot; electrical layer &quot; is etched for the first time above the active area of the p-type metal-oxide-semiconductor half field effect transistor and part of the shallow trench. Then, an offset spacer is formed over the active region of the first dielectric layer in a portion of the D-type metal oxide half field effect transistor. Then, the second defined photoresist layer is removed. On-part of the shallow trench isolation, P-type CMOS half-effect transistor active area, P-type MOSFET half-gate transistor gate pattern, compensation gap, and the first layer above the electrical layer, &gt; silicon 'Butterfly layer (siHcon ~ boron layer). The silicon oxide-boron layer forms a borosilicate glass layer, and for the first time diffuses boron atoms into the active region of the p-type gold gas half field effect transistor, thereby forming a p-type slightly doped source / drain. After that, a second dielectric layer is deposited on the borosilicate glass layer. Next, a portion of the second dielectric layer, a portion of the borosilicate glass j layer, and a portion of the first dielectric layer are etched a second time to form a first-butterfly glass spacer ( first BSG spacer) and a second borosilicate glass

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A V. Invention ^ ^-* Second BSG spacer. After that, a p-type impurity is implanted in the p-type gold gas half-field-effect electric field B-body active region to form a pj-type doped source / drain. Next, an n + type impurity is implanted in the n-type metal-oxide-semiconductor half-field-effect transistor. Active area to form an n + type heavily doped source / drain. Finally, tempering =: Shi Xi glass gap wall 'in the lower area of the first-borosilicate glass gap wall gold ί 3: Atoms to form a source / drain extension interface to ~ P type gold gas + field effect Transistor. 5 ~ 4 diagrams simple explanation: Manufacturing replenishment = =: Cheng :::: Ming symbol to the main part of the representative symbol 10 15 20 25 30 35 40 45 50 P-type semiconductor substrate n-well area shallow trench isolation channel gate N-type metal-oxide-semiconductor half-field-effect transistor gate electrode pattern, p-type metal-oxide-semiconductor half-field-effect transistor gate pattern, n-type lightly doped source / drain

Description (10) Poor / 2 The first defined photoresist layer 60 60A 65 70 80 85 90 95 100 105 110 120 500 505 The first dielectric layer The first defined photoresist layer compensates the gap stone-Butterfly layer boron Silicon broken layer P_ type lightly doped source / drain second dielectric layer first borosilicate glass spacer wall second borosilicate glass spacer wall P + type heavily doped source / drain n + type heavily doped Miscellaneous source / drain source / non-extended junction P-type metal oxide half field effect transistor active area η type metal oxide half field effect transistor active area The crystal uses borosilicate glass to form a p-split metal-oxide-semiconductor field-effect transistor source / drain extension junction. The details are described below. The structure of a typical complementary metal-oxide-semiconductor half-field-effect transistor includes a P-well complementary metal-oxide half-field P-well CMOS, η-well complementary metal-oxide-semiconductor half-field-effect transistor (p_well CMOS), and twin-well complementary metal-oxide-semiconductor half-field-effect transistor (t-well CMOS). However, in this embodiment, only the details

Page 14 (π)-~ ---------- ^ ^ Well complementary gold gas half field effect transistor 'As for the other two types of inter ^^ half field effect transistor structures are also included. The first drawings to the 0th β diagrams are cross-sectional views of a process for manufacturing a complementary metal-oxide-semiconductor half field effect transistor according to an embodiment of the present invention. According to the diagram in the first figure, a region of a complementary metal-oxide-semiconductor field-effect transistor is provided on or in a p-type single crystal silicon substrate with a &lt; 100 &gt; crystal lattice orientation. The p-type semiconductor substrate (p_type sejniconductor substrate) 10 has a concentration of less than about 1 · OE 1 5 atoms per cubic centimeter. Then 'form a 0¾ well area (n_weU regi0n) 15 and implant a dose of about 10 to 200KeV using an ion implantation procedure using phosphorus (P) as an ion source'. .〇E 12 to 丨 .EE 13 atoms'. Next, a drj ^ e_in program was used at a temperature of about 1000 degrees to form a concentration of about 10 oe / cm3 16 atoms. The n-type well region 15 ′ is above the p-type semiconductor substrate 10. Then, a relatively deep shallow trench isolation (ST Ϊ) 20 is formed around the P-type semiconductor substrate 10 and a part of the n-type well region 15 to isolate the leakage current between the element regions to form a ρ. A PMOSFET active region 500 and a n-type NMOSFET active region 5 0 5. In the active region 50 of the p-type metal-oxide-semiconductor field-effect transistor and the active region 505 of the n-type metal-oxide-semiconductor half-field-effect transistor, an ion cloth using boron (B) or boron fluoride (BF2) as an ion source is used. The implantation procedure involves implanting a dose of about 12 atoms per square centimeter at 10 KeV at an energy of about 10 KeV to form a channel 25. P-type metal oxide

(12) (12)

Area / body active area 5 0 0 and n-type metal-oxide half field effect transistor active area 505 'uses thermal oxidation, which includes a dry oxidation method (dry ox i da t ion) and A wet oxidation method forms a gate oxide layer 30. Then, on the gate oxide layer 30, a polycrystalline silicon gate (

polysilicon gate) 35, using si lane as a source gas, using low pressure chemical vapor deposition (LPCVD) technology, forming a polycrystalline silicon layer at a temperature of about 600 degrees to 650 degrees, with a thickness of about It is between 1000 Angstroms and 2500 Angstroms. Then 'etch the polysilicon gate 35 and the gate oxide layer 30' to form a P-type MOSFET half-field transistor transistor pattern (PMOSFET gate patter η) 4 5 in the active region of the p-type MOSFET half-field transistor 500. Above and an n-type metal-oxide-semiconductor half-field-effect transistor gate pattern (NM0SFET gate pattern) 40 above the active region 50 of the n-type metal-oxide-semiconductor half-field effect transistor. A first defined photoresist layer 50A is formed on the p-type metal-oxide-semiconductor field-effect transistor active region 500 and a portion of the shallow trench isolation 20. After that, in the active region 505 of the n-type metal-oxide-semiconductor field-effect transistor, an ion implantation procedure using lin (ρ) or broken (as) as an ion source is implanted at a energy of less than 30 K e V, and a dose is implanted. There are between about 1.0E 1 to 5.0 E 1 5 atoms per square centimeter, forming an n-type lightly doped source / drain 50. Then, the first defined photoresist layer 50A is removed. f According to the diagram in the third figure, isolate 20, ^ type metal oxide in shallow trenches.

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Explanation of t (13) Zai 45 combination Λ pole: Case 40, P-type metal-oxide half-field effect transistor interpole diagram 4b, n-type metal-oxide half-field effect thunder ^ field effect transistor active area 50 Said L moving area 505, and. -Type metal-oxygen semi-dielectric-concentration contains =; long,.; Redundant one first dielectric layer 60 ′, this η. + · ", Slllcon oxide, silicon nitride (•,. Γ16, or silicon oxide / silicon nitride. The deposition method and conditions are as follows. After dioxane is deposited, ethyl ethanoate (TE0s) is used as a source gas. Low-pressure two-gas j / child product (LPCVD) technology 'deposits silicon dioxide at a temperature of about 500 to 800 degrees Celsius, with a thickness of about 50 to 300 angstroms. In Shen, silicon nitride ^ •, using low-pressure chemical vapor deposition (LpcVD) technology, to deposit silicon nitride at a thickness of about 750 degrees, with a thickness of about 50 angstroms to 300 angstroms. When depositing silicon oxide / silicon nitride Using Low Pressure Chemical Vapor Deposition (LPCVD) technology 'to deposit silicon oxide / silicon nitride at a temperature of about 500 degrees to 800 degrees, with a thickness of about 10 G angstroms to 300 angstroms — According to the diagram in the fourth figure, a second defined photoresist layer 60A is formed on the first dielectric layer 60. Then, the active region 500 of the p-type metal-oxide-semiconductor half field effect transistor is formed. On top of a part of the shallow trench isolation 20, reactive ion etching (RIE) technology using CHF3 as a contact etcher 'etches a portion of the first dielectric layer 6 for the first time. Then, a portion During the etching process of the first dielectric layer 600, a compensation flank (Of fset spacer) 65 is formed over the active area of the P-type metal-oxide-semiconductor field-effect transistor 500. Then, the second defined light is removed. Resist layer 60A.

Page 17 * 1 (14) According to the diagram in the fifth figure, 'isolated in a part of the shallow trench 2 o, P-type metal-oxide-semiconductor field-effect transistor active area 500, P-type metal-oxide-semiconductor half-field effect transistor On the gate pattern 45, the compensation spacer 65, and the first dielectric layer 60, a silicon-boron layer is deposited using SiH4 and dagger 116 as a source gas and using ultra-high vacuum chemical vapor deposition (UHV / CVD) technology. (Si-B layer) 70 'its thickness is between 100 angstroms and 300 angstroms. According to the diagram of the sixth figure, 'using a rapid thermal process (RTP), at a temperature of about 800 degrees to 1000 degrees', the silicon oxide-boron layer 70 (as shown in the fifth figure) As shown in the formula (its time is about 10 seconds to 60 seconds, to form a borosilicate glass layer 80, and the first diffusion of boron atoms in the active area of the p-type metal-oxygen half field effect transistor 5 0 0 'Thereby forming a P-type lightly doped source / imaging electrode 85. Among them, the deleted atom has a concentration of about 5.0 oE / 21 cm / cm3. Then, on the borosilicate glass layer 80, a A second dielectric layer 90. The second dielectric layer 90 includes a silicon oxide or a silicon nitride layer. Ethyl orthoester is used as a source gas. Low pressure chemical vapor deposition (LPCVD) technology is used to deposit silicon dioxide at a temperature of about 500 degrees to 800 degrees, with a thickness of about 50 to 2000 angstroms. Using low pressure chemical vapor deposition (LPCVD) technology 'At a high temperature. About 750 degrees, a silicon nitride layer is deposited to a thickness of about 500 angstroms to 2000 angstroms. Basis As shown in 'CHF3 as an etchant using reactive ion etching (RIE) technique, the second dielectric layer is etched circle of seven figures a part of the 9〇,

Page 18 Λ Five portions of borosilicate glass layer 80, and a second portion of first dielectric layer 60 'are etched to form a first shed glass spacer 95 and a first BSG spacer Second borosilicate glass spacer (second BSG spacer) 100. According to the diagram of the eighth figure, in the active region 500 of the P-type metal-oxide-semiconductor field-effect transistor 500, an ion implantation procedure using boron (B) or boron fluoride (BF2) as an ion source is performed at an energy. Between about 1 K e V and 80 K e V, a dose of about 1.0 E 1 5 to 1 · 0 E 1 6 per square centimeter is implanted to form a p + -type heavily doped source Pole / drain (heav i 1 y doped source / drain) 1 05. Afterwards, in the active region of the n-type metal-oxide-semiconductor field-effect transistor 505, an ion implantation procedure using phosphorus (P) or arsenic (As) as an ion source is performed at an energy of less than 10 K e V to Between 80 KeV, a dose of about 1.0E 15 to 1.0E 16 atoms per square centimeter is implanted to form an n + -type heavily doped source / drain 110. According to the diagram of the ninth figure, 'Tempering the first ^ Peng Shixi glass partition wall g 5 using a rapid thermal process (RTP)' at a temperature of about 950 degrees to 105 degrees, The second diffusion of boron atoms in the region below the first borosilicate glass spacer 95 is between about 10 seconds and 60 seconds. Thereby, a source / drain extension junction 120 is formed in the _p plastic gold-oxygen half field effect transistor. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all others that do not depart from the disclosure of the present invention

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Claims (1)

7 2 ._____ VI. Application scope 1. A method for manufacturing a complementary metal-oxide-semiconductor field-effect transistor (CMOS) on a semiconductor substrate, the method at least includes: providing a semiconductor substrate having a semiconductor substrate First conductivity type; forming a well region in the semiconductor substrate, the well region having a second conductivity type, and the conductivity of the second conductivity and The first conductivity is opposite; a shallow trench isolation (STI) is formed in the semiconductor substrate and the well region to form a plurality of active regions; and a channel is formed in the semiconductor region and the well region. A semiconductor substrate and the well region; forming a P-type metal-oxide-semiconductor field-effect transistor (PM0SFET) gate pattern and an n-type metal-oxide-semiconductor field-effect transistor (NM0SFET) gate pattern on the semiconductor substrate and the well region Forming a first defined photoresist layer on the well region; implanting a first impurity of the second conductivity into the semiconductor substrate Thereby forming a first lightly doped source / drain (1 i ght iy doped s urce / drain); removing the first defined photoresist layer; depositing a first insulating layer on the A semiconductor substrate and the well region; forming a second defined photoresist layer on the first insulating layer; a first silver engraving part of the first insulating layer on the well region; 7p (offset spacer) on page 21 During the step of decorating the insulating layer over the well area, the scope of the patent application forms a compensation wall (a part of the Si-B layer) in the well area and This step removes the second defined photoresist layer, and deposits it on the edge layer of the 5th-shed layer; oxidizes the silicon-boron layer to form a borosilicate glass layer (BSG 1 &amp; πΓ), and diffuses for the first time A boron atom in the well region to form a second lightly doped source / drain; deposition-a second insulating layer on the borosilicate glass layer; etching a part of the second insulating layer, A part of the shed glass layer and a second etched part of the first insulating layer are formed to form a first butterfly stone glass spacer and a first collar stone glass spacer; implanted in the first A conductive-impurity in the well region to form a first heavily doped source / drain; implant a second impurity of the second conductivity into the semiconductor A second heavily doped source / drain is formed in the substrate, wherein the second impurity An impurity concentration greater than the first; and tempering the first rural cullet spacer, and a second diffusion of the boron atom form a source / drain extension junction is not pole. 3 1 in the mother cubic centimeter 1. 〇 E 1 5 atoms. 2. If you want to apply for the first scope of the patent application, please refer to ^... A $ Method of method ′, where the semiconductor substrate mentioned above contains at least a concentration of about 5%. Page 22 6. Scope of patent application 3. If the scope of patent application is the first! The term method includes at least one p-type. ^% 40% The method of item 1 in the range of 152, wherein the above-mentioned well area is formed / has been implanted with an ion implantation energy of about 100KeV to eV, and implanted with Agent: Divided between UE 12 and u E 13 atoms, followed by 1 rounding procedure at a temperature of about roundness, to form a well area with a concentration of J cubic centimeter 1, 0 E 1 6 atoms. The method of the patent model, wherein the above includes at least one n-type. Non-compliance 6 :, Ϊ1: The method of the first item of the patent scope, wherein the above-mentioned main active region of the LM_3-type metal-oxygen half field effect transistor. Shao i :: Zhuan: The method of the first item of Shiwei ’# in the active region of the active G n 'metal oxide half field effect transistor described above. 8 · If the scope of the patent application is the first, at least the sentence 厶 η, six τ, and the above-mentioned channels are rotten (B) are ions of an ion source, and the quantity is about 〇Kev, + tA ^ ^ Carved in the cloth planting sequence ,another. Implant a dose of about 1. cm per square centimeter of the OE electrical layer (approximately every electrical layer domain to domain to form an energy atom) 6. Apply for a patent scope 9. If the method of applying for a patent scope fi item, where the above In other words, at least, an ion implant containing (called ― ion source: / formed from an energy of about lOKeV, implanted at a dose of about ⑽ atoms per square centimeter of labor. _ 10. Method as described in the first patent application The formation of the p-type metal-oxide-semiconductor half-field-effect transistor gate pattern and the n-type metal-oxide-semiconductor half-field transistor pattern described above includes at least one polycrystalline silicon gate (ρ 〇1 ysi 1 ic 0 nga ) And two open-electrode layer (gate oxide layer). There are many descriptions of gate silicon crystals. / -N 2 in the upper layer and its S1, W / | \ method of tungsten tungsten squared one ο ο 1 Jingliduo please include * φ-pack as little as Π pole 1 2 The method of the first scope of the patent application 'wherein the above-the formation of a slightly doped source / drain, including at least the wall (P) An ion implantation procedure for an ion source, with an energy of less than 3 OK eV, implanting a dose of about 1.0 oE 14 to 5.0 oE 15 atoms per square centimeter. '1 3. The method according to item 1 of the scope of patent application, wherein the first-slightly heterogeneous source / Drain formation 'contains at least arsenic (As) as the ion 7 original polyion implantation procedure, at an energy of less than 30KeV, implantation-plus = ^ ^ ^, large dose, .sp. 1. 0E 1 4 to 5.0 E 1 5 atoms. Page 24 6. Application for patent scope 1 4. The method according to item 1 of the patent scope, wherein the first insulating layer includes at least silicon oxide, and TEOS is used as The source gas, using low pressure chemical vapor deposition (LPCVD) technology, deposits the first insulating layer at a temperature between about 500 degrees and 800 degrees, with a thickness between about 50 angstroms and 300 angstroms. 15. The method according to item 1 of the scope of patent application, wherein the above-mentioned first insulating layer includes at least silicon nitride, using low pressure chemical vapor deposition (LPCVD) technology, at a temperature of about 750 degrees, The first insulating layer is deposited with a thickness between about 50 angstroms and 300 angstroms. 1 6. The method according to item 丨 of the scope of the patent application, wherein the first insulating layer includes at least siHcon oxide / silicon nitride, using low-pressure chemical vapor deposition (LpcVD) technology. The temperature is about 500 degrees to 800 degrees, and the first insulating layer is deposited at about 100 to 300 angstroms. The method of item 1 in the scope of patent application, wherein the first etching of the first insulation mentioned above includes at least a reactive ionization (RIE) technique using chf3 as an etchant. 18. The item in scope of the patent application Method, wherein the above-mentioned deposition of Shi Xi S! -B layer) ^ includes at least the use of as a gas, using ultra-thin vacuum chemical vapor deposition (V / CVD) technology to deposit Page 25 42 ^ B7? ____ 6. Scope of Patent Application The silicon-boron layer has a thickness of about 100 angstroms to 300 angstroms. 19. The method according to item 1 of the scope of patent application, wherein the above-mentioned silicon-boron layer is oxidized to form a borosilicate glass layer, at least including a rapid thermal process (RTP), at a temperature of about 800 degrees to 1,000. Between 0 degrees, the silicon-boron layer is oxidized for a time between about 10 seconds and 60 seconds. 20. The method according to item 1 of the scope of patent application, wherein the boron atom described above contains at least a concentration of about 5.0 oE 2 1 atom per cubic centimeter. 2 1 · The method according to item 1 of the scope of patent application, wherein the above-mentioned second insulating layer includes at least silicon dioxide (si 1 icon oxide), using ethyl orthosilicate (TEOS) as a source gas, and a low-pressure chemical gas Phase deposition (LPCVD) technology, the second insulating layer is deposited at a temperature of about 500 degrees to 800 degrees, with a thickness of about 500 angstroms to 2000 angstroms. 2 2. The method according to item 1 of the scope of patent application, wherein the above-mentioned second insulating layer includes at least a silicon nitride layer (si 1 icon nUride), and a low pressure chemical vapor deposition (LPCVD) technique is used at a temperature of about 7 At 50 degrees, the second insulating layer is deposited to a thickness of between about 500 Angstroms and 2000 Angstroms. Page 26 6. The scope of patent application 2 4 ♦ If the scope of patent application is the first one, the method of solid item 1 'where the above-mentioned borosilicate glass layer is at least Γ / ΓΜΤΠ 乂 as a reactive ion contact etching (RIE) )technology. τ 2 5. As stated in the method of claim 1, wherein the second silver engraving of the first insulating layer described above includes at least a reactive ion axis etch (R IE) technique using CHF3 as an etchant. 2 6. The method according to item 1 of the scope of patent application, wherein the formation of the first heavily doped source / drain described above includes at least an ion implantation procedure using boron (B) as an ion source at an energy of approximately Between 1K e V and 80 Ke V, a dose of between about 10E 1.0 and 1.0E 16 atoms per square centimeter is implanted. 27. The method according to item 1 of the scope of patent application, wherein the formation of the above-mentioned first heavily doped source / drain comprises at least an ionization = Wei Zhi procedure using boron fluoride (BFa) as an ion source. Between an energy of about IKeV to 80KeV, a dose of about 1 atom per square centimeter between 1.0E 1 5 and 1 · 0E 1 6 is implanted. 28. The method as stated in item [Scope of the Patent], wherein the formation of the second heavily doped source / drain described above includes at least an ion cloth with phosphorus (P) as an ion source, and the procedure is two to one. The energy is less than lOKeV to 80KeV, and it is implanted in a dose of about 1. 0E 15 to 1. OE U per square centimeter. Page 27 29. The method according to item i of the patent application, wherein the formation of the second heavily doped source / non-electrode 'includes at least an ion implantation procedure using arsenic (As) as an ion source' at an energy of approximately Between less than 10 KeV and 801 ^^, a dose of about .0E15 to .0E16 atoms per square centimeter is implanted. 30. The method according to item 1 of the patent claim, wherein the second diffusion of atomic atoms mentioned above includes at least a rapid thermal process (RTP) at a temperature of about 950 degrees to 105 degrees The 'diffusion' of the boron atom occurs between about 10 seconds and 60 seconds. A method for manufacturing a complementary metal-oxide-semiconductor field-effect transistor (CMOS) on a semiconductor substrate, the method at least includes: &amp; p-type semi conductor substrate; well region) in the p-type semiconductor substrate; and 乂, “shallow trench isolation (STI allow trench isolation, STI) in the p-type semiconductor substrate and a part of the n-type well region to form— Active region of P-type metal-oxide-semiconductor field-effect transistor (PM0SFET) and active region of n-type metal-oxide-semiconductor field-effect transistor (NM0SFET); forming a channel in the p-type metal-oxide-semiconductor field-effect transistor The transistor is active and in the active area of the n-type metal-oxide half field effect transistor; 3, a gate oxi de layer is formed in the active area of the p-type metal-oxide and the n-type metal oxide Active area of oxygen half field effect transistor Page 28, 42 of 7 2 6. Applying for patents; depositing a polysilicon gate on the gate oxidation potential; etching the polysilicon gate and the gate oxide layer to form a p The metal-oxide-semiconductor half-field-effect transistor gate is active on the p-type metal-oxide-semiconductor half-field-effect transistor above the main two-domain and an n-type metal-oxide-semiconductor half-field-effect transistor gate pattern is active on the n-type oxygen half-effect transistor Over the region; * forming a first defined photoresist layer on the mouth-type gold-oxygen half field effect transistor active region and a portion of the shallow trench isolation; φ implanting a n-type impurity on the n-type gold In the active area of the oxygen half field effect transistor, an η-type lightly doped source / drainα is formed; the first defined photoresist layer is removed; di e 1 ectr ic: 1 ayer) isolated in the shallow trench, far-n-type metal-oxygen half-field effect. ^ ^ ^, lei a Μ is called k &amp; 野 &gt; Japanese body gate pattern, the P type Metal Oxygen Half-Field Effect ϋ Case Λ Stomach n-type Metal Oxide Half-Field Effect Transistor Active Area, Intellectual ft Half-Field Effect Transistor Active Area A first defined photoresist layer on the first dielectric layer; the first dielectric layer of the effect transistor on the 15-type metal-oxygen half field report The main effect of the effect transistor :: mf set spacer) during the p-type metal-oxide half-field step; on a part of the first dielectric layer etching step to remove the second defined photoresist layer; Page 29 ^ 269 7 2., VI. Applying for a general envelopment ~ ~-deposit a silicon-boron layer (Si-B layer) in a part of the shallow trench isolation, the P-type metal-oxygen half field effect transistor active Region, the p-type metal-oxide-semiconductor field-effect transistor gate pattern, the compensation gap wall, and the first dielectric layer; oxidizing the silicon-boron layer to form a borosilicate glass layer (BSG layer), and firstly Sub-diffusion deletion of atoms in the active region of the p-type metal-oxide half field effect transistor to form a p-type lightly doped source / drain; depositing a second dielectric layer on the borosilicate glass layer; A portion of the second dielectric layer, a portion of the borosilicate glass layer, and a portion of the first dielectric layer are etched a second time, thereby forming a first shed glass barrier and A second town; ε evening glass spacer; implanting a P + -type impurity into the active region of the p-type metal-oxide half field effect transistor to form a P + -type heavily doped source / drain (heavi doped source / drain); implanting an n + -type impurity into the active region of the n-type metal-oxide-half field effect transistor to form an η + -type heavily doped source / Drain; and tempering the first borosilicate glass spacer and diffusing the boron atom in the area below the first borosilicate glass spacer for a second time to form a source / drain extension Interfaced with a p-type metal-oxide-semiconductor field-effect transistor. 03. The method according to item 31 of the patent application, wherein the above-mentioned p-type semiconductor substrate contains at least a concentration of less than about 1 · 〇E 1 5 Atom 4269 7 2 VI. Applying for "&quot; '&quot; ____ 3 3 According to the method in the scope of patent application No. 3], the formation of' at least contains phosphorus (p) as an ion ', the above-mentioned n-type well region is Ion implantation procedure with energy between about 100Kπ and 200KeY, ^ uE 12 μ.0E 13 atoms, d: per minute (dmin) program at a temperature of about __ degrees, open "^ one drive The n-well area with a cubic centimeter of 1.0 E 16 atoms is approximately every 34. The method of item 31 in the scope of the patent application, wherein the element contains at least boron (B) as an ion source. Ion implantation = implantation in the shape of the wrist, about one dose per square centimeter] · 丄: solid: 35. If the method of the scope of patent application No. 31, wherein the above-mentioned channel is formed, at least ^ contains boron fluoride ( Swell 2) is an ion implantation process / of an ion source, implanting a dose of about 12 atoms per square centimeter at an energy of about 10 KeV. · 36. The method according to item 31 of the scope of patent application, wherein the formation of the above-mentioned gate gasification layer 'includes at least a thermal oxidation method (therma 丨 xidatión). 37. The method according to item 36 of the scope of patent application, wherein the above-mentioned thermal oxidation method includes at least a dry oxidation method (d r y 0 x i d a t i ο η) and a wet oxidation, wet oxidation ° Page 31 VI. Application scope of patents * '~ 3 8' The method described in item 31 of the scope of patent application 'wherein the above-mentioned polycrystalline silicon layer r is formed' includes at least the use of silicon methane (si 1 ane) as a source gas, M low pressure The chemical vapor deposition (LPCVD) technology forms the polycrystalline silicon layer at a temperature between about 600 ° and 650 °, with a thickness of about 100 Angstroms to 2500 Angstroms. 3. 39. The method according to item 31 of the scope of patent application, wherein the formation of the above-mentioned rr-type slightly doped source / drain includes at least ionization using a phosphorus (p) as an ion source = implantation procedure ' An energy is less than 30KeV, and a large dose is implanted, between about 1.0E 14 and 5.0E 15 atoms per square centimeter. 40 ′ The method of claim 31, wherein the formation of the η-type slightly doped source / drain described above includes at least an ion implantation procedure using arsenic (As) as an ion source. The energy is less than about 30 keV, and a dose of about 1.0E 14 to 5.0E 15 atoms per square centimeter is implanted. 41. The method according to item 31 of the scope of patent application, wherein the first dielectric layer includes at least silicon dioxide (si 1 icon oxide), and uses ethyl orthosilicate (TE0S) as a source gas to The low-pressure chemical vapor deposition (LpcvD) technology 'deposits the first dielectric layer' at a temperature between about 500 degrees and 800 degrees, and has a thickness between about 50 angstroms and 300 angstroms. 42. The method according to item 31 of the scope of patent application, wherein the first dielectric layer includes at least siiicori nitride. 1 Uses a low-pressure chemical gas. Page 32 _ ^ 2S9 γ ^ VI. Patent Application Phase deposition (LPCVD) technology deposits the first dielectric layer at a temperature of about 750 degrees, with a thickness of about 50 angstroms to 300 angstroms. 43. The method of claim 31, wherein the first dielectric layer includes at least silicon oxide / silicon ni tride 'using low pressure chemical vapor deposition (LPCVD) technology, The first dielectric layer is deposited at a temperature between about 500 degrees and 800 degrees, and has a thickness between about 100 angstroms and 300 angstroms. 44. The method of claim 31, wherein the first etching of the first dielectric layer mentioned above includes at least a reactive ion etching (RIE) technique using CHF3 as an etchant. 4 5. The method according to item 31 of the patent application park, wherein the deposition of the above-mentioned silicon-boron layer (Si-B layer) includes at least the use of siH4 and Minma as a source gas with ultra-high vacuum chemical vapor deposition ( UHV / CVD) technology, depositing the Shixi-Butterfly layer 'has a thickness between about 100 angstroms and 300 angstroms. 46_ The method of claim 31, wherein the above-mentioned silicon-boron layer is oxidized to form a shed bite glass layer, which includes at least a rapid thermal process (RTp) at a temperature of about 950 degrees to 100%. Between 0 degrees, the silicon-boron layer is oxidized for a time between about 10 seconds and 60 seconds. 4 7. The method according to item 3 丨 in the scope of patent application, wherein the boron atom described above is Page 33 VI. Scope of patent application Less than a roll of about 5. 0E 21 atoms per cubic centimeter. 48. If the method according to item 31 of the patent application, wherein the second dielectric layer includes at least silicon dioxide (si 1 ic〇n 〇x 丨 de), use ethyl orthoxanthate (TEOS) as a Source gas, using low pressure chemical vapor deposition (LpcvD) technology, to deposit the second dielectric layer at a temperature of about 50 ° to 800 °, with a thickness of about 500 angstroms to 200 angstroms. . 49. If the method according to item 31 of the scope of patent application, wherein the second dielectric layer includes at least a silicon nitride nitride layer, a low-pressure chemical vapor deposition (LPCVD) technique is used at a temperature of about 7 50 The thickness of the second dielectric layer is about 500 Angstroms to 2000 Angstroms. 50. The method according to item 31 of the scope of patent application, wherein the engraving of the second dielectric layer includes at least a reactive ion etching (RIE) technique using CHF3 as an etchant. 51. The method according to item 31 of the scope of patent application, wherein the silver engraving of the above-mentioned silicate glass layer includes at least a reactive ion etching (RIE) technique using CHFa as a nicking agent. 52. The method according to claim 31, wherein the second etching of the first dielectric layer mentioned above includes at least a reactive ion etching (RIE) technique using CHF3 as an etchant. Page 34 VI. Application for patent scope 53. The method of the scope of patent application No. 31, wherein the formation of the above-mentioned P + type heavily doped source / drain includes at least ions using boron (B) as an ion source In the implantation procedure, a dose of between about 0E 15 and 1.0E 16 atoms per square centimeter is implanted at an energy between about I KeV and about 80 KeV. 54. The method according to item 31 of the scope of patent application, wherein the formation of the above-mentioned P + -type heavily doped source / drain includes at least an ion implantation procedure using boron fluoride (BF2) as an ion source. An energy of about 1 KeV to 801 (6 ¥, implant a dose of about 1.0 oE 1 5 to 1 · 0E 1 6 atoms per square centimeter. 5 5, as in the 31st scope of the patent application Method, wherein the formation of the above-mentioned n + -type heavily doped source / drain includes at least an ion implantation procedure using phosphorus (P) as an ion source, and implanting an energy of less than lOKeV to 80KeV. The dose is about 1. 0E 15 to 1. 0E 16 atoms per square centimeter. 5 6. The method according to item 31 of the scope of patent application, wherein the formation of the n / type heavily doped source / electrode mentioned above is at least Including an ion implantation procedure using arsenic (A s) as an ion source, implanting a dose of approximately 1 0E 1 5 to 1. 0E 1 6 atoms per square centimeter at an energy of less than lOKeV to 80KeV 5 7. The method according to item 31 of the scope of patent application, wherein the first diffusion of the butterfly atom mentioned above includes at least one rapid heat Cheng (the RTP), in a wide temperature between about 950 degrees to about 50 degrees 1 billion, the diffusion of boron atoms for a time of about 1 second square P.35 4 ^ 69 7 2 VI. Patent application range to 60 seconds. Page 36