402802 A7 B7__ 五、發明説明（I ) 發明背景： 發明技術領域： 本發明是一種有關於積體電路的裝置，特別是指一種有 關於積體電路上的調整電壓源裝置與方法。而且，本發明的 電壓產生器可以因應不同的操作模式而作調整。 先前技述概述= 經濟部中央標孪局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 許多積體電路晶片（一般簡稱爲晶片）有超過一種以上 的操作模式。例如，在正常的工作狀態下，晶片執行正常的 功能，此時爲正常模式；在記憶體晶片中，指的正常模式可 能是處理存取記憶體的需求。另外，積體電路晶片有測試模 式，用來測試該晶片的功能是否正確。測試模式常常與 ''暖 機〃（burn-in )測試有關。暖機測試模式是一種可告度的 性能測試，其測試晶片在超過正常工作溫度的條件下，晶片 的操作效能等變化。例如，一個晶片可能被強迫進行暖機測 試，透過加熱方式使晶片的溫度上升至相當高的溫度，並以 相當高的電壓源VDD供應給該晶片。暖機試驗一般用來檢驗 晶片在短期使用後是否會喪失其功能。以下，電壓源VDD的 準位在正常工作模式時是記爲VDDN，在暖機模式時記爲 VDDbi 〇 但是，暖機試驗可能對具有電壓產生器的晶片造成損 害。特別是一些具有電壓產生器的積體電路晶片，而這些晶 片的電壓產生器產生負電壓以產生反偏壓（back-bias )使 用在控制N通道場效電晶體（NFETs )的臨限電壓上。該負 電壓源一般以VBB表示。VBB有時也稱爲負基板電壓源 ___ 4 ____ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） at 402802 B7 五、發明説明（>) (Negative substrate supply voltage )與提供正電壓的 電壓源VDD並存，暖機試驗的高準位電壓源VDDBI可能造成晶 片上一些電晶體的損害，因該電壓準位已超過電晶體的崩潰 電壓（breakdown voltage )。更有甚者，一些晶片上具有 拉升電壓的電壓源，其可使電壓源的準位高於供應的電壓源 VDD。如此一來，使得晶片上的電晶體溺潰情形更加惡化。 傳統的解決方法之一是如圖一所示，在進行暖機試驗時 將負電壓源VBB的準位調成較小的準位VBBbi。如此使得暖機 試驗的高電壓準位VDDBI的影響下降，而避免電晶體傰潰的 情形發生。 經濟部中央標隼扃員工消費合作社印裝 (請先閲讀背面之注意事項再填寫本頁) 傳統電壓調整系統10包括一使用於正常模式的電壓感 測電路（VSC ) 11，以及緩衝電路12，該緩衝電路12有 一輸出端連接至多工器13的一個輸入端。電壓感測電路11 是用來檢測負電壓源VBB是否已達到預定的正常工作模式的 電壓值。一般正常工作模式下的VBB電壓值約是電壓源VDD 電壓值的一半，即VBB =-VDD/2。當負電壓源VBB的電壓值 到達預定正常工作模式的臨限電壓時，電壓感測電路11送 出確認信號VLDN，該確認信號透過緩衝電路12傳至多工器 13 ° 電壓調整系統10更包括一使用於暖機試驗模式的電壓 感測電路（BI VSC ) 15，以及電壓緩衝電路16，該緩衝 電路也連接至多工器13。電壓感測電路15是用來檢測負電 壓源VBB是否已達到預定的暖機試驗模式的臨限電壓值。暖 機試驗模式的臨限電壓值是較一般正常模式的臨限電壓值 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210:<297公釐） 402^0^ 經濟部中央標隼局員工消費合作社印製 A7 B7 五、發明説明（>) 更負。當負電壓源VBB的電壓值到達預定暖機試驗模式的臨 限電壓時，電壓感測電路15送出確認信號VLDBI，該確認信 號透過緩衝電路16傳至多工器13。 多工器13具有一輸出端連接至電荷泵(CP)19，以及一 選擇端接受暖機試驗模式的控制信號BI。一般暖機試驗模 式的控制信號是由晶片上的測試模式暫存器（未顯示在 圖一）所提供，而該暫存器的內容則由外部測試儀器（未顯 示在圖中）所控制°進行暖機試驗時’控制信號會使得 電壓調整系統1〇進入暖機試驗模式。另外，晶片上的檢測 電路會被用來檢驗控制信號BI與何時進入暖機試驗模式。 圖二是電壓調整系統10在電源開啓時的時序圖。負電 壓源VBB的電壓準位以圖中的波形21來表示，控制信號BI 以波形23表示。電壓準位感測信號VLDn、¥1!^及VLD。分別 以波形25、27及29來表示。在該實施例中，電壓感測電 路11及15是電壓除法器型式的電壓感測電路。同時，電壓 感測信號VLDh即VLDb^際爲類比信號’不過爲了方便解釋 起見，圖二中以數位信號形式表示。在此實施例中，電壓調 整系統10的電壓源爲3伏特，正常模式時VBB爲-1. 5V，暖 機試驗時VBB則爲-1.0V。 請參考圖一及圖二，如果該晶片的電源開啓在暖機試驗 模式的情況時，由於負電壓源VBB的起始值爲零伏特，電壓 感測電路11及15會送出非確認（de-assert )f言號，即VLDn 與乂1^1均爲邏輯高電位。在暖機試驗模式時，信號bi是確 認的（邏輯高電位），因此使得多工器13選擇緩衝電路16 __6 本紙張尺度適用中國國CNS ) Α4ί見格—(2「0X297公釐1 * (請先閲讀背面之注意事項再填寫本頁) .裝* -9 A7 402802 B7 - 五、發明説明（义） 的信號輸出。亦即，多工器13的輸出信號VLD。在暖機試驗 模式時是與信號VUk相同。高電位的VLD。信號會使電壓泵 19工作而使負電壓源VBB的電壓向負值增加。因此，一開始 電壓波形21爲由零電壓開始的負斜率波形，由零電壓開始 的這一段曲線表記爲2h。 當負電壓源VBB的電壓到達-1. 〇V時（即暖機試驗模式 時VBB的臨限電壓值），電壓感測電路使感測信號Vldbi爲確 認信號(即邏輯低電位），因此使信號VLD。變成邏輯低電位’ 如圖二中記號2h與27!所指出者。該邏輯低電位信號VLD〇 使電壓泵19停止動作，因此負電壓源VBB的電位維持在_ 1.0V附近’如波形213所顯示。 經濟部中央橾準局員工消費合作、社印製 ϋ· —^1— ί 裝—II I I 訂—I I I I 播線 ,: - * (請先閲讀背面之注意事項再填寫本頁) ， 另一方面，當在正常工作模式下，控制信號BI是邏輯 低電位時，多工器13選擇緩衝電路12的VLDN信號（由電 壓感測電路11產生，經由緩衝電路12 )成爲輸出信號VLD〇。 如上所述’當電壓源VBB的電壓未達正常工作模式的VBB臨 限電壓，電壓感測電路11輸出非確認的信號VLDN。因此， 當信號BI爲邏輯低電位的非確認信號時，信號VLD。也是非 確認的，如圖二中標號23!所示。在正常工作模式時，負電 壓源VBB的臨限電壓是更負於暖機試驗模式時的電壓。接著 電荷泵19被啓動，使得負電壓源VBB的電壓往負值增加如 圖中2h所示。 當負電壓源VBB的電壓值到達正常工作模式的臨限電壓 時，電壓感測電路11發出確認信號，跟著多工器13的輸出 信號VLD。也發出確認信號，如圖二中215與25咖標示。VLD〇 〜 7 氏張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） A7 402802 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（/) 信號將使電荷泵19停止動作，使負電壓源VBB的電壓維持 在正常工作模式的VBB臨限電壓，在此例約爲-1. 5V如圖二 中2h所標示。不過，在此傳統的解決方式中有一問題，即 分離的暖機試驗模式所需的額外電路佔據了寶貴的晶片面 積，若可以多出這部分的晶片面積，將可作爲其他電路使 用。所以本案發明人提出一種可以偵測正常模式與暖機試驗 模式的VBB臨限電壓的電路，其可使所需的晶片面積最小 化。 發明簡要說明： 本發明提出一種適用於晶片上的電壓源調整系統，其可 以在不同的操作模式下提供不同的電壓源給不同的工作模 式所使用。在一個實施例中舉出了包含電壓感測電路（VSC ) 及一可設定緩衝電路（CBC )以調整晶片上的電壓產生器^ 該可設定緩衝電路產生一輸出信號至晶片上的電壓產生器 以控制電壓產生器的動作與否。電壓感測電路（VSC )則產 生偵測的電壓準位VLD信號，其準位可以是晶片上的電壓產 生器的功能準位。 可設定緩衝電路（CBC )接收控制工作模式的信號，以 及來自電壓感測電路的偵測信號VLD。可設定緩衝電路對於 控制信號的回應是在可設定緩衝電路中預先設定一相對於 選擇的工作模式的電壓準位。特別是針對不同的工作模式的 一個激發準位，當不同的工作模式時，可設定緩衝電路可以 使晶片上的電壓產生器產生相對應的電壓源電壓。本發明所 揭露之晶片上可調整的電壓源系統，其優點是使前述傳統的 _ 8 (請先閲讀背面之注意事項再填寫本頁) t -β 丁 本紙張尺度適用中國國家標準（CNS ) A4祝格（210x297公釐） 經濟部中央標隼局員工消費合作衽印製 402802 A7 _B7 五、發明説明（G) 技術更爲簡單，因此可以較傳統的電壓源調整技術節省積體 電路晶片的面積。另外，本發明的技術更可減少電力的消 耗，因爲本案的技術可以減少一個電壓感測電路，而通常電 壓感測電路都是需要消耗大量電力的β 本發明的特點之一是可設定緩衝電路（CBC )使用了一 可設定的拉升(pull-up)電路，其可以改變臨限電壓的激發 點。該可設定的拉升電路被使用在提升內部一節點的電 壓，然後藉以使輸出的信號可以控制電壓產生器的動作或不 動作。在其中一種操作模式下，該拉升電路強力提升節點電 壓，以使該緩衝電路在另一種操作模式之間有所不同，並藉 此改變臨限電壓。在另一種情況下，本發明中的可設定緩衝 電路也可以包含一拉降（pull-down )電路，以達到同樣的 效果。 圖示的簡要說明： 圖一是傳統習知的晶片上電源產生器電路的功能方塊圖，其 可以調整電壓產生器的電壓以適用於暖機試驗模式。 圖二是用來解釋圖一的動作的時序圖。 圖三是本發明的一個實施例的功能方塊圖，其用來解釋晶片 上的動態調整電壓源。 圖四是用來解釋本發明的一實施例中的可設定緩衝電路 (CBC )的動作的時序圖。 圖五是本發明的一個實施例的可設定緩衝電路的功能方塊 圖’該可設定緩衝電路中包含有一拉升電路。 圖六是本發明的一個實施例的可設定緩衝電路的功能方塊 尺度顧巾關家蘇_( CNS ) Α4雖（21GX297公釐)~ ---J----_---—裝-----「訂—_------線 (請先閲讀背面之注意事項再填寫本頁) ‘ . 經濟部中央標準局員工消費合作社印11 402802 A7 B7 五、發明説明（/ ) 圖，該可設定緩衝電路中包含有一拉降電路。 圖七是圖五的一個實施例電路圖。 圖八是用來解釋圖七的可設定緩衝電路的時序圖。 圖九是用來解釋圖六的可設定緩衝電路的一個實施例之詳 細電路圖。 圖號之簡要說明= 10傳統電壓調整系統 11 ' 15 電壓感測電路（VSC) 12、16 緩衝電路 13多工器 19電荷泵 32、90可設定緩衝電路（CBC ) 34、36、38 接線 51可設定拉升電路（CPUC ) 53拉降電路（PDC ) 55緩衝電路 57、95 節點 61拉升電路（PUC ) 63可設定拉降電路（CPDC ) P70-P73、P74、P77、P78P 通道場效電晶體(PFET) N75、N91-N93 N通道場效電晶體(NFET) 71、73、77、78、79 反相器 75電容器 發明的詳細說明： 10 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ------;------裝------7訂J-----‘線 (請先閱讀背面之注意事項再填寫本頁) ， 402802 經濟部中夬標準局員工消費合作.社印製 A7 B7 五、發明説明（『） 圖三是本發明一個實施例之功能方塊圖，其用來解釋積 體電路上的動態調整電壓源裝置30。爲了便於對照，圖示 中將相同功能或相似功能的方塊標示一樣的圖號。動態調整 電壓源裝置30包括電壓感測電路(VSC)ll，電荷泵19以及 一可設定緩衝電路（CBC ) 32。如同在圖一中的傳統裝置， 電壓感測電路11是用來偵測負電壓源VBB電壓是否已達到 正常工作模式的臨限電壓。電壓感測電路11的輸出端接線 34輸出感測信號VLD，該信號的電壓可代表負電壓源VBB的 某種功能的電壓準位。電壓感測電路11產生輸出信號VLD， 當負電壓源VBB的電壓到達正常模式的臨限電壓時，理論上 VLD信號的電壓準位將相等於正常工作模式的臨限電壓或稱 爲可設定緩衝電路32的激發點。在本實施例中，信號VLD 是基本上正比於負電壓源VBB的電壓值。 可設定緩衝電路32的一個輸入端連接致電壓感測電路 11的輸出端接線34，而另一輸入端則以接線36接收暖機試 驗模式的控制信號BI，而其輸出端則透過接線38與電荷泵 19連接。根據本發明，可設定緩衝電路32具有一可調整的 臨限電壓激發點，控制信號BI將使該電路在正常工作模式 與暖機試驗模式有不同的臨限電壓激發點。在此所稱的臨限 電壓激發點或開關點電位，效應上是與輸入的電壓作比較。 如果輸入的電壓信號小於該激發點，則可設定緩衝電路32 視此輸入電壓爲邏輯低準位，相反的，如果輸入的電壓信號 大於該激發點，則可設定緩衝電路32視此輸入電壓爲邏輯 高準位。 __11 本紙張尺度適财關家縣（CNS ) A峨格（21GX297公釐) " ~ -------：----裝------：-訂J------線 / . , (請先閱讀背面之注意事項再填寫本頁) _ 402802 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（^) 如上面所述，電壓感測電路11產生VLD信號，該信號 的電壓正比於負電壓源VBB的電壓值。可設定緩衝電路32 的正常工作模式的臨限電壓激發點是預先設定的，使電壓源 VDD及負電壓源VBB的電壓分別是正常工作模式的電位（例 如3. 3V )和-1. 5V。相對的，在暖機試驗模式時，臨限電壓 激發點也是預先設定的，使電壓源VDD及負電壓源VBB的電 壓分別是暖機試驗模式的電位（例如5· 5V )和-1. 0V。以下 將利用圖四對可設定緩衝電路32的這些臨限電壓與電路操 作，做一更詳細的說明。 圖四是用來解釋本發明的一個實施例（圖三）的操作的 時序圖。圖四中負電壓源VBB的電壓波形40，及感測信號 VLD的波形41。如上面對圖三所做的描述，電壓感測電路11 產生VLD信號，該信號的電壓正比於負電壓源VBB的電壓 值。 信號VLD。在暖機試驗模式下的波形如圖中圖號43所示 的波形。在信號VLD的電壓（波形41 )到達預定的可設定 緩衝電路32的暖機試驗模式的臨限電壓激發點之前，可設 定緩衝電路32輸出信號VLD。爲邏輯高準位。但是當信號VLD 的電壓到達預定的可設定緩衝電路32的暖機試驗模式的臨 限電壓激發點（波形41與暖機試驗模式之臨限電壓的交叉 點44 )時，可設定緩衝電路32輸出信號VLD。爲邏輯低準位 如圖中箭號45所示。該邏輯低準位的輸出信號VLD。會使圖 三中的電荷泵19停止動作，以使得負電壓源VBB與感測信 號VLD大致維持在波形4G與41的點4(h與4h處。當然，如 12 本紙伕尺度適用中國國家標準（CNS ) A4祝格（2 Η) X 297公釐） -----；----- 裝------：-訂 J-----j 線 (請先閲讀背面之注意事項再填寫本頁) . . 402802 經濟部中央標準局貝工消費合作社印裝 A7 B7 五、發明説明（（〇) 果負電壓源VBB的電壓值變的較小時，可設定緩衝電路32 將輸出信號VLD。爲邏輯高準位以啓動圖三中的電荷泵19， 使得負電壓源VBB的電壓繼續向負值增加。 信號VLD〇在正常工作模式時的作用如圖四的圚號47所 示的波形》在信號VLD的電壓（圖四中圖號41所示的波形） 到達在可設定緩衝電路32的預定正常工作模式的臨限電壓 激發點前，可設定緩衝電路32產生高邏輯準位的信號VLD。。 當信號VLD的電壓到達在可設定緩衝電路32的預定正常工 作模式的臨限電壓激發點（圖四中圖號41所示波形的標示 48點處），可設定緩衝電路32將使信號VLD。轉態爲低邏輯 準位，請參考圖號49的標示。該邏輯低準位的VLD〇信號將 使電荷泵19停止動作，因而使負電壓源VBB的電壓與信號 VLD的電壓大約維持在波形4G及41的4G2與4G!處。當然， 如果負電壓源VBB的電壓值大小不足時，可設定緩衝電路32 將使信號VLD。再次轉態爲邏輯高準位，以啓動電荷泵19使 得負電壓源VBB的電壓值變的更負。 綜合以上所述，在正常工作模式時，當負電壓源VBB的 電壓到達-1. 5V時，可設定緩衝電路32使信號VLD。轉態爲低 邏輯準位，而在暖機試驗模式時，當負電壓源VBB的電壓到 達-1· 0V時，可設定緩衝電路32使信號VLD。轉態爲低邏輯準 位。 圖五是圖三中的可設定緩衝電路32的實施例之功能方 塊圖。在此實施例中，可設定緩衝電路32包含一可設定拉 升電路（configurable pull up circuit, CPUC ) 51，一 13 本紙張尺度適用中國國家標準（CNS ) Λ4祝格（210X297公釐） . ' —裝------Γ訂J----'線 (請先閲讀背面之注意事項再填寫本頁) . ， 402802 經濟部中央標準局員工消費合作.社印製 A7 B7 五、發明説明（丨I ) 拉降電路（pull down circuit, PDC ) 53，以及一反相的 緩衝電路55。其中，可設定拉升電路51具有一輸入端接至 接線36以接受控制信號BI，另一輸入端則接至接線34以 接受信號VLD，另外，一拉升端接至節點57。拉降電路53 有一輸入端接至接線34，一拉降端接至節點57。緩衝電路 55的輸入端接至節點57，而輸出端接至接線38，以送出信 號 VLD〇 〇 上述可設定緩衝電路32的動作如下。接受控制信號 BI，使可設定拉升電路（CPUC ) 51爲正常工作模式或暖機 試驗模式。實際上，可設定拉升電路51與拉降電路53的作 用是一具有可設定臨限電壓開關或激發點的反相器。特別 是，藉著改變該反相器的臨限電壓或激發點，使可設定拉升 電路51在暖機試驗模式時比正常工作模式時有較強的拉升 作用，以拉升節點57的電壓。因此，當可設定緩衝電路32 在暖機試驗模式時，可設定拉升電路51有較強的拉升動作， 使得臨限電壓的開關點或激發點提高，因而使可設定緩衝電 路32在負電壓源VBB的電壓值較正常工作模式高時，輸出 確認的低電位VLD。信號。在上述情況下，可設定拉升電路51 與拉降電路53的臨限電壓激發點是相對於負電壓源VBB的 電壓值到達-1.0V處。 在暖機試驗的電源開啓時，負電壓源VBB的電壓值約爲 0V ▲因此，電壓感測電路（VSC ) 11 —開始產生邏輯低準 位的VLD信號，使得可設定緩衝電路32在其節點57處產生 一邏輯低準位信號。反相的緩衝電路55產生邏輯高準位的 14 本紙張尺度適用中國國家標準（CNS ) A4说格（210X297公釐） U3. (請先閲讀背面之注意事項再填寫本頁) 、τ 402802 經濟部中央標準局員工消費合作衽印製 A7 ____B7 五、發明説明（// ) VLD。信號，以啓動電荷泵19使得負電壓源VBB的電壓值向負 值增加》不過，當負電壓源VBB的電壓值達到-1. GV時，可 設定緩衝電路32會輸出邏輯高準位於節點57。該邏輯高準 位將使緩衝電路55產生邏輯低準位的VLD〇信號，因此電荷 泵19停止動作。 另一方面，當可設定緩衝電路32處於正常工作模式時， 可設定拉升電路51的效果下降，使得臨限電壓的開關點電 位降低。如此一來，將令可設定緩衝電路32在負電壓源VBB 的電壓值更負時，才輸出低準位的確認信號VLD〇。在本實施 例中，可設定拉升電路51與拉降電路53的臨限電壓激發點 是相對於負電壓源VBB的電壓值到達-1. 5V處。如上面所 述，一旦可設定拉升電路51被設定後，來自電壓感測電路 (VSC) 11的感測信號VLD透過可設定拉升電路51及緩衝電路 55，使得圖三中的電荷泵19停止動作。 圖六是可設定緩衝電路32的另一個實施例，其包括了 一拉升電路61，一緩衝電路55以及一可設定拉降電路 (configurable pull-down circuit)63。基本上圖五的架構 與圖六相似，僅是以拉升電路61取代可設定拉升電路51， 以可設定拉降電路63取代拉降電路53。 上述實施例的可設定緩衝電路32的動作如下。接受控 制信號BI，使可設定拉降電路(CPDC)63爲正常工作模式或 暖機試驗模式。實際上，可設定拉降電路63與拉升電路61 的作用是一具有可設定臨限電壓開關或激發點的反相器。特 別是，藉著改變該反相器的臨限電壓或激發點，使可設定拉 "^^尺度適财關轉準（(：叫44規格_(21(^297公釐) — ------；-----装------、-IT—----- (請先閲讀背面之注意事項再填寫本頁) at 402802 B7 五、發明説明（0) 降電路63在暖機試驗模式時比正常工作模式時有較弱的拉 降作用，以拉降節點57的電壓。因此，當可設定緩衝電路 32在暖機試驗模式時，可設定拉降電路63的拉降動作較 弱，使得臨限電壓的開關點或激發點提高，因而使可設定緩 衝電路32在負電壓源VBB的電壓值較正常工作模式時的電 壓值爲高的情況，便輸出確認的低電位VLD。信號。在上述暖 機試驗情況下，可設定拉降電路63與拉升電路61的臨限電 壓激發點是相對於負電壓源VBB的電壓值到達-1. 〇V處。 同樣的，當可設定緩衝電路32在正常工作模式時，可 設定拉降電路63的拉降動作較強，使得臨限電壓的開關點 或激發點爲一較暖機試驗模式時低的正電壓準位，因而使可 設定緩衝電路32在負電壓源VBB的電壓值較暖機試驗模式 時的電壓值爲低的情況，便輸出確認的低電位VLD〇信號。在 上述正常工作模式情況下，可設定拉降電路63與拉升電路 61的臨限電壓激發點是相對於負電壓源VBB的電壓值到達-1.5V 處。 經濟部中央標準局員工消費合作社印製 (請先閎讀背面之注意事項再填寫本頁) 圖七是圖五中可設定緩衝電路(CBC)32的一個具體實施 例的電路圖，另外圖三裡的電壓感測電路(VSC)ll的電路圖 也在此圖中顯示。在此實施例中電壓感測電路11包括P通 道場效電晶體(PFETs)P70-P73及一反相器71。P通道場效 電晶體P70-P73彼此互相連接，使得各電晶體在導通時其通 道可以形成由電壓源VDD至負電壓源VBB的一條路徑。p通 道場效電晶體P70的閘極與反相器71的輸出端耦合在一 起。反相器71的輸入端則用來接收低電力控制信號（low 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） 經濟部中央標準局員工消費合作社印製 A7 402802 B7 五、發明説明（丨/) power control signal)LP。低電力控制信號LP是由一控制 電路（未顯示）所送出，用以使晶片進入低電力模式的信號。 一旦低電力控制信號成立時，P通道場效電晶體P70關閉， 亦即由電壓源tDD至負電壓源VSS的導通路徑關閉，以節省 電力消耗。 P通道場效電晶體P70的源極和汲極分別連接至電壓源 VDD以及二極體形式的P通道場效電晶體P71的源極。P通 道場效電晶體P71的閘極耦合至接線34以及也是二極體形 式的P通道場效電晶體P72的源極。P通道場效電晶體P72 的閘極耦合至也是二極體形式的P通道場效電晶體P73的源 極。P通道場效電晶體P73的閘極和汲極一起接至負電壓源 VBB 〇 在本實施例中，可設定緩衝電路(CBC)32包括一反相器 73，一電容器75，一可設定拉升電路(CPUC)51，一拉降電 路(PDC)53以及反相的緩衝電路55。其中，該可設定拉升電 路(CPUC)51由P通道場效電晶體P74、P77及P78構成，該 拉降電路(PDC)53由N通道場效電晶體N75構成，而該反相 的緩衝電路55則由串接的三個反相器77、78、79所構 成。電容器75是由一 P通道場效電晶體構成，將源極與汲 極並接成爲電容器的第一電極，而該電晶體的閘極則當作電 容器的第二電極。 可設定緩衝電路(CBC)32的結構與連接關係如下所述。 電容器的第一電極與第二電極分別接至電壓源VDD與接線 34。另外，接線34更接至場效電晶體N75、P74以及P78 17 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^------^------1T—-----0 /. . · (請先閲讀背面之注意事項再填寫本頁) 402B02 經濟部中央標準局員工消費合作社印製 Α7 Β7 五、發明説明（U ) 的閘極。P通道場效電晶體P74的源極與汲極分別接至電壓 源VDD與節點57。N通道場效電晶體N74的源極與汲極分 別接至地電位(ground)與節點57。節點57還接至P通道場 效電晶體P78的汲極。而P通道場效電晶體P78的源極則接 至P通道場效電晶體P77的汲極。P通道場效電晶體P77的 源極接至電壓源VDD，而其閘極則接至反相器73的輸出端。 反相器73的輸入端接收控制信號BI。 本實施例的可設定緩衝電路32的動作情形如下所述。 在正常工作模式下，負電壓源VSS的電壓值爲-1. 5V，電壓 感測電路11的輸出會使接線34上的電壓大約等於可設定緩 衝電路32的激發點。特別是每一個P通道場效電晶體P70-P73的尺寸都是經過事先調整的，以使得在每一個P通道場 效電晶體上的壓降可以使接線34上的電壓準位在正常工作 模式下爲所設計的可設定緩衝電路32的激發點準位，此時 的電壓源VDD爲正常工作模式的電壓值，負電壓源VBB的電 壓值則爲-1. 5V。關於P通道場效電晶體P70-P73的尺寸可 以使用傳統的商業化工具，如HSPICE來模擬運算而求出理 想的尺寸。另外，這些電晶體的尺寸調整可以利用晶片上多 餘的小尺寸元件透過金屬連線來整合成所需的尺寸。 場效電晶體P74及N75構成一互補式金氧半導體(CMOS) 反相器，該反相器的臨限電位（或稱激發點）由此二電晶體 的尺寸所決定。通常增加P通道場效電晶體拉升元件的尺寸 (指加大寬度對長度的比值）則拉升路徑的強度增加。同樣 的，增加拉降的場效電晶體元件的尺寸則拉降路徑的強度增 本紙張尺度適用中國國家標準（CNS ) μ現格（2丨〇 X 297公釐） 1^. HI II —^1 丨·· — - - —1 i. - I- - I (請先閱讀背面之注意事項再填寫本頁)402802 A7 B7__ V. Description of the Invention (I) Background of the Invention: Field of the Invention: The present invention relates to an integrated circuit device, and more particularly to an apparatus and method for adjusting a voltage source on an integrated circuit. Moreover, the voltage generator of the present invention can be adjusted for different operation modes. Overview of previous technical descriptions = Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back before filling out this page) Many integrated circuit chips (generally referred to as chips) have more than one mode of operation. For example, under normal operating conditions, the chip performs normal functions, which is the normal mode; in a memory chip, the normal mode may refer to the processing of memory access requirements. In addition, the integrated circuit chip has a test mode to test whether the function of the chip is correct. The test mode is often related to the "burn-in" test. The warm-up test mode is a reportable performance test. It tests the chip's operating efficiency and other changes when the chip exceeds the normal operating temperature. For example, a wafer may be forced to undergo a warm-up test, which raises the temperature of the wafer to a relatively high temperature by heating, and supplies the wafer with a relatively high voltage source VDD. The warm-up test is generally used to check whether the chip will lose its function after short-term use. In the following, the level of the voltage source VDD is recorded as VDDN in the normal operation mode and VDDbi in the warm-up mode. However, the warm-up test may cause damage to the chip with the voltage generator. In particular, some integrated circuit chips with voltage generators, and the voltage generators of these chips generate negative voltage to generate back-bias, which is used to control the threshold voltage of N-channel field effect transistors (NFETs). . This negative voltage source is generally represented by VBB. VBB is sometimes referred to as a negative substrate voltage source ___ 4 ____ This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) at 402802 B7 V. > (Negative substrate supply voltage) and provide A positive voltage source VDD coexists, and the high-level voltage source VDDBI of the warm-up test may cause damage to some transistors on the wafer, because the voltage level has exceeded the breakdown voltage of the transistor. What's more, some chips have a voltage source with a boosted voltage, which can make the level of the voltage source higher than the supplied voltage source VDD. As a result, the drowning situation of the transistor on the wafer is worsened. One of the traditional solutions is to adjust the level of the negative voltage source VBB to a smaller level VBBbi during the warm-up test as shown in Figure 1. This reduces the influence of the high-voltage level VDDBI in the warm-up test, and prevents the transistor from collapsing. Printed by the Ministry of Economic Affairs' Central Consumer Cooperatives (please read the notes on the back before filling this page) The traditional voltage adjustment system 10 includes a voltage sensing circuit (VSC) 11 and a buffer circuit 12 for normal mode. The buffer circuit 12 has an output terminal connected to an input terminal of the multiplexer 13. The voltage sensing circuit 11 is used to detect whether the negative voltage source VBB has reached a predetermined voltage value of the normal operating mode. In normal operating mode, the VBB voltage is about half of the voltage source VDD voltage, that is, VBB = -VDD / 2. When the voltage value of the negative voltage source VBB reaches the threshold voltage of the predetermined normal operating mode, the voltage sensing circuit 11 sends a confirmation signal VLDN, which is transmitted to the multiplexer 13 through the buffer circuit 12. The voltage adjustment system 10 further includes a use The voltage sensing circuit (BI VSC) 15 in the warm-up test mode and the voltage buffer circuit 16 are also connected to the multiplexer 13. The voltage sensing circuit 15 is used to detect whether the negative voltage source VBB has reached a threshold voltage value of a predetermined warm-up test mode. The threshold voltage value of the warm-up test mode is higher than the threshold voltage value of the normal mode. 5 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210: < 297 mm) 402 ^ 0 ^ Central Standard of the Ministry of Economic Affairs A7 B7 printed by the Bureau ’s Consumer Cooperative Fifth, the invention description (>) is more negative. When the voltage value of the negative voltage source VBB reaches the threshold voltage of the predetermined warm-up test mode, the voltage sensing circuit 15 sends a confirmation signal VLDBI, which is transmitted to the multiplexer 13 through the buffer circuit 16. The multiplexer 13 has an output terminal connected to the charge pump (CP) 19, and a selection terminal receiving a control signal BI of the warm-up test mode. The control signal for the general warm-up test mode is provided by the test mode register (not shown in Figure 1) on the chip, and the content of the register is controlled by an external test instrument (not shown in the figure). During the warm-up test, the control signal will cause the voltage adjustment system 10 to enter the warm-up test mode. In addition, the detection circuit on the chip will be used to verify the control signal BI and when to enter the warm-up test mode. FIG. 2 is a timing diagram of the voltage adjustment system 10 when the power is turned on. The voltage level of the negative voltage source VBB is represented by waveform 21 in the figure, and the control signal BI is represented by waveform 23. Voltage level sensing signals VLDn, ¥ 1! ^ And VLD. Represented by waveforms 25, 27, and 29, respectively. In this embodiment, the voltage sensing circuits 11 and 15 are voltage sensing circuits of a voltage divider type. At the same time, the voltage sensing signal VLDh, that is, VLDb ^ is an analog signal ', but for the sake of convenience of explanation, it is shown as a digital signal in FIG. In this embodiment, the voltage source of the voltage adjustment system 10 is 3 volts, VBB is -1.5 V in the normal mode, and VBB is -1.0 V in the warm-up test. Please refer to Figure 1 and Figure 2. If the power of this chip is turned on in the warm-up test mode, the voltage sensing circuits 11 and 15 will send non-confirmation (de- assert) f, that is, VLDn and 乂 1 ^ 1 are logic high. In the warm-up test mode, the signal bi is confirmed (logic high potential), so the multiplexer 13 selects the buffer circuit 16 __6 This paper size is applicable to China's CNS) Α4ί 见 格 — (2 「0X297mm1 * ( Please read the precautions on the back before filling in this page). Installation * -9 A7 402802 B7-V. Signal output of the invention description (meaning). That is, the output signal VLD of the multiplexer 13. In the warm-up test mode It is the same as the signal VUk. VLD with a high potential. The signal will cause the voltage pump 19 to operate and increase the voltage of the negative voltage source VBB to a negative value. Therefore, the voltage waveform 21 at the beginning is a negative slope waveform starting from zero voltage and starting from zero. The curve at the beginning of the voltage is recorded as 2h. When the voltage of the negative voltage source VBB reaches -1.0V (that is, the threshold voltage value of VBB in the warm-up test mode), the voltage sensing circuit makes the sensing signal Vldbi confirm Signal (ie, logic low), so that the signal VLD. Becomes a logic low 'as indicated by the symbols 2h and 27! In Figure 2. This logic low signal VLD0 stops the voltage pump 19, so the negative voltage source VBB The potential is maintained near _ 1.0V 'As shown by waveform 213. Consumers' cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs, printed by the companyϋ— ^ 1— ί—II II order—IIII broadcast line ,:-* (Please read the notes on the back before filling in (On this page), on the other hand, when the control signal BI is a logic low potential in the normal operating mode, the multiplexer 13 selects the VLDN signal of the buffer circuit 12 (generated by the voltage sensing circuit 11 via the buffer circuit 12) to become Output signal VLD. As described above, when the voltage of the voltage source VBB does not reach the VBB threshold voltage of the normal operating mode, the voltage sensing circuit 11 outputs a non-confirmed signal VLDN. Therefore, when the signal BI is a logic low potential, the non-confirmed The signal is the signal VLD. It is also non-confirmed, as shown by 23 in Figure 2. In the normal working mode, the threshold voltage of the negative voltage source VBB is more negative than the voltage in the warm-up test mode. Then the charge pump 19 is activated, so that the voltage of the negative voltage source VBB increases to a negative value as shown in 2h in the figure. When the voltage value of the negative voltage source VBB reaches the threshold voltage of the normal working mode, the voltage sensing circuit 11 sends a confirmation signal and follows many The output signal VLD of the device 13. It also sends a confirmation signal, as indicated by 215 and 25 in Figure 2. VLD 〇 ~ 7 The scale is applicable to China National Standards (CNS) A4 specifications (210X297 mm) A7 402802 B7 Central Ministry of Economic Affairs 5V Printed by the Consumer Cooperative of the Bureau of Standards 5. Explanation of the invention (/) The signal will stop the charge pump 19, so that the voltage of the negative voltage source VBB is maintained at the VBB threshold voltage of the normal working mode, in this case about -1. 5V As indicated by 2h in Figure 2. However, there is a problem in this traditional solution, that is, the extra circuit required for the separate warm-up test mode occupies valuable chip area, and if this part of the chip area can be extra, it can be used for other circuits. Therefore, the inventor of the present invention proposes a circuit that can detect the VBB threshold voltage of the normal mode and the warm-up test mode, which can minimize the required chip area. Brief description of the invention: The present invention proposes a voltage source adjustment system suitable for a wafer, which can provide different voltage sources to different working modes in different operating modes. In one embodiment, a voltage sensing circuit (VSC) and a settable buffer circuit (CBC) are included to adjust the voltage generator on the chip. The settable buffer circuit generates an output signal to the voltage generator on the chip. To control the operation of the voltage generator. The voltage sensing circuit (VSC) generates a detected voltage level VLD signal, and the level can be the function level of the voltage generator on the chip. The buffer circuit (CBC) can be set to receive the signal for controlling the working mode and the detection signal VLD from the voltage sensing circuit. The response of the settable buffer circuit to the control signal is to preset a voltage level in the settable buffer circuit relative to the selected working mode. Especially for an excitation level of different working modes, a buffer circuit can be set to enable the voltage generator on the chip to generate a corresponding voltage source voltage in different working modes. The adjustable voltage source system on the wafer disclosed by the present invention has the advantage of making the aforementioned traditional _ 8 (please read the precautions on the back before filling this page) t -β Dimensions of this paper are applicable to Chinese National Standards (CNS) A4 Zhuge (210x297 mm) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs for consumer cooperation and printing of 402802 A7 _B7 V. Description of the invention (G) The technology is simpler, so it can save integrated circuit chips compared to traditional voltage source adjustment technology area. In addition, the technology of the present invention can further reduce the power consumption, because the technology of this case can reduce one voltage sensing circuit, and usually the voltage sensing circuit needs to consume a large amount of power. One of the features of the present invention is that a buffer circuit can be set (CBC) uses a settable pull-up circuit, which can change the threshold of the threshold voltage. This configurable pull-up circuit is used to boost the voltage of an internal node, and then the output signal can control the action or non-action of the voltage generator. In one of the operation modes, the pull-up circuit strongly boosts the node voltage to make the snubber circuit different between the other operation modes and thereby change the threshold voltage. In another case, the settable buffer circuit in the present invention may also include a pull-down circuit to achieve the same effect. Brief description of the figure: Figure 1 is a functional block diagram of a conventional conventional chip power generator circuit, which can adjust the voltage of the voltage generator to be suitable for the warm-up test mode. FIG. 2 is a timing diagram for explaining the operation of FIG. FIG. 3 is a functional block diagram of an embodiment of the present invention, which is used to explain a dynamically adjusted voltage source on a chip. FIG. 4 is a timing diagram for explaining the operation of the settable buffer circuit (CBC) in an embodiment of the present invention. FIG. 5 is a functional block diagram of a settable buffer circuit according to an embodiment of the present invention. The settable buffer circuit includes a pull-up circuit. Figure 6 is a functional block scale of a buffer circuit that can be set according to an embodiment of the present invention. Gu Jiaguan (CNS) Α4 (21GX297 mm) ~ --- J ----_------ ---- "Order —_------ line (please read the precautions on the back before filling out this page) '. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 11 402802 A7 B7 V. Description of Invention (/) Figure 7, the settable buffer circuit includes a pull-down circuit. Figure 7 is a circuit diagram of an embodiment of Figure 5. Figure 8 is a timing diagram used to explain the settable buffer circuit of Figure 7. Figure 9 is used to explain Figure 6 Detailed circuit diagram of an embodiment of the settable buffer circuit. Brief description of the drawing number = 10 Traditional voltage adjustment system 11 '15 Voltage sensing circuit (VSC) 12, 16 Buffer circuit 13 Multiplexer 19 Charge pump 32, 90 can Set buffer circuit (CBC) 34, 36, 38 Wiring 51 can set pull-up circuit (CPUC) 53 pull-down circuit (PDC) 55 buffer circuit 57, 95 nodes 61 pull-up circuit (PUC) 63 can set pull-down circuit (CPDC) ) P70-P73, P74, P77, P78P channel field effect transistor (PFET) N75, N91-N93 N channel field effect transistor (NFET) 71, 73, 77, 78, 79 Inverter 75 Capacitor invention detailed description: 10 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) ------;- ---- Install ------ 7 Order J ----- 'line (please read the precautions on the back before filling this page), 402802 Employees of the China Standards Bureau, Ministry of Economic Affairs, Consumer Co-operation. Printed by A7 B7 V. Description of the invention (") Figure 3 is a functional block diagram of an embodiment of the present invention, which is used to explain the dynamic adjustment of the voltage source device 30 on the integrated circuit. In order to facilitate comparison, the same function or similar function is shown in the figure The squares are marked with the same figure number. The dynamically adjusted voltage source device 30 includes a voltage sensing circuit (VSC) 11, a charge pump 19, and a settable buffer circuit (CBC) 32. As in the conventional device in FIG. 1, the voltage sensing The circuit 11 is used to detect whether the voltage of the negative voltage source VBB has reached the threshold voltage of the normal working mode. The output terminal 34 of the voltage sensing circuit 11 outputs a sensing signal VLD, and the voltage of this signal can represent the voltage of the negative voltage source VBB. Voltage level of a certain function. The voltage sensing circuit 11 generates an output The signal VLD, when the voltage of the negative voltage source VBB reaches the threshold voltage of the normal mode, the voltage level of the VLD signal will theoretically be equal to the threshold voltage of the normal operating mode or the excitation point of the settable buffer circuit 32. In this embodiment, the signal VLD is a voltage value that is substantially proportional to the negative voltage source VBB. One input terminal of the buffer circuit 32 can be set to be connected to the output terminal connection 34 of the voltage sensing circuit 11 while the other input terminal receives the control signal BI of the warm-up test mode via the connection 36, and its output terminal is connected to The charge pump 19 is connected. According to the present invention, the settable buffer circuit 32 has an adjustable threshold voltage excitation point, and the control signal BI will cause the circuit to have different threshold voltage excitation points in the normal operating mode and the warm-up test mode. The threshold potential referred to here as the threshold voltage excitation point or switching point is compared with the input voltage in effect. If the input voltage signal is less than the excitation point, the buffer circuit 32 can be set to treat the input voltage as a logic low level. Conversely, if the input voltage signal is greater than the excitation point, the buffer circuit 32 can be set to treat the input voltage as Logic high level. __11 The paper size is suitable for Guancai County (CNS) A Ege (21GX297 mm) " ~ -------: ---- install --------:-order J ---- --Line /., (Please read the precautions on the back before filling this page) _ 402802 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (^) As mentioned above, the voltage sensing circuit 11 A VLD signal is generated, the voltage of which is proportional to the voltage value of the negative voltage source VBB. The threshold voltage excitation point of the normal operating mode of the buffer circuit 32 can be set so that the voltages of the voltage source VDD and the negative voltage source VBB are the potentials of the normal operating mode (for example, 3.3V) and -1.5V, respectively. In contrast, in the warm-up test mode, the threshold voltage excitation point is also set in advance, so that the voltages of the voltage source VDD and the negative voltage source VBB are the potentials of the warm-up test mode (for example, 5 · 5V) and -1.0V. . In the following, these threshold voltages and circuit operations of the settable buffer circuit 32 will be described in more detail using FIG. Fig. 4 is a timing chart for explaining the operation of one embodiment (Fig. 3) of the present invention. The voltage waveform 40 of the negative voltage source VBB and the waveform 41 of the sensing signal VLD in FIG. 4. As described above with reference to Figure 3, the voltage sensing circuit 11 generates a VLD signal whose voltage is proportional to the voltage value of the negative voltage source VBB. Signal VLD. The waveform in the warm-up test mode is shown in Figure 43 in the figure. The buffer circuit 32 may be set to output the signal VLD before the voltage (waveform 41) of the signal VLD reaches a predetermined threshold of the warm-up test mode of the settable buffer circuit 32. Is a logic high level. However, when the voltage of the signal VLD reaches a predetermined threshold of the warm-up test mode in which the buffer circuit 32 can be set (the intersection point of the waveform 41 and the threshold voltage of the warm-up test mode 44), the output of the buffer circuit 32 can be set. Signal VLD. The logic low level is shown by arrow 45 in the figure. The logic low level output signal VLD. The charge pump 19 in FIG. 3 will be stopped, so that the negative voltage source VBB and the sensing signal VLD are maintained approximately at the points 4 (h and 4h) of the waveforms 4G and 41. Of course, if the paper size is 12, the Chinese national standard applies (CNS) A4 greeting (2 Η) X 297 mm) -----; ----- Outfit --------: Order J ----- j line (please read the first Note: Please fill in this page again... 402802 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed A7 B7 V. Description of the invention ((〇) If the voltage value of the negative voltage source VBB becomes smaller, the buffer circuit 32 can be set. The output signal VLD. Is at a logic high level to start the charge pump 19 in FIG. 3, so that the voltage of the negative voltage source VBB continues to increase to a negative value. The function of the signal VLD〇 in the normal working mode is shown as 四 47 in Figure 4. The waveform shown "before the voltage of the signal VLD (the waveform shown by the figure 41 in Figure 4) reaches the threshold voltage excitation point of the predetermined normal operating mode in which the buffer circuit 32 can be set, the buffer circuit 32 can be set to generate a high logic The level of the signal VLD ... When the voltage of the signal VLD reaches the scheduled normal operation of the settable buffer circuit 32 The threshold voltage excitation point of the formula (at the 48 mark of the waveform shown by the number 41 in FIG. 4) can be set to the buffer circuit 32 to make the signal VLD. The transition state is a low logic level, please refer to the mark of figure 49. This logic low level VLD0 signal will stop the charge pump 19, so that the voltage of the negative voltage source VBB and the voltage of the signal VLD are maintained at approximately 4G2 and 4G! Of the waveforms 4G and 41. Of course, if the negative voltage source When the voltage value of VBB is insufficient, the buffer circuit 32 can be set to make the signal VLD. The state transitions to a logic high level again to start the charge pump 19 to make the voltage value of the negative voltage source VBB more negative. In summary, In the normal working mode, when the voltage of the negative voltage source VBB reaches -1.5V, the buffer circuit 32 can be set to make the signal VLD. The transition state is a low logic level, and in the warm-up test mode, when the negative voltage source VBB When the voltage reaches -1 · 0V, the buffer circuit 32 can be set to make the signal VLD. The transition state is a low logic level. Fig. 5 is a functional block diagram of the embodiment of the settable buffer circuit 32 in Fig. 3. In this embodiment The settable buffer circuit 32 includes a settable Configurable pull up circuit (CPUC) 51, 13 This paper size is applicable to the Chinese National Standard (CNS) Λ4 Zhuge (210X297 mm). '— 装 ------ Γ 定 J ----' (Please read the notes on the back before filling out this page). 402802 Consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by the company A7 B7 V. Description of the invention (丨 I) Pull down circuit (PDC) 53 And an inverting buffer circuit 55. Among them, the pull-up circuit 51 can be set to have one input terminal connected to the connection 36 to receive the control signal BI, the other input terminal connected to the connection 34 to receive the signal VLD, and a pull-up terminal connected to the node 57. The pull-down circuit 53 has an input terminal connected to the connection 34 and a pull-down terminal connected to the node 57. The input terminal of the buffer circuit 55 is connected to the node 57 and the output terminal is connected to the connection 38 to send the signal VLD. The operation of the above-mentioned settable buffer circuit 32 is as follows. Accept the control signal BI, so that the pull-up circuit (CPUC) 51 can be set to the normal working mode or warm-up test mode. In fact, the role of the settable pull-up circuit 51 and the drop-down circuit 53 is an inverter having a settable threshold voltage switch or excitation point. In particular, by changing the threshold voltage or excitation point of the inverter, the pull-up circuit 51 can be set to have a stronger pull-up effect in the warm-up test mode than in the normal working mode, so as to pull up the node 57. Voltage. Therefore, when the settable buffer circuit 32 is in the warm-up test mode, the settable pull-up circuit 51 can be set to have a strong pull-up action, so that the switching point or the excitation point of the threshold voltage is increased, so that the settable buffer circuit 32 is in the negative state. When the voltage value of the voltage source VBB is higher than the normal operating mode, the low potential VLD confirmed is output. signal. In the above case, the threshold voltage excitation points of the pull-up circuit 51 and the pull-down circuit 53 can be set to reach -1.0V with respect to the voltage value of the negative voltage source VBB. When the power supply for the warm-up test is turned on, the voltage value of the negative voltage source VBB is about 0V ▲ Therefore, the voltage sensing circuit (VSC) 11-begins to generate a logic low level VLD signal, so that the buffer circuit 32 can be set at its node A logic low signal is generated at 57. The inverting buffer circuit 55 produces a logic high level of 14. This paper size applies the Chinese National Standard (CNS) A4 grid (210X297 mm) U3. (Please read the precautions on the back before filling this page), τ 402802 Economy A7 ____B7 printed by the consumer cooperation of the Ministry of Standards of the People's Republic of China V. Description of Invention (//) VLD. Signal to start the charge pump 19 so that the voltage value of the negative voltage source VBB increases to a negative value. However, when the voltage value of the negative voltage source VBB reaches -1. GV, the settable buffer circuit 32 will output a logic Micro Motion at node 57. . This logic high level causes the buffer circuit 55 to generate a logic low level VLD0 signal, so the charge pump 19 stops operating. On the other hand, when the settable buffer circuit 32 is in the normal operation mode, the effect of the settable pull-up circuit 51 is reduced, so that the threshold voltage switching point potential is reduced. In this way, the settable buffer circuit 32 will output the low-level confirmation signal VLD0 when the voltage value of the negative voltage source VBB becomes more negative. In this embodiment, the threshold voltage excitation point of the pull-up circuit 51 and the pull-down circuit 53 can be set to reach a voltage value of -1.5V at a voltage relative to the negative voltage source VBB. As described above, once the settable pull-up circuit 51 is set, the sensing signal VLD from the voltage sensing circuit (VSC) 11 passes through the settable pull-up circuit 51 and the buffer circuit 55, so that the charge pump 19 in FIG. Stop action. FIG. 6 shows another embodiment of the configurable buffer circuit 32, which includes a pull-up circuit 61, a buffer circuit 55, and a configurable pull-down circuit 63. Basically, the structure of FIG. 5 is similar to that of FIG. 6, except that the settable pull-up circuit 51 is replaced by the set-up circuit 61, and the set-down pull-down circuit 63 is replaced by the set-up pull-down circuit 63. The operation of the settable buffer circuit 32 of the above embodiment is as follows. Accept the control signal BI to set the pull-down circuit (CPDC) 63 to the normal working mode or warm-up test mode. In fact, the role of the settable pull-down circuit 63 and the pull-up circuit 61 is an inverter with a settable threshold voltage switch or excitation point. In particular, by changing the threshold voltage or the excitation point of the inverter, the settable quotation of the ^^ scale can be adjusted to the appropriate financial level ((: called 44 specifications _ (21 (^ 297 mm) —- ----; ----- install ------, -IT ------- (Please read the precautions on the back before filling this page) at 402802 B7 V. Description of the invention (0) The circuit 63 has a weaker pull-down effect in the warm-up test mode than in the normal working mode to pull down the voltage of the node 57. Therefore, when the buffer circuit 32 can be set in the warm-up test mode, the pull-down circuit 63 can be set The weak pull-down action makes the threshold voltage switch point or excitation point increase, so that the settable buffer circuit 32 can output a confirmation when the voltage value of the negative voltage source VBB is higher than the voltage value in the normal working mode. 。 Low potential VLD. Signal. In the case of the warm-up test, the threshold voltage excitation point of the pull-down circuit 63 and the pull-up circuit 61 can be set to reach a voltage value of −1.0% relative to the voltage value of the negative voltage source VBB. Similarly, when the buffer circuit 32 can be set in the normal working mode, the pull-down action of the pull-down circuit 63 can be set to be strong, so that the threshold is The switching point or excitation point of the voltage is a low positive voltage level in the warm-up test mode, so that the voltage value of the buffer circuit 32 when the voltage value of the negative voltage source VBB is lower than in the warm-up test mode can be set. The low-level VLD0 signal is output. In the case of the above-mentioned normal working mode, the threshold voltage excitation point of the pull-down circuit 63 and the pull-up circuit 61 can be set to reach -1.5V with respect to the voltage value of the negative voltage source VBB. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) Figure 7 is a circuit diagram of a specific embodiment of the settable buffer circuit (CBC) 32 in Figure 5 The circuit diagram of Sanli's voltage sensing circuit (VSC) 11 is also shown in this figure. In this embodiment, the voltage sensing circuit 11 includes P-channel field effect transistors (PFETs) P70-P73 and an inverter 71. The P-channel field-effect transistors P70-P73 are connected to each other, so that when the transistors are turned on, their channels can form a path from the voltage source VDD to the negative voltage source VBB. The gate and inversion of the p-channel field-effect transistor P70 71 output coupling Together. The input of the inverter 71 is used to receive the low power control signal (low This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm)) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 402802 B7 5. Invention description (丨 /) power control signal) LP. The low power control signal LP is a signal sent by a control circuit (not shown) to make the chip enter the low power mode. Once the low power control signal is established The P-channel field effect transistor P70 is turned off, that is, the conduction path from the voltage source tDD to the negative voltage source VSS is turned off to save power consumption. The source and drain of the P-channel field effect transistor P70 are connected to the voltage source VDD and the source of the P-channel field effect transistor P71 in the form of a diode, respectively. The gate of the P-channel field-effect transistor P71 is coupled to the wiring 34 and the source of the P-channel field-effect transistor P72, which is also a diode. The gate of the P-channel field-effect transistor P72 is coupled to the source of the P-channel field-effect transistor P73, which is also a diode. The gate and drain of the P-channel field effect transistor P73 are connected to the negative voltage source VBB together. In this embodiment, the settable buffer circuit (CBC) 32 includes an inverter 73, a capacitor 75, and a settable pull-up. A rising circuit (CPUC) 51, a pull-down circuit (PDC) 53 and an inverting buffer circuit 55. Among them, the settable pull-up circuit (CPUC) 51 is composed of P-channel field effect transistors P74, P77, and P78, the pull-down circuit (PDC) 53 is composed of N-channel field effect transistors N75, and the inverted buffer The circuit 55 is composed of three inverters 77, 78, and 79 connected in series. The capacitor 75 is composed of a P-channel field effect transistor. The source and the drain are connected in parallel to become the first electrode of the capacitor, and the gate of the transistor is used as the second electrode of the capacitor. The configuration and connection relationship of the settable buffer circuit (CBC) 32 are as follows. The first electrode and the second electrode of the capacitor are connected to the voltage source VDD and the wiring 34, respectively. In addition, the connection 34 is also connected to the field effect transistors N75, P74 and P78. 17 This paper wave size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ^ ------ ^ ------ 1T— ----- 0 /.. · (Please read the notes on the back before filling out this page) 402B02 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Α7 Β7 V. Gates of the invention description (U). The source and drain of the P-channel field effect transistor P74 are connected to the voltage source VDD and the node 57 respectively. The source and drain of the N-channel field effect transistor N74 are connected to the ground and the node 57 respectively. Node 57 is also connected to the drain of the P-channel field effect transistor P78. The source of the P-channel field-effect transistor P78 is connected to the drain of the P-channel field-effect transistor P77. The source of the P-channel field effect transistor P77 is connected to the voltage source VDD, and its gate is connected to the output of the inverter 73. An input terminal of the inverter 73 receives a control signal BI. The operation of the settable buffer circuit 32 in this embodiment is as follows. In the normal operating mode, the voltage value of the negative voltage source VSS is -1.5V. The output of the voltage sensing circuit 11 will cause the voltage on the wiring 34 to be approximately equal to the excitation point of the settable buffer circuit 32. In particular, the size of each P-channel field-effect transistor P70-P73 is adjusted in advance so that the voltage drop across each P-channel field-effect transistor can make the voltage level on wiring 34 in the normal working mode. 5V。 The following is designed to set the excitation point level of the buffer circuit 32, the voltage source VDD at this time is the voltage value of the normal operating mode, the voltage value of the negative voltage source VBB is -1.5V. Regarding the size of the P-channel field effect transistor P70-P73, you can use traditional commercial tools, such as HSPICE, to simulate and calculate the ideal size. In addition, the size adjustment of these transistors can be integrated into the required size by using the remaining small-sized components on the wafer through metal connections. The field effect transistors P74 and N75 form a complementary metal-oxide-semiconductor (CMOS) inverter. The threshold potential (or excitation point) of the inverter is determined by the size of the two transistors. Generally, increasing the size of the P-channel field effect transistor pull-up element (referring to increasing the ratio of width to length) increases the strength of the pull-up path. Similarly, increasing the size of the pull-down field-effect transistor element increases the strength of the pull-down path. The paper size applies the Chinese National Standard (CNS) μ Appearance (2 丨 〇X 297 mm) 1 ^. HI II — ^ 1 丨 ·· —--—1 i.-I--I (Please read the precautions on the back before filling this page)
、1T '線 經濟部中央標準局員工消費合作社印家 402802 A7 B7_ 五、發明説明（) 加。如果拉升路徑的強度大於拉降路徑的強度，則反相器的 激發點會是較高準位的正電壓值。如果拉降路徑的強度大於 拉升路徑的強度，則反相器的激發點會是較低準位的正電壓 值。以上改變激發點的技術早已是在積體電路中習知的技 術，本發明利用此一觀念應用於改變可設定緩衝電路32的 激發點準位。 P通道場效電晶體P77及P78構成一具選擇性地拉升路 徑與P通道場效電晶體P74平行，以改變由可設定拉升電路 51與拉降電路53所組成的反相器的拉升路徑之強度。在暖 機試驗模式時，控制信號BI爲確認信號，使得反相器73輸 出邏輯低準位信號至P通道場效電晶體P77。因此，使得介 於電壓源VDD與節點57間，由P通道場效電晶體P77與P 通道場效電晶體P78構成的路徑導通。拉升路徑被強化’由 可設定拉升電路51與拉降電路53 (即N通道場效電晶體 N75 )所組成的反相器的激發點因此提高。可設定拉升電路 51中的P通道場效電晶體P77與P78的尺寸可以預先經由模 擬暖機試驗模式的條件來求得適當的尺寸，以滿足該激發點 可對應於負電壓源的電壓爲-1. 0V ° 圖八是用以說明圖七所揭露的電路之操作時序圖。由電 壓感測電路11所產生的感測信號VLD的電壓準位及可設定 緩衝電路32的臨限電壓Vsr分別爲圖中的波形81及83所代 表。現在請參考圖七及圖八’在電源開啓進入暖機試驗模式 時，電荷泵19 (在圖三）會使負電壓源VBB的電壓向負值 增加如圖八中箭號211所指處。在暖機試驗模式時’可設定 19 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公— ------；-------^------J-----ά. (請先閲讀背面之注意事項再填寫本頁) . 經濟部中央棣準局員工消費合作社印製 403802 A7 B7 五、發明説明（丨；7 ) 拉升電路(CPUC)51使得由P通道場效電晶體P77及P78所構 成的拉升路徑致能(enable)，因此臨限電壓Vsr (即前述的 臨限電壓開關點或激發點）是一較高的準位如箭號83^斤 示。所以，在起始狀態時感測信號VLD的電壓準位高於可設 定緩衝電路32的臨限電壓激發點，使得可設定緩衝電路32 產生的信號VLD。爲邏輯高準位。 當負電壓源VBB的電壓到達-1. GV時，感測信號VLD的 電壓準位會達到可設定緩衝電路32在暖機試驗模式的臨限 電壓激發點，因此使得可設定緩衝電路32輸出的信號VLD。 爲邏輯低準位，該邏輯低準位的VLD。信號會使電荷泵19停 止動作。如此一來，便可以使得負電壓源VBB的電壓值大約 爲-1. 0V，如圖中箭號213所指處。 在正常工作模式時，控制信號BI爲非確認的控制信號， 使得反相器73輸出邏輯高準位信號至P通道場效電晶體 P77。因此，使得介於電壓源VDD與節點57間，由P通道場 效電晶體P77與P通道場效電晶體P78構成的路徑截止。所 以實際上P通道場效電晶體P77及P78不會影響可設定緩衝 電路32的臨限電壓激發點，也就是說該激發點此時僅與場 效電晶體P74及N75有關。特別是，場效電晶體P74及N75 與電壓感測電路11裡的P通道場效電晶體的尺寸是預先設 計好的，可以使得負電壓源VBB的電壓正好爲-1. 5V時，正 常工作模式下的可設定緩衝電路32正好達到其臨限電壓的 激發點。 根據以上所述，當控制信號BI爲非確認時，使可設定 本^^1適用中國國家標準（CNS) A4規格（21Qx297公捷)' '~ I---.裝------訂丨-----、旅 * -.··- (請先閲讀背面之注意事項再填寫本頁) . AV 402802 B7 經濟部中央標率局員工消费合作社印製 五、發明説明（if) 緩衝電路32爲正常工作模式，其中的可設定拉升電路51的 Ρ通道場效電晶體Ρ77及Ρ78失去作用，造成臨限電壓VsT 爲一較低的準位如圖八中箭號85與波形832所示。因爲此時 臨限電壓激發點較低，可設定緩衝電路32輸出信號VLD◦會 發生由低準位至高準位的轉態現象如圖中箭號86所示，該 信號將使電荷泵19再次起動。最後負電壓源VBB的電壓值 變化如圖中波形214處所示。 當負電壓源VBB的電壓值到達-1. 5V時，感測信號VLD 的電壓準位將達到正常工作模式時可設定緩衝電路32的臨 限電壓激發點，使得可設定緩衝電路32輸出信號VLD。爲邏 輯低準位使電荷泵19停止動作。因此負電壓源VBB的電壓 值將大約保持在-1. 5V如圖八中波形216處所示》綜上所 述，可設定緩衝電路32產生的VLD。信號基本上等同於圖一 中的信號VLD。，但是本發明使用較少的電路。 圖九是用以解釋圖六的可設定緩衝電路的一個實施例 之詳細電路圖，該圖中具有如圖六所示的可設定拉降電路。 在此實施例中，可設定緩衝電路90取代了圖七中的可設定 緩衝電路32，其不同處是以可設定的拉降路徑取代拉升路 徑。不過兩者的基本觀念是相同的；亦即，增加拉升相對於 拉降的強度可以提高互補金氧半導體反相器的臨限電壓激 發點至一較高的準位，同樣的若增加拉降相對於拉升的強度 可以降低互補金氧半導體反相器的臨限電壓激發點至一較 低的正電壓準位。 該可設定緩衝電路90的實施例包括，反相緩衝器55， _ 21 . 、 0¾ (請先閱讀背面之注意事項再填寫本頁) r -9 Γ 本紙張尺度適用中國國家標準（CNS ) A4蛛格（210X297公瘦）1T 'line Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China 402802 A7 B7_ V. Description of Invention () Canada. If the strength of the pull-up path is greater than the strength of the pull-down path, the excitation point of the inverter will be a higher level of positive voltage value. If the strength of the pull-down path is greater than the strength of the pull-up path, the excitation point of the inverter will be a positive voltage at a lower level. The above technique for changing the excitation point has long been known in integrated circuits. The present invention uses this concept to change the level of the excitation point of the settable buffer circuit 32. The P-channel field-effect transistors P77 and P78 form a selective pull-up path parallel to the P-channel field-effect transistor P74 to change the pull-up of an inverter composed of a programmable pull-up circuit 51 and a pull-down circuit 53 The strength of the ascent path. In the warm-up test mode, the control signal BI is a confirmation signal, so that the inverter 73 outputs a logic low level signal to the P-channel field effect transistor P77. Therefore, the path formed by the P-channel field-effect transistor P77 and the P-channel field-effect transistor P78 between the voltage source VDD and the node 57 is turned on. The pull-up path is strengthened 'so that the excitation point of the inverter composed of the settable pull-up circuit 51 and the pull-down circuit 53 (i.e., N-channel field effect transistor N75) is increased. The size of the P-channel field effect transistors P77 and P78 in the pull-up circuit 51 can be set. The appropriate size can be obtained in advance through the conditions of the simulated warm-up test mode, so that the voltage at which the excitation point can correspond to the negative voltage source is -1. 0V ° Figure 8 is a timing diagram for explaining the operation of the circuit disclosed in Figure 7. The voltage level of the sensing signal VLD generated by the voltage sensing circuit 11 and the threshold voltage Vsr of the settable buffer circuit 32 are respectively represented by waveforms 81 and 83 in the figure. Please refer to Fig. 7 and Fig. 8 '. When the power is turned on and enters the warm-up test mode, the charge pump 19 (in Fig. 3) will increase the voltage of the negative voltage source VBB to a negative value as shown by the arrow 211 in Fig. In the warm-up test mode, '19 paper sizes can be set to the Chinese National Standard (CNS) A4 specification (210X297 male — ------; ------- ^ ------ J-- --- ά. (Please read the precautions on the back before filling out this page). Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 403802 A7 B7 V. Description of the invention (丨; 7) The pull-up circuit (CPUC) 51 makes The pull-up path formed by the P-channel field-effect transistors P77 and P78 is enabled, so the threshold voltage Vsr (that is, the aforementioned threshold voltage switching point or excitation point) is a higher level such as an arrow Therefore, the voltage level of the sensing signal VLD in the initial state is higher than the threshold voltage excitation point of the settable buffer circuit 32, so that the signal VLD generated by the buffer circuit 32 can be set. It is a logic high level When the voltage of the negative voltage source VBB reaches -1. GV, the voltage level of the sensing signal VLD will reach the threshold voltage excitation point of the settable buffer circuit 32 in the warm-up test mode, so that the output of the buffer circuit 32 can be set The signal VLD. Is a logic low level, and the logic low level VLD. Signal causes the charge pump 19 to stop operating. In this way, the voltage value of the negative voltage source VBB can be approximately -1.0V, as indicated by the arrow 213 in the figure. In the normal working mode, the control signal BI is an unconfirmed control signal, so that it is inverted The device 73 outputs a logic high level signal to the P-channel field effect transistor P77. Therefore, the path formed by the P-channel field effect transistor P77 and the P-channel field effect transistor P78 is cut off between the voltage source VDD and the node 57 So in fact, the P-channel field effect transistors P77 and P78 will not affect the threshold voltage excitation point of the settable buffer circuit 32, that is, the excitation point is only related to the field effect transistors P74 and N75 at this time. In particular, The field effect transistors P74 and N75 and the P-channel field effect transistor in the voltage sensing circuit 11 are pre-designed so that the voltage of the negative voltage source VBB is exactly -1.5 V, in the normal working mode. The buffer circuit 32 can be set to exactly reach the threshold of its threshold voltage. According to the above, when the control signal BI is non-confirmed, the settable value ^^ 1 is applicable to the Chinese National Standard (CNS) A4 specification (21Qx297). '' ~ I ---. Install ------ Order 丨 -----旅 *-. ··-(Please read the notes on the back before filling out this page). AV 402802 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (if) The buffer circuit 32 is in normal working mode. Among them, the P-channel field effect transistors P77 and P78 of the settable pull-up circuit 51 fail, causing the threshold voltage VsT to be a lower level, as shown by the arrow 85 and the waveform 832 in FIG. 8. Because the threshold voltage threshold is low at this time, the output signal VLD of the buffer circuit 32 can be set. A transition phenomenon from a low level to a high level will occur as shown by the arrow 86 in the figure. This signal will make the charge pump 19 again. start. Finally, the voltage value of the negative voltage source VBB changes as shown by waveform 214 in the figure. When the voltage value of the negative voltage source VBB reaches -1.5V, the voltage level of the sensing signal VLD will reach the normal working mode. The threshold voltage excitation point of the buffer circuit 32 can be set, so that the output signal VLD of the buffer circuit 32 can be set. . The charge pump 19 is stopped for a logic low level. Therefore, the voltage value of the negative voltage source VBB will be maintained at approximately -1.5V as shown by the waveform 216 in Figure 8 ". In summary, the VLD generated by the buffer circuit 32 can be set. The signal is basically equivalent to the signal VLD in Figure 1. However, the present invention uses fewer circuits. Fig. 9 is a detailed circuit diagram for explaining an embodiment of the settable buffer circuit of Fig. 6, which has a settable pull-down circuit as shown in Fig. 6. In this embodiment, the settable buffer circuit 90 replaces the settable buffer circuit 32 in Fig. 7. The difference is that a settable pull-down path replaces the pull-up path. However, the basic concepts of the two are the same; that is, increasing the strength of the pull-up relative to the pull-down can increase the threshold voltage excitation point of the complementary metal oxide semiconductor inverter to a higher level. Decreasing the strength relative to the pull-up can reduce the threshold voltage excitation point of the complementary metal oxide semiconductor inverter to a lower positive voltage level. The embodiment of the settable buffer circuit 90 includes an inverting buffer 55, _ 21., 0 ¾ (Please read the precautions on the back before filling out this page) r -9 Γ This paper size applies Chinese National Standard (CNS) A4 Spider grid (210X297 male thin)
40260S 經濟部中央搮準扃負工消费合作社印笨 A7 ____B7_ 五、發明説明（I 了） 可設定拉降電路63 (由N通道場效電晶體N75、N91-N93 所構成）以及拉升電路61 (由P通道場效電晶體P74所構 成）。與圖七的實施例不同的是N通道場效電晶體N75的源 極接到節點95而非地電位。節點95同時也接至N通道場效 電晶體N91、N92的汲極。另外，與圖七的可設定緩衝電路 32不同的是反相器的輸出端接至N通道場效電晶體N91的閘 極而非P通道場效電晶體P77。可設定緩衝電路90的內部 連線關係爲：N通道場效電晶體N91的源極接至地電位。N 通道場效電晶體N92的閘極與源極分別接至接線34以接收 信號VLD，以及N通道場效電晶體N93的汲極。N通道場效 電晶體N93的閘極及源極分別接至接線36以接收信號BI， 以及地電位。 另外，與圖七的可設定緩衝電路32不同的是此實施例 改變可設定路徑的強度是藉著改變該路徑的有效通道長度 (effective channel length)，以代替致能 / 失能 (enabling/disabling)—個平行的通道路徑。當然，該使用 平行路徑的方式也可以適用在可設定拉降電路63的其他實 施例上，同理，可設定路徑長度的方式也可以使用在可設定 拉升電路51的其他實施例上。可設定緩衝電路90的臨限電 壓激發點可能有一點點不同於圖七的可設定緩衝電路32， 所以電壓感測電路11可能需要做一些調整以達到所需的要 求。 在暖機試驗模式時，控制信號BI爲確認信號，故透過 反相器73使N通道場效電晶體N93導通，而N通道場效電 _ ____22___ 本紙張尺度適用中國國家榡準（CNS ) A4規格（2丨OX297公釐） ^----裝------^tTJ-----線 (請先閲讀背面之注意事項再填寫本頁) A7 402802 五、發明説明（/) 晶體N91關閉。結果是，在暖機試驗模式時，N通道場效電 晶體N75、N92及N93形成拉降路徑。該拉降路徑有一相當 長的有效通道長度。因此，在暖機試驗模式時，拉降路徑的 強度相當弱，所以造成可設定緩衝電路90有較高的臨限電 壓激發點。 相對的，在正常工作模式時，控制信號BI爲非確認信 號，故透過反相器73使N通道場效電晶體N91導通，而N 通道場效電晶體N93關閉。結果是，在正常工作模式時，N 通道場效電晶體N75及N91形成拉降路徑。因只有兩個電晶 體所以該拉降路徑相對於暖機試驗模式時有一較短的有效 通道長度。因此，在正常工作模式時，拉降路徑的強度較強， 所以造成可設定緩衝電路90有較低的臨限電壓激發點。根 據以上所述可知，對於信號VLD與BI，可設定緩衝電路90 提供一與圖七中的可設定緩衝電路30相同的功能，且均產 生信號VLD。。 以上對於本發明一種使用於積體電路上的動態調整電 壓源裝置的詳細實施例之描述並不是用來限制本發明的架 構。經由以上對本發明的揭露，凡熟習該類技術者皆能應用 本發明之技術於其他種類的電壓源供應裝置上，例如正電壓 源供應裝置。當然還有其他不同的電壓感測電路也可以應用 在其他不同的實施例上。另外，其他已知的邏輯電路也可以 用來實現前面提出的可設定電壓緩衝電路32及90，當然其 中控制信號（例如信號BI )邏輯高電位動作或低電位動作 的關係是可以互換的。根據以上對本發明較佳實施例的揭 -------23____ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -------^----裝------訂J-----線 - C (請先閲讀背面之注意事項再填寫本頁) · - 經濟部中央標隼局員工消費合作社印製 402δ0 Α7 Β7 五、發明説明（>< ) 露，其他不同形式的改變均應視爲不脫離本發明之精神與範 經濟部中央標準局員工消費合作社印製40260S Ministry of Economic Affairs, Central, Standard, Consumer, and Consumer Cooperatives, Ben Ben A7 ____B7_ 5. Description of the Invention (I) The pull-down circuit 63 (consisting of N-channel field effect transistors N75, N91-N93) and pull-up circuit 61 (Composed of P-channel field effect transistor P74). The difference from the embodiment of FIG. 7 is that the source of the N-channel field effect transistor N75 is connected to the node 95 instead of the ground potential. Node 95 is also connected to the drains of N-channel field effect transistors N91 and N92. In addition, unlike the settable buffer circuit 32 of FIG. 7, the output terminal of the inverter is connected to the gate of the N-channel field effect transistor N91 instead of the P-channel field effect transistor P77. The internal connection relationship of the buffer circuit 90 can be set as follows: the source of the N-channel field effect transistor N91 is connected to the ground potential. The gate and source of the N-channel field effect transistor N92 are connected to the connection 34 to receive the signal VLD, and the drain of the N-channel field effect transistor N93. The gate and source of the N-channel field effect transistor N93 are connected to the connection 36 to receive the signal BI and the ground potential. In addition, the difference from the settable buffer circuit 32 of FIG. 7 is that in this embodiment, the strength of the settable path is changed by changing the effective channel length of the path instead of enabling / disabling. ) —A parallel channel path. Of course, the method using the parallel path can also be applied to other embodiments in which the pull-down circuit 63 can be set. Similarly, the method in which the path length can be set can also be used in other embodiments in which the pull-up circuit 51 can be set. The threshold voltage excitation point of the settable buffer circuit 90 may be slightly different from the settable buffer circuit 32 of FIG. 7, so the voltage sensing circuit 11 may need to be adjusted to meet the required requirements. In the warm-up test mode, the control signal BI is a confirmation signal, so the N-channel field-effect transistor N93 is turned on through the inverter 73, and the N-channel field-effect transistor _ __22___ This paper standard applies to China National Standard (CNS) A4 Specifications (2 丨 OX297mm) ^ ---- install -------- ^ tTJ ----- line (please read the precautions on the back before filling this page) A7 402802 V. Description of the invention (/) Crystal N91 is off. As a result, in the warm-up test mode, the N-channel field effect transistors N75, N92, and N93 form a pull-down path. The pull-down path has a considerable effective channel length. Therefore, in the warm-up test mode, the strength of the pull-down path is relatively weak, so that the buffer circuit 90 can be set to have a higher threshold voltage excitation point. In contrast, in the normal operating mode, the control signal BI is a non-confirmation signal, so the N-channel field effect transistor N91 is turned on through the inverter 73, and the N-channel field effect transistor N93 is turned off. As a result, in the normal operating mode, the N-channel field effect transistors N75 and N91 form a pull-down path. Because there are only two electric crystals, the pull-down path has a shorter effective channel length compared to the warm-up test mode. Therefore, in the normal working mode, the strength of the pull-down path is strong, so that the buffer circuit 90 can be set to have a lower threshold voltage excitation point. Based on the above, it can be known that, for the signals VLD and BI, the settable buffer circuit 90 provides a function similar to that of the settable buffer circuit 30 in FIG. 7, and both generate the signal VLD. . The above description of the detailed embodiment of the dynamic adjusting voltage source device used in the integrated circuit of the present invention is not intended to limit the structure of the present invention. Through the above disclosure of the present invention, anyone skilled in this type of technology can apply the technology of the present invention to other types of voltage source supply devices, such as positive voltage source supply devices. Of course, there are other different voltage sensing circuits that can also be applied to other different embodiments. In addition, other known logic circuits can also be used to implement the previously settable voltage buffer circuits 32 and 90. Of course, the relationship between the control signal (such as signal BI) logic high-potential action or low-potential action can be interchanged. According to the above disclosure of the preferred embodiment of the present invention ------- 23____ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ------- ^ ---- install- ---- Order J ----- Line-C (Please read the notes on the back before filling this page) ·-Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 402δ0 Α7 Β7 V. Description of the invention (> <) Exposure, other different forms of changes should be regarded as not deviating from the spirit of the present invention and printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy
(請先閲讀背面之注意事項再填寫本I) 本紙張尺度適用中國國家標準（CNS )八料見格（210X297公釐） 裝_ 訂| 線(Please read the notes on the back before filling in this I) This paper size is applicable to the Chinese National Standard (CNS) Yakiri (210X297 mm). _ Order | Line