TW406368B - Method for manufacturing the bonding pad of integrated circuit - Google Patents

Abstract

A method for manufacturing the bonding pad of integrated circuit, comprising the steps of: depositing a insulator layer on a semiconductor substrate, and then defining the via; depositing a conductive material in via and on said insulator layer; removing the conductive material on insulator layer by etching process; proceeding photolithography process to define the bonding pad and remove the conductive material on unprotected area in insulator layer; and depositing and defining a passivation layer to protect the circuit therebelow from the interference of moisture or other materials that may result in circuit short. The point of the present invention is to proceed separately the manufacture for the top layer of interconnection and the bonding pad and to locate the pad above said interconnection. This could solve the conventional problem of short contact due to the thin conductive lateral deposition of the bonding and increase the integration degree of the device.

Description

Printed by Shelley Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs 406368 5. Field of Invention (<) Field of Invention = The present invention relates to an integrated circuit wiring pad insulation structure, especially for the design of bonding pads Encountered pitting problems caused by etch back when the pads are in contact with the wiring. Background of the Invention: Integrated circuits can be defined as electronic products that are composed of a plurality of electronic components and circuits. The manufacturing process of integrated circuits is very complicated. One of the steps is the production of solder pads connected to the outside world. Please refer to Figure 1. A. The production process of the conventional method is as follows: firstly define the uppermost interconnections and bonding pads, and then perform wire bonding operations so that the connection through the bonding wires can connect the internal signals of the integrated circuit with the outside world. After the integrated circuit manufacturing process technology has entered the deep sub-micron, the difference between the size of the uppermost interconnects and the pads has become larger and larger. When Damascene is used as a planarization technology, chemical mechanical polishing of the metal (chemical (mechanical polishing; CMP) During the planarization process, the difference in polishing rate between the two also becomes larger. When the uppermost interconnects reach the end of the etching, the pads have also caused excessive etching, forming a middle depression. In the conventional manufacturing process, FIG. 1B to E are the process diagrams of the tangent section from 1-Γ in the above diagram for the design of the Bonding Pad in FIG. 1A, and 301, 302, and 303 in FIG. 1 are diagrams. A B interlayer window 9 and a pad contact window 900 filled with a conductive substance are formed by conductive wires. On the semiconductor substrate 10 that has completed the previous process, a silicon oxide is deposited as the insulating layer 20, which is defined by lithography and etching processes. The interlayer window 9 and the pad contact window 900 which are connected to the uppermost layer are connected. Use sputtering or chemical vapor deposition (please read the precautions on the back before filling this page) The size of the bound paper is in accordance with the Chinese National Standard (CNS > A4 size (210X297mm) 406368 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (>)deposition; CVD) and other methods to form the first conductivity Materials 30 such as: (A1), aluminum copper (CuAl), copper (Cu), tungsten (W), or other conductive materials in the interlayer window 9, the pad contact window 900, and the insulating layer 20, Removal of the first conductive material 30 on the insulating layer 20 by chemical mechanical polishing In order to form the conductive interconnects 30a and the solder pads 300, in the general process, the solder pad contact window 900 needs to form a large opening to facilitate subsequent wiring work, but when the size of the upper-level interconnects and the solder pads are significantly different. In the process of chemical mechanical polishing, at the same time that the innermost interconnection of the upper layer reaches the end of the etching, the pad 300a has caused an over-etching situation, forming a state of intermediate depression, as shown in FIG. 1D. Generally, when the pad contacts the window area, When the thickness is greater than 50 μιη × 50 μιη, the thickness of the first conductive material deposited by the pad 300 after the chemical mechanical polishing, the gap between the lowest point in the middle and the periphery may reach 3000 ~ 4000 angstroms, or even greater. In this way, during the subsequent wiring process, the contact area between the pads and the wiring is too low, resulting in poor contact between the wiring and the pads, which may cause the wiring to fall off or increase external interference (reducing the signal / noise ratio (S / N ratio) )), Especially when the protective layer 40 is formed by subsequent deposition of silicon oxide, silicon nitride, or the like, because the surface flatness becomes worse, the phenomenon of peeling easily occurs. Summary of the invention: In view of this, the main purpose of the present invention is to provide a method for forming a pad in an integrated circuit, which solves the problem that the width of the contact window of the deposited pad is higher than the uppermost layer when the pad is formed in the conventional process. The interconnect window width is large, resulting in a natural depression after CMP etchback, which causes a problem of poor speech contact. _ 3 This paper size uses China National Standard (CNS) A4 (210X297 mm) {Please read the precautions on the back before filling this page)

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.y-· I Yin Ben, Consumers Cooperative of Central Bureau of Standards, Ministry of Economic Affairs _ 406368_iy___ 5. Description of the invention (3) The secondary purpose of the present invention is to provide a manufacturing method for forming solder pads in integrated circuits, providing a comparative Flatten the contact surface, reduce the peeling of the protective layer, and improve the production yield and electrical reliability of the integrated circuit gasket. The present invention uses the following process method to achieve the above-mentioned objective: firstly, an insulating layer is deposited on a semiconductor substrate that has completed the previous process, and then a lithographic etching is used to define an interlayer window. Then, sputtering is used. Or chemical vapor deposition (CVD) and other methods to deposit the first conductive material in the interlayer window and the insulating layer, and then etch back by chemical mechanical polishing to deposit the first conductive material on the insulating layer. Removal or partial removal to form a conductive interconnect structure, which is deposited by sputtering or chemical vapor deposition (CVD), and then the first conductive layer left on the insulating layer after etch back Materials or separately deposit a second conductive material, define the pad structure by lithography, and then deposit silicon oxide or silicon nitride and other materials to define the pad structure without forming a protective layer of the pad structure. . In order to allow your reviewers to further understand and approve the purpose, features, and effects of the present invention, we will explain it in detail with the illustrations as follows: Brief description of the diagram: Figure 1A is a pad formed in a traditional integrated circuit The top view of the manufacturing method is shown in Fig. 1. B through E are sectional views taken along the tangent line 1-Γ. Fig. 2 is an upper view of the process of forming a pad by the padless contact window of the present invention. FIG. 3 is a circle on the process of forming a pad with a contact window of a pad according to the present invention. Figure 4A ~ 4 | The pad design in the first embodiment of the present invention is shown in Figure 2 along 2-2 'of li 4 This paper is suitable for the country's fell * Feng (CNS > A4 threat (210X297 public reply)' — (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs __406368_B -____ V. Description of the Invention (/ [) The cross section of the manufacturing process is shown in Figure 5A ~ 5g. The design of the solder pad in the second embodiment is shown in the section 3-3 '^^ of the third figure. The drawing number in the figure is explained: 9 ~ boundary window 10 ~ ^ plate 20-insulating layer 30 ~ first conductive material Layer 3 pad structure 33 ~ first conductive material layer 34-first conductive material layer 40A protective layer 50-second conductive material layer 90 ^ pad contact window 1 100-second conductive material layer 200-first conductive The material structure layer 300 # pad structure 301 ~ the uppermost inner wiring 302 ~ the uppermost inner wiring 303 pad wire 6004 pad structure detailed description: the first embodiment circle 2 is the pad design of the first embodiment, and Figure 4 It is a cross-section process drawing of 2-2 'in Yuan Erzhong. First, the upper-level interconnection is performed on a semiconductor substrate 10 that has completed the previous process. After fabrication, the insulating layer 20 is deposited first, and then the interlayer window 9 is defined by lithographic etching. The key point of the present invention is to avoid the depression phenomenon caused by chemical mechanical polishing (CMP) during the formation of the solder pads during the deposition to form the wiring. The problem of poor contact with the solder pads, so the solder pads and the upper-layer interconnect are separately formed in two stages. The material of the insulation layer can be oxygen-based paper size, using the Chinese national standard (CNS M4 specification (210X297 Mm Γ (Please read the notes on the back before filling in this page) —pack '

， 1T 5_ Printed by the Shell Consumer Cooperative of the Central Samples Bureau of the Ministry of Economic Affairs 406368_ »: ___________ V. Description of the Invention (γ) Silicon oxide or Silicon-Oxygen-Nitride, with a deposition thickness of 2000 to Between 10,000 angstroms, successively, as shown in Figures 4B and C, a first conductive material 30 is deposited on the interlayer window 9 and the insulating layer 20, and then the first first layer is deposited on the insulating layer 20 by etch back. The conductive material 30 is removed to form a conductive interconnect 30a. The deposition is performed by sputtering or chemical vapor deposition (CVD) to deposit aluminum (A1) and aluminum copper (CuAl) with a thickness of 4000 to 20,000 angstroms. , Copper (Cu), tungsten (W), or other conductive materials, and the etch-back is performed by chemical mechanical polishing (CMP) to remove the first conductive material above the insulating layer. Generally, the above process is used in the process. Before the etch-back step, a layer of silicon nitride (Si3N4) or polycrystalline silicon is deposited as a barrier layer (not shown) after the deposition of the insulating layer 20 as the detection of the etching end point during CMP etch-back. As shown in E, a second conductive material 50 is deposited on the insulating layer 20, the first On the electrical material 30a, a pad 300 is defined, and then a protective layer 40 is deposited and defined to complete the pad structure. The second conductive layer 50 described above is deposited by sputtering or chemical vapor deposition. The thickness is between 2000 and 8000 angstroms. It uses aluminum (A1), aluminum copper (CuAl), copper (Cu), tungsten (W) or other conductive materials, and the protective layer 40 uses silicon oxide. Or silicon nitride, it is best to use silicon nitride, because silicon nitride has a higher density to prevent the intrusion of moisture or other gases from the outside to cause short-circuiting of the wire. In addition, in the first embodiment, as shown in FIG. 4F, after depositing the first conductive material layer, CMP etchback may be used to remove only the first conductive material 30 deposited on the insulating layer 20 above. It is not necessary to completely remove the first conductive material layer, and the thickness of the first conductive material layer 33 on the insulating layer 20 is kept between 2000 and 8000 angstroms. National Standards (CNS) A4 (210X297mm) One --------- ¾— (Please read the precautions on the back before filling this page)

* 1T The Printing Industry Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, India 406368 ir 5. Explanation of the invention ((?) Defines the pad structure and the process of forming a protective layer 'and omits the deposition of the second conductive layer. Second Embodiment The present invention can also The second embodiment operates. The same figure in the circle represents the same level as the first embodiment. Figure 3 shows the pad design of the second embodiment. The difference between the first embodiment and the second embodiment lies in the second embodiment. The definition of the pad contact window 90 in the embodiment is similar to the conventional structure, but the width of the pad contact window 90 is similar to the interlayer window 9, and FIG. 5 is a cross-sectional process diagram of 3-3 'in FIG. Referring to FIG. 4, first, the uppermost interconnection is produced on a semiconductor substrate 10 that has completed the previous process. After the insulation layer 20 is deposited, the interlayer window 9 and the pad contact window are defined by lithography and etching. 90, which can avoid conventional problems. The insulation layer material and deposition thickness are as described in the first embodiment. As shown in Figures 5B and 5C, the first conductive material 30 is deposited on the interlayer window 9 and the solder joint. The contact window 90 is neutralized on the insulating layer 20 The first conductive material 30 deposited on the insulating layer 20 is removed by etch-back to form a conductive interconnect 30a and a conductive wiring 31 structure connected to the bonding pad. The deposition is performed by sputtering or chemical vapor deposition. (CVD) method to deposit aluminum (A1), aluminum copper (CuAl), copper (Cu), tungsten (W) or other conductive materials with a thickness between 4000 and 20,000 angstroms, and the etchback is performed by chemical mechanical polishing ( CMP) method to remove the first conductive material layer 30 above the insulating layer, and then, as shown in FIG. 5D, deposit a second conductive material 50 on the insulating layer 20, the interlayer window 30a, and the pad contact window 31 Above, the second conductive layer 50 mentioned above is using sputtering or chemical vapor phase 7 (please read the precautions on the back before filling this page) > A4 size (210X297 mm)

Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative II II 406368 5. Description of the invention (?). It is deposited by thickness of 2000 to 8000 angstroms. It uses aluminum (A1), aluminum copper (CuAl), copper (Cu), tungsten (W), or other conductive materials. Then, as shown in FIG. 5E, the second conductive material layer 50 defines the pad 600 on the pad contact window, and then deposits the pad structure without forming a pad structure. The protective layer 40 is used to complete the pad structure, and the protective layer 40 is made of silicon oxide or silicon nitride. In addition, in the second embodiment, as shown in FIG. 5F, after depositing the first conductive material layer, the CMP can still be etched back to deposit only the first conductive material 30 on the insulating layer 20 The first conductive material layer does not need to be completely removed, and the thickness of the first conductive material layer 34 on the insulating layer 20 is between 2000 and 8000 angstroms, and then the subsequent definition of the pad structure and the formation of a protective layer is performed. Process. The present invention can also be applied to a semiconductor substrate having only a pad structure on the surface, and the pad structure consists of only one metal layer. To sum up, the integrated circuit wire bonding pad provided by the present invention has the following advantages over the conventional technology: 1. The present invention forms a pad on the upper surface of the substrate and forms a pad above the pad, which significantly improves the pad. In the conventional technique, the contact between the gasket and the sag is caused by the shim deposition after chemical mechanical polishing. 2. Because its top surface is flatter than that in the conventional technique, it also reduces the contact between the gold gasket and the conventional process. Peeling may occur between polycrystalline silicon or the cover. 3. The design of the present invention that the gasket is made over the wire or the area of the gasket is reduced can significantly increase the density of the components. 8 ---------- install-- (please read the precautions on the back before filling in this page), * τ. 丨 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 406368 V. Description of the Invention (j *) The present invention is described through specific embodiments to explain the principles and spirit of the present invention. It should be understood that the present invention is not limited to the specific embodiments disclosed. Therefore, the principles and Changes in any relevant details made below the scope should be considered as further embodiments of the present invention. (Please read the notes on the back before filling this page)

* 1T Printed by the Consumers' Cooperatives of the Central Bureau of Standards and Accreditation of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) Α4 (210X tear mm)

Claims (1)

406368 A8 B8 C8 D8 Printed by the Consumer Sample Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs *. 6. Scope of Patent Application 1. A manufacturing method for forming solder pads in integrated circuits, including: (a) depositing an insulating layer before the completion of the previous process On a semiconductor substrate; (b) etching said insulating layer to define a via; (i) depositing a first conductive material in the via and said insulating layer; (d) applying said first conductive The material is partially etched back to form the gold interconnect; (e) the pad structure is defined for the first conductive material remaining above a via window; (f) a protective layer is deposited on the insulating layer There is no area on the pad structure. 2. The manufacturing method of forming a bonding pad in a integrated circuit as described in item 1 of the scope of the patent application, wherein the first conductive material layer is aluminum (A1), aluminum copper (CuAl), copper (Cu ), Tungsten (W), or one of the other conductive materials. 3. The manufacturing method of forming a bonding pad in an integrated circuit according to item 1 of the scope of the patent application, wherein the first conductive material is deposited with a thickness between 4000 and 20,000 angstroms. 4. A method for manufacturing a solder pad in an integrated circuit as described in item 1 of the scope of the patent application, wherein the uranium engraving is performed by a chemical mechanical polishing (CMP) method. 5. A method for forming a solder pad in an integrated circuit as described in item 1 of the scope of the patent application, in which the first conductive material described in the first conductive material is partially etched back and the thickness of the insulating layer remains on the insulating layer. Between 2000 and 8000 Angstroms. 6. —A kind of manufacturing method for forming solder pads in integrated circuits, including: 10 (Please read the precautions on the back before filling this page) This paper is not suitable for China • Family (CNS) A4 specification (210X297) (%) ♦ Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, 11 406368 A8 B8 C8 D8 π, patent application scope (a) depositing an insulation layer on the semiconductor substrate that has completed the previous process; (b) etching the insulation layer mentioned Defining a via window; (c) depositing a first conductive material in the via window and said insulating layer; (d) etching back the first conductive material to form a metal wire; (e) ) Depositing a second conductive material layer on the interlayer window and the insulating layer; (f) etching the second conductive material above the interlayer window to define a pad structure; (g) depositing a protective layer on A region where a spacer structure is not formed on the insulating layer. 7. A method for manufacturing a solder pad in a integrated circuit according to item 6 of the scope of the patent application, wherein the first conductive material layer is aluminum (A1), aluminum copper (CuAl), copper (〇) 〇, tungsten (W) or one of the other conductive materials. 8. A method for forming a bonding pad in an integrated circuit as described in item 6 of the scope of the patent application, wherein the deposition thickness of the first conductive material is between Between 4000 and 20000 Angstroms. 9. A method for forming a bonding pad in an integrated circuit as described in item 6 of the patent application scope, wherein the etch-back is performed by a chemical mechanical polishing (CMP) method. 10. A method for forming a bonding pad in an integrated circuit according to item 6 of the scope of application for a patent, wherein the second conductive material is deposited with a thickness between 2000 and 8000 angstroms. The manufacturing method of the dance mat in the body circuit includes: 11 (Please read the precautions on the back before filling this page) This paper is scaled to the China National Sample Rate (CNS) Α4 specification (210X297) and 406368 A8 B8 C8 D8 Printed by the Shellfish Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs *. Patent scope: (a) depositing an insulating layer on the semiconductor substrate that has completed the previous process; (b) defining an interlayer window and a pad contact window on the insulating layer; (c) depositing a first conductive material on the substrate Layer windows, pad contact windows, and said insulating layer; (d) Partial etch-back of the first conductive material described above to form a gold interconnect; (e) Over a dielectric window The remaining first conductive material defines the gasket structure; ⑺ deposits a protective layer on the insulation layer in the area where the gasket structure is not formed., 12 · A product as described in item 11 of the scope of patent application A method for manufacturing a solder pad in a circuit, wherein the first conductive material layer is one of aluminum (A1), aluminum copper (CuAl), copper (Cu), tungsten (W), or one of other conductive materials ❶ 13. The manufacturing method of forming a bonding pad in an integrated circuit according to item 11 of the scope of patent application, wherein said first conductive material is deposited with a thickness between 4000 and 20,000 angstroms.丨 A manufacturing method of forming a bonding pad in an integrated circuit according to item 1, wherein said The etch back method uses a chemical mechanical polishing (CMP) method. 15. A manufacturing method for forming a bonding pad in an integrated circuit as described in item 丨! Of the patent application scope, wherein the first conductive material is partially The thickness remaining on the insulating layer after etch back is between 2000 and 8000 angstroms. A method for manufacturing a solder pad in a circuit includes: (a) depositing an insulating layer on a semiconductor substrate that has completed the previous process; 12- ------ I — (Please read the notes on the reverse side before filling out this page) The size of the paper used in this edition is China_Fujian Standard (CNS) A4 (210X297 mm). Industrial and consumer cooperative seal *. Λ8 B8406368 dI Sixth, the scope of patent application (b) Define the interlayer window and the pad contact window on the insulation layer; (c) Deposit the first conductive material on the interlayer window and the pad In the contact window and on the insulation layer; (d) etch back the first conductive material; (e) deposit a second conductive material layer on the interlayer window, the pad contact window and the insulation layer (F) etching a second conductive material described above a via window, defining Gasket structure; (g) Depositing a protective layer on the insulation layer where no gasket structure is formed. 17. A method for manufacturing a bonding pad in an integrated circuit according to item 16 of the scope of the patent application, wherein the first conductive material layer is aluminum (A1), aluminum copper (CuAl), copper ( Cu), tungsten (W), or other conductive materials 18. The method for manufacturing a bonding pad in an integrated circuit as described in item 16 of the scope of patent application, wherein the first conductive material is deposited with a thickness between Between 4000 and 20000 Angstroms. 19. A manufacturing method of forming a bonding pad in an integrated circuit as described in item 16 of the scope of the patent application, wherein the etch-back is performed using a chemical mechanical polishing (CMP) method. 20. A manufacturing method for forming a bonding pad in an integrated circuit as described in item 16 of the scope of the patent application, wherein said second conductive material has a deposition thickness between 2000 and 8000 Angstroms "----- ---- n I n IIT (Please pay attention to the “If” on the back before filling in this page) · 13 This paper size uses China National Standard (CNS) A4 specification (2 丨 0X297 public envy)