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TW396473B - Ball grid array package - Google Patents

Ball grid array package Download PDF

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Publication number
TW396473B
TW396473B TW087110579A TW87110579A TW396473B TW 396473 B TW396473 B TW 396473B TW 087110579 A TW087110579 A TW 087110579A TW 87110579 A TW87110579 A TW 87110579A TW 396473 B TW396473 B TW 396473B
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TW
Taiwan
Prior art keywords
semiconductor wafer
substrate
item
layer
wafer
Prior art date
Application number
TW087110579A
Other languages
English (en)
Inventor
Teck-Hown Nam
Original Assignee
Hyundai Electronics Ind
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Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW396473B publication Critical patent/TW396473B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01—ELECTRIC ELEMENTS
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（丨） <發明的範圍> 本發明係有關一種球形柵格陣列封震。特別是有 種具有經過改進的球配置構造的微小球形栅格陣列^穿關一 <相關技藝的描述> 隨著積體電路製造工藝的迅速發展，用於保護形 單位晶片上的許多單位元件不受外部環境影響的封拿技 術’也同其他的製造技藝一起得到了發展。在大部份^ 子裝置中’安裝有製成封裝的半導體晶片，人們努力盡旦 減小裝設有這種半導體晶片的印刷電路板的面積，鱼這二 努力相對應，要求實現封裝尺寸的小型化。作為使^裝尺 寸小型化的技術之-，人們提出了晶片尺寸封裝(Chips^e Package :CSP)或晶片規模封裝(Chip Scale:csp)， 遗種封裝的尺寸減小到與晶片尺寸相當的程度。在這種晶 •片規模插件中，球形柵格陣列封裝（Ball Grip Array Package : BGA Package)，不儘因為它的面積小，而且，還 因它的良好的性能及可靠性而引人注目。這種BGA封裝有 塑料球形栅格陣列(plastic Ball Grid A取y 封裝、多 層陶兗球形柵格陣朗裝(Ce腦ie BaU :cbga) 封裝· ’條帶载體自動化引線鍵結（TAB :Tape Automated Bonding)球形栅格陣列封裝及類似球形桃格陣列(廳 ylike)封裝。另外，還有丁的记邙公 的微小球栅 格陣列封裝。 ㈣球形拇格陣列封裝，通過在其表面上形成的導電 ^ °卩電路進行信號傳送。半導體積體度的增加會使 ----------------Q------、訂----- -* - (請先Μ讀紫面之注意事項再填寫本頁) 本紙張尺度賴 經濟部中央標準局員工消費合作社印製 五、發明説明（> ) 所述BGA封裝上的球數量增加。球數口 碰撞，而且會使通過域於山^ 3 )丨灸衣之間的 H使通過球輸出、輸入的數據產生 解決這個問題，必需減小球為了 工藝上的易實現。〃“種解蝴法受到 卜枯Ϊ包括所述Β〇Α封裝在内的所有封裝中，必需 在:σ封裝所占面積的條件下提高積體度。 Μ 2 W是現有晶歧模封裝(Chip Seale Paek_群中且 有表性的微型球形柵格陣列（卜_⑽A ^ 的概略剖面圖。 -^^A) ς“、、第1圖’提供了半導體晶# 2即印模(㈣，它具 :内J面2a和外表面2b ’在内表面2a上形成有個多半導 雪内表面“的上部表面上形成有許多個於與外部 曰 、彳5號的鍵結點(未圖示）。這些鍵結點形成於半導體 2 2的内端部。在第i圖中，半導體晶片2的内表面a 。在所述半導體晶片2的内表面2a上依次層疊者 爭’橡膠4和印刷有電路配線的柔軟的梁式引線薄膜6， :面，同附屬層（Compliant layer :8)—起說明彈性橡膠4和 弋弓丨線薄膜6的配線通過半邊濟晶片2的鍵結點和鍵結 (請先S讀背面之注意事項异填霉本頁} -訂_ _· 連線而在電氣上相互連結，在 上’配置有許多導電性焊鍚珣 之間進行g_的輸出輸入，以 避：梁式引線薄膜6的表面 ’用於在與半導體晶片2 外部電路電氣連接 焊鍚球機形成於 焊 結構蔡形柵格陣列封裝，通過將導電性的 峰寻i 石，号i 裝置的印刷電路板上的配線進行鍚 1=¾接到插座上，而形成電氣信號傳送
本紙張尺度適规格（2H)x‘iT 五 A7 B7 經濟部中央標準局員工消費合作社印製 、發明説明（$ ) 體系。 此外’有上述結構的球形柵格陣列封裝，為了與日益 成為高積體化及小塑化的半導體晶片尺寸相對地增加單位 面積上的焊鍚球數量’需要減小球的直徑，提高梁式引線 鍵結技術。在滿足不了這種要求的情況下，半導體尺寸的 減小受到限制。 <發明之總論〉 因此，本發明的目的在於提供一種球形柵格陣列封裝， 隨著在一定面積内增加安裝在單位晶片上的半導體晶片的 積體度，可以相對地增加於外部電路傳遞信號的球數量。 本發明的另一目的是，提供一種不增加封裝所占面積 卻能提高積體度的球形柵格陣列封裝。 根據本發明的一個方案，本發明係有關一種球形柵格 陣列封裝包括基板和設置在該基板内的半導體晶片之類的 各種元件。該基板具有第一表面和比所述的第一表面高且 形成於所述第一表面周圍的第二表面。半導體晶片配=在 第一表面上，在其上部表面設有用於與外部電路進行信號 傳送的多個襯墊(pad)’設置在各層上的具有相同功能 塾之間相互電氣連接’並至少-叠放一個。球形拇格陣列 封裝包含設在所述基板上，其一端與所述半導體晶片的 面和基板的第二表面上，與半導體晶片的襯墊，以及露^ 在基板的第二表面上的引線電氣連接。 根據另一個方案，本發明有關的球形柵格陣列封I勺 括基板和設在該基板内的兩個疊放的半導體晶片之類的匕 本紙張尺度適用中國國家標準（CNS ) A4規格（X297公釐） I- n n —I-1 n I-1^)^, 11 (諳先閲讀背面之注意事項再填寫本頁} 訂 I- 種元件，基板具有第—矣 表面周圍的第二表 ：第:表：高且：成於第- 配置在所述基板的第體曰曰片包括.f 一半導體晶片， 於與外部魏進行仲 /、上獅表®上設有用 配置在所述第-半個襯墊；第二半導體晶片， 述的第體ί片導體晶片的上部表面上’其尺寸小於所 路出，且在其上部設有多個襯塾。此外的襯塾 袼陣列封裝包含設在爲柘 發月的球形柵 塾在電氣上域通且^在第^晶片的襯 所二: 第二表面上的:一電氣導連體 <附圖的簡單說明如下> 附圖的簡要說明如下： 圖第1圖是現有實施例的球形柵格陣列封穿的概略。， 面圖第2岐本㈣實施_球形柵格.丨㈣的概略剖 示意^八圖至第5B圖是表示第2圖所示封μ製造_ <圖示中元件名稱與符號對照> 22.......基板 22a 基板的第·—表面 本紙張尺度適用中(CNS) （ 21〇χ297公釐- A7 A7 經濟部中夬標準局員工消費合作社印製 五、發明説明（ί) ·--- 22b......基板的第二表面 22c......基板的内側壁的表面 24…黏接劑層 26…第一半導體晶片 28a、28b.第一、第二條帶 30.. ..…載體薄膜 32……·第二半導體晶片 34.·，..··彈性橡膠 36…梁式引線薄膜 38a、38b.第一、第二焊鍚球 4〇.......第二引線 42.. .....連線 44…·.··密封劑 <較佳具體實施例之詳細描述> 下面’參照附圖說明本發明的較佳具體實施例。 如第2圖所示，本發明的球形柵格陣列封裝包括具有 第一表面22a和第二表面22b的基板22。此外^所述^板 22還包括將第一表面22a與第二表面22b的端部連接起來 的内側壁的表面22c。所述基板22的第一表面22a的尺寸 稍大於晶片尺寸，以便將半導體晶片26、32裝入在其上。 基板22的第一表面22a形成在基板22的内表面的中央上， 第二表面22b比第一表面22a的規定高度高，並沿著第— 表面22a的端部配置。第二表面22b具有使基板22的尺寸 不超出半導體晶片26、32的尺寸範圍很多的寬度。 ____ 7 ^ ) ( 210X297/^ ) (請先閲讀背面之注意事項再填寫本頁) 訂 發明説明（4) 表面is晶片26'32包括：第一半導體晶片26 ’其外 導:=，= 挪，以及位於;們之—條帶和第二條帶 第-半導體晶片的L。載在體第 體曰H 在弟一半導體晶片20和第二半導 ^ 32 被設置在其上方二二4::=體晶片26的鍵結點不 人彈性橡膠34,該彈性橡膠具有可 ;:;ί體線薄鱗的第-引線的-端與 在其上端與附著 在基板22上埋設著多根第二弓I的Λρ. ^ L =露出在第二表面―==線： 準 五、 ::===二引線4。的-端，= 在基板22的第二表面^上鍵結。露 二烊“連 A4規格（210x297公釐） 經濟部中央標準局員工消費合作社印製 、發明説明（7 々具有上述結構的球形柵格陣列封裝，通過將導電性的 第^第二焊鎖球38a、38b與形成印刷電路板上的配線進 仃％知、或與插座連接’形成電信號傳送系統。 此外，根據設計規則(Design rule)，所述第一半體晶片 26的鍵結點’可全部與第二焊鎮球娜進行電氣連接，或 =有-部份與第二焊鍚球38b進行電氣連接。在只有一部 =第二焊鎖球38b連接的情況上，其餘的鍵結點與梁式 線薄膜36的第一引線中的，不與第二半導體％的鍵結 ^相連接的剩餘的引線相連接，並與第一焊錄球撕相連 如上所述，通過改變鍵結點的連接方式，本較佳呈 只施例的構造可_於第—半導體晶片26與第二半導^ 片32具有相同功能的(隨機存取記體)或r〇m(唯讀記 ，體）中。此外’本較隹具體實瑜彳的構造也適用於第—半 ^體晶片26與第二半導體心32具有不同功能的情況， J如第導體晶片啤是具有控制功能的微處理器，第 半導體片是具有儲存功能的(隨機存取記憶體）或 ROM(唯讀記憶體)等儲存晶片的情況。 ,下面，參照第3A圖至第5B.圖說明製造第2圖中的球 形柵格陣列封裝的方法。 曰第3A圖表示在基板22的第—表面上裝入第一半導體 晶片26的狀態的平面圖，第3B圖是沿著第3A圖中的 3B’線剖開之斷面圖。 參照第3A圖和第3B圖，可提供這樣的基板22，即， 本紙張尺度適用中 (請先聞讀背面之注意事項再填寫本頁) 、βτ A7 B7 五、發明説明（夕） 經濟部中央標準局負工消費合作社印製 1.1i QI. (請先閲讀背面之注意事項再填寫本頁) 、-» 例如具有正六面體形狀，並具有比其端部側的第二表面 的咼度低的規定高度的第一表面22a ’該高度差可使半導體 晶片被裝入到基板22的中央部。所述基板22係由絕緣材 料製成，最好是用塑料化合物製成。所述基板22側壁的内 表面22c具有規定的傾斜度，如第3C圖的概略放大圖所示， 在該傾斜面中埋設著多根具有導電性能的第二引線 柱，用於與第-半導體晶片26進行信號的輸入 =终 所述第二引線40最好是用金(Au)製成。如第3C圖所示， 基板22的側壁内表面22c形成階梯式的，以便使每3根引 線配置在同一平面上，這樣可以提高引線4〇的積體度，在 所述基板22的第-半導體晶片22a上，黏附著沿其ς部具 有許多襯墊電極(未圖示）的第一半導體晶片26，而且是在 填充有黏接劑24的狀態下黏附的。黏附第一半導體晶片之 後’再實施把所述第二引線40與第一半導體晶片^的概 塾電極電氣連接的:^程。如第3C圖所示，在本較佳且體奋 施例中，由於所述[半導體晶片26與第二引線4〇、保二 相隔規定距耗狀態，因此，採Μ線職方法，用連 42把各第二引線4〇和與其對應的各襯塾電極連接起來、。 但是，上述引線鍵結方法也可改變為其它方法。 上圖，為了在第一半導體晶片26 將：㈣Vi半¥體晶片26的第二半導體晶片32， 將第-條帶28a黏附在所述第一半導體晶片26上 J上:次黏，30和第二條帶咖。在第二條帶: 裝入苐一半導體晶片32，在第二半導體晶片32上裝入彈 經 中 準 局 員 工 消 費 合 作 社 印 製 五 '發明説明（f 性橡膠(elastomers，該彈性橡膠34的面積足以使 圖的梁式引線薄膜36黏接在所述彈性橡膠％和第二半 體晶片32的端部上’然後進行梁式化線薄膜 ^電氣連接。第4A圖所示的平面圖表示上述過程結束的狀 配線工程如後，進行封褒(encapsukti⑽工程，用密封 洌44把露出有配線的斜面區封 質是液態密封樹脂。 封d &時，用於密封的物 接著，如第5A圖及第β -導體晶片26和第二半導 進行形成焊鍚球的工铲十山 進行&號的輸入輸出’ =仃械㈣球的场。露出在襯底22 線40 _部卿祕其上部表面==的弓1 接；梁式引線36的各引線盘m甘球連 球地連接，蝴焊錄 間的信號傳送系統。 體曰曰片26、32之 -在上述較佳具體實施例中，雖崎明了田4 晶片的例子，但也可以通射^兒明了 *放一個半導體 柱_)的積體度的辦法通==的斜度來增加接線 裝，即，裝入在最上部的半導^ 2層以上的晶片構成封 ==片，方法進行二連接與 =線連接’顿’能夠《固定面積製造具有= 此外，所述的球形柵格陣列封裝也可適用於單層晶片 訂 箭 I----- . ]1 本纸張尺度適用 A7 A7 經濟部中夬樣準局員工消費合作社印製 、發明説明（丨p ) =封裝’這種封裝存在著鍵結點數量過多且焊鍚球之間易 ^生碰撞關題。在這種纽τ，半導體晶片的^部份键 =與形成於基板的第二表面上的第二焊鎮球之間形成電 =傳送稱；半導體日日日片的其餘鍵結點與形成於梁式引 =膜的上部的第-烊鎖球之間形成電信號傳送通路。前 未說明的結論與前面說明的實施例—樣，因此，在此不 -Η». S&· 1衷覆〇 、如上所述，本發_球雜格㈣域是將半導體晶 二!多層疊放而成的’因此，能夠以—樣的面積製造具 更的封裝。而且，本發明的封裝，不儘在晶片上 。，而且在基板上部也可形成甩於構 ^點之間的信號傳送的通路的焊鎖球成==== 2減小球的直徑的技述，也可防止焊錫球之間的.衝撞。 不要更高的引線鍵合技術，可觀有技術水平 、=合技術’所以，可防止製造f增加和良率降 ::製成的封裝是降溫型鄉— 這裏’雖然本發明的較佳具體實施例作了說_ ^此項技術之人士可對它進行修改或改變其形^因， =解為只要是屬於本發明的精神和範圍的所有的修’ 、文开^均包括在本發·明的專利申請範圍内。 和 12 本紙張尺舰财國國家標準（c^g^_297公釐7 C请先聞讀背面之注意事項鼻填寫本頁)

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  1. 〇 71 10579 、申請專利範園 2. 經濟部中央標準局員工消費合作社印製 3. 4. 一種球形柵袼陣列封裝，包括： -表面周_第二表表面高且形成於所述! i:上個放著’並配置在所述的第- 傳送的多個概塾二面進行信* 的襯墊之間相互魏連^置在各層上的具有相同功負 多根引線’設在所述基板上 片的一部份襯墊連接，$ :、鳊/、所述+導體^ 多個導電性_1露出在所述第二表面上; 形成於所述半導體晶片中的幻 上，與戶ki導體表ί和所述基板的第二知 的第-心日日片的襯塾’以及露出在所述基右 的弟一表面的引線電氣連接。 圍第1項所述之球形柵格陣列封裝’j 括'於所述半導體晶片的襯墊與連接在所制 所述附屬層包括：〗_(_piiant)層， 的圖樣層把所述半導體晶片的襯墊與所述半導 體晶片的襯墊電氣連接； 緩衝層’用於緩衝對所述丰導體晶片的外部衝撞。 t申請專利範圍第2項所述之球__韻裝，其 中所述緩衝層是彈性橡膠(elastomer)。 ^申請專利範圍第i項所述之球形柵格陣列封裝，其 中與所述躲連接—結點，通過連線被鍵合。 ⑽)娜(21〇x29Tiiy (請先閲讀背面之注意事項存填寫本貧) 申請專利範圍 5. 7. 8. ^申請專利_第4項所述之球频 中具有所述連線和通過所述連線被鍵 丨封裝，其 被硬化的液態樹脂封裝起來。 伤的部份， ^申請專利範圍第！項所述之球形柵袼 :述半導體晶片的最下方的半導體晶 J ’其 第-表面之間填有黏接劑付^體日日片與所述基板的 ^申請專利_第i 狀麵姆 中所述封裝還包含按第—黏接層，具 ，裝〜、 之間接糊序於所述半導體晶片 一種球形栅格陣列封裝，其中包括. 表面高，於所述第 ^半導體晶片’配置在所述基板的第—表面上，在 個=的表面上設有於與外部電路進行信號傳遞的多 =半導體晶片，配置在所述第一半導體晶片的上部 2上’其尺寸小於所述第一半導體晶片，便使所述 塾了+導體晶片的襯墊露出’且在其上部設有多個襯 ^艮引m在所述基板上，與所述第—半導體晶 片的襯墊電氣連接，且露出在所述的第二表面上· 多個導·焊鍚球’軸於所料二铸體晶片的表 本紙張尺度適用中國蘇^( eNS $ Β9β47Β Α8 B8 C8 D8 申請專利範圍 面和所述基板的第二表面上，並與所述第二 片的襯墊，以及露出在所述基板的第- 曰曰 電氣連接。 ㈣上的引線 9. ::請專利範圍第8項所述之球形栅格陣列封裝，1 中還包括介於所述半導體晶片的襯塾 導體晶片的襯塾上的焊鍚球之間的^接在所述半 所述所屬層包括：緩衝層，⑽ 衝撞;導電性的圖樣層，把所述半ί = Γ 的襯塾與所.述半導體“ _塾 +導體曰曰片 1〇·:申料利_9項所狀球形=陣 中所述緩衝層是彈性橡膠(elast〇mer)。車列封裝’其 U，如申請專利_第8項所述之球 中與所述_連接的鍵結點，^柵^陣列封裝’其 12·如申料利翻第8項所述之_=袼^鍵結。 中具有所述連線和通過所述連 。，封農，其 硬化的液態樹脂封裝起來。 订鍵結的部分，被 13.如申請專利範圍第8項 中所述半導體晶片中的最下方陣列封裝，其 述基板的第一表面上，在所述半導，晶片|占附在所 一表面之間填有黏接劑。 —/、所述基板的第 丨4.如申請專利範圍第8項所述之* 令所述封農還包含按第一黏接層，：袼陣列封裝，其 載體薄膜，以及第二黏接層的、有導電性圖樣的 片之間的膜。 、W於所逃半導體晶
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CN1206226A (zh) 1999-01-27
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JP3611455B2 (ja) 2005-01-19
KR100255476B1 (ko) 2000-05-01

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