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TW344170B - High frequency fully digital phase locked loop - Google Patents

High frequency fully digital phase locked loop

Info

Publication number
TW344170B
TW344170B TW086105772A TW86105772A TW344170B TW 344170 B TW344170 B TW 344170B TW 086105772 A TW086105772 A TW 086105772A TW 86105772 A TW86105772 A TW 86105772A TW 344170 B TW344170 B TW 344170B
Authority
TW
Taiwan
Prior art keywords
counter
count
phase
high frequency
locked loop
Prior art date
Application number
TW086105772A
Other languages
Chinese (zh)
Inventor
Bor-Min Wang
Shuh-Fa Yang
Original Assignee
Ind Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to TW086105772A priority Critical patent/TW344170B/en
Application granted granted Critical
Publication of TW344170B publication Critical patent/TW344170B/en

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Abstract

A high frequency fully digital phase locked loop for phase locking local signals from an input signal, which comprises: (a) at least one digital control oscillator for receiving the local signals and generating an output signal; (b) at least one K-counter providing a first control signal to the digital control oscillator; (c) at least one phase detector for receiving and comparing an output signal with an input signal, and providing a second control signal to the K-counter from the phase difference between the output signal and the input signal; and (d) in which the digital control oscillator comprises: (1) at least one delay line including L levels for generating L clock pulses in which L is an integer number and each delay gate has a delay phase φ; (2) at least one programmable upper count-, lower count-, N-counter, in which L is an integer; (3) at least one multiplexer for selecting one of the L clock pulses from the count of the programmable upper count-, lower count-, N-counter; and (4) at least one adaptive compensation circuit determining an N value according to the following conditions: (formula) π<D(t)<2π and D(t)~2π, in which t represents a specific time.
TW086105772A 1997-05-01 1997-05-01 High frequency fully digital phase locked loop TW344170B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086105772A TW344170B (en) 1997-05-01 1997-05-01 High frequency fully digital phase locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086105772A TW344170B (en) 1997-05-01 1997-05-01 High frequency fully digital phase locked loop

Publications (1)

Publication Number Publication Date
TW344170B true TW344170B (en) 1998-11-01

Family

ID=58263723

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086105772A TW344170B (en) 1997-05-01 1997-05-01 High frequency fully digital phase locked loop

Country Status (1)

Country Link
TW (1) TW344170B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106330181A (en) * 2015-07-02 2017-01-11 无锡华润上华半导体有限公司 Delay locked loop detection method and system
TWI726390B (en) * 2018-09-28 2021-05-01 美商高通公司 Apparatus and method for an all-digital phase lock loop

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106330181A (en) * 2015-07-02 2017-01-11 无锡华润上华半导体有限公司 Delay locked loop detection method and system
CN106330181B (en) * 2015-07-02 2019-05-21 无锡华润上华科技有限公司 The detection method and system of delay lock loop
TWI726390B (en) * 2018-09-28 2021-05-01 美商高通公司 Apparatus and method for an all-digital phase lock loop

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