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TW344133B - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
TW344133B
TW344133B TW084106134A TW84106134A TW344133B TW 344133 B TW344133 B TW 344133B TW 084106134 A TW084106134 A TW 084106134A TW 84106134 A TW84106134 A TW 84106134A TW 344133 B TW344133 B TW 344133B
Authority
TW
Taiwan
Prior art keywords
circuit
output
data
memory portion
operation circuit
Prior art date
Application number
TW084106134A
Other languages
Chinese (zh)
Inventor
Miki Matsumoto
Kanji Oishi
Masahiro Katayama
Kazufumi Watanabe
Original Assignee
Hitachi Ltd
Hitachi Cho Lsi Eng Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Cho Lsi Eng Co Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW344133B publication Critical patent/TW344133B/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A semiconductor memory characterized in comprising: a memory portion having a plurality of memory cells furnished at the points of intersection between a plurality of word lines and a plurality of data lines; an operation circuit having a plurality of operation modes and operating in accordance with a designated operation mode; a first external terminal; a first output circuit furnished interposingly between the output terminal of the operation circuit and the first external terminal, the first output circuit feeding the output data of the operation circuit to the first external terminal; a second output circuit furnished interposingly between the output terminal of the operation circuit and the memory portion, the second output circuit feeding the output data of the operation circuit as write data to the memory portion; a first input circuit for providing a first input terminal of the operation circuit with first data supplied from outside the semiconductor memory; and a second input circuit furnished interposingly between a second input terminal of the operation circuit and the memory portion, the second input circuit providing the second input terminal with second data retrieved from the memory portion; in which the operation circuit receives and operates on the first and the second data in accordance with the designated operation mode; and in which the output data of the operation circuit is given to the first external terminal in the operation cycle in which the same output data is written to the memory portion.
TW084106134A 1994-07-27 1995-06-15 Semiconductor memory TW344133B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6194893A JPH0845269A (en) 1994-07-27 1994-07-27 Semiconductor memory device

Publications (1)

Publication Number Publication Date
TW344133B true TW344133B (en) 1998-11-01

Family

ID=16332087

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084106134A TW344133B (en) 1994-07-27 1995-06-15 Semiconductor memory

Country Status (5)

Country Link
US (1) US5598372A (en)
JP (1) JPH0845269A (en)
KR (1) KR960006017A (en)
CN (1) CN1116763A (en)
TW (1) TW344133B (en)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748551A (en) * 1995-12-29 1998-05-05 Micron Technology, Inc. Memory device with multiple internal banks and staggered command execution
JPH10247384A (en) * 1997-03-03 1998-09-14 Mitsubishi Electric Corp Synchronizing type semiconductor memory
JP4039532B2 (en) 1997-10-02 2008-01-30 株式会社ルネサステクノロジ Semiconductor integrated circuit device
ITMI981564A1 (en) * 1998-07-09 2000-01-09 St Microelectronics Srl NON-VOLATILE MEMORY ABLE TO RUN A PROGRAM INDEPENDENTLY
KR100307626B1 (en) * 1998-08-31 2001-11-30 윤종용 Merged memory logic integrated circuit device having DRAM and buffer memory
GB2343529B (en) * 1998-11-07 2003-06-11 Ibm Filtering incoming e-mail
US6601130B1 (en) * 1998-11-24 2003-07-29 Koninklijke Philips Electronics N.V. Memory interface unit with programmable strobes to select different memory devices
JP2000187983A (en) * 1998-12-22 2000-07-04 Nec Corp Memory device
US6259646B1 (en) 2000-01-28 2001-07-10 Micron Technology, Inc. Fast accessing of a memory device
JP2001312895A (en) * 2000-04-26 2001-11-09 Nec Corp Semiconductor storage device
JP2002175689A (en) 2000-09-29 2002-06-21 Mitsubishi Electric Corp Semiconductor integrated circuit device
US6798711B2 (en) * 2002-03-19 2004-09-28 Micron Technology, Inc. Memory with address management
US7019998B2 (en) * 2003-09-09 2006-03-28 Silicon Storage Technology, Inc. Unified multilevel cell memory
JP4846306B2 (en) * 2005-09-09 2011-12-28 富士通セミコンダクター株式会社 Semiconductor memory device, semiconductor integrated circuit system using the same, and method for controlling semiconductor memory device
JP4310439B2 (en) * 2006-01-30 2009-08-12 国立大学法人京都大学 Exclusive-OR type functional memory
JP5351145B2 (en) * 2008-04-22 2013-11-27 パナソニック株式会社 Memory control device, memory system, semiconductor integrated circuit, and memory control method
KR100967100B1 (en) * 2008-09-08 2010-07-01 주식회사 하이닉스반도체 Semiconductor memory device and word line driving method thereof
US8964496B2 (en) 2013-07-26 2015-02-24 Micron Technology, Inc. Apparatuses and methods for performing compare operations using sensing circuitry
US9613714B1 (en) * 2016-01-19 2017-04-04 Ememory Technology Inc. One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method
US10559351B2 (en) 2017-02-20 2020-02-11 Texas Instruments Incorporated Methods and apparatus for reduced area control register circuit
JP6761104B2 (en) * 2017-03-06 2020-09-23 ゼンテルジャパン株式会社 Semiconductor storage system
US10884656B2 (en) 2017-06-16 2021-01-05 Microsoft Technology Licensing, Llc Performing background functions using logic integrated with a memory
US10866900B2 (en) 2017-10-17 2020-12-15 Samsung Electronics Co., Ltd. ISA extension for high-bandwidth memory
CN109979505B (en) * 2017-12-28 2020-10-27 展讯通信（上海）有限公司 SRAM write circuit
DE102018207020A1 (en) * 2018-05-07 2019-11-07 Robert Bosch Gmbh Static Random Access Memory Block and Receive Sensor
TWI863635B (en) * 2023-10-19 2024-11-21 新唐科技股份有限公司 Microcontroller circuit, control method and operating system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH079751B2 (en) * 1985-06-17 1995-02-01 株式会社日立製作所 Semiconductor memory device
US4903236A (en) * 1987-07-15 1990-02-20 Mitsubishi Denki Kabushiki Kaisha Nonvolatile semiconductor memory device and a writing method therefor

Also Published As

Publication number Publication date
CN1116763A (en) 1996-02-14
JPH0845269A (en) 1996-02-16
KR960006017A (en) 1996-02-23
US5598372A (en) 1997-01-28

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