TW202408034A - Package structure - Google Patents

Abstract

A package structure includes a leadframe, at least two dies, at least one spacer and a plastic package material. The leadframe includes a die pad. The dies are disposed on the die pad of the leadframe. The spacer is disposed between at least one of the dies and the die pad. The plastic package material is disposed on the leadframe, and covers the dies. A first minimum edge distance is located between one of a plurality of edges of the spacer and one of a plurality of edges of the die pad, a second minimum edge distance is located between one of a plurality of edges of the dies and one of the edges of the die pad, and the first minimum edge distance is larger than the second minimum edge distance. Therefore, a risk of the delamination of the plastic package material during the package structure stressed can be reduced, wherein the flexibility of design of the package structure can be increased via the spacer, and the spacer can be configured to protect the dies to prevent the damage.

Description

Package structure

The present disclosure relates to a packaging structure, and in particular, a packaging structure that can increase a sufficient contact area between a plastic packaging material and a chip holder.

In today's semiconductor packaging industry, the size of the packaging structure is gradually reduced in response to the development of technology. The size of the packaging structure can be reduced by reducing the area of the chip seat of the lead frame and reducing the area of the chip. However, when the area of the chip holder is reduced, the edge of the chip is too close to the edge of the wafer holder, that is, the distance between the edge of the wafer holder and the edge of the chip is insufficient, resulting in insufficient contact area between the plastic packaging material and the wafer holder. Accordingly, when the packaging structure is stressed, the plastic packaging material is prone to serious delamination defects at the edge of the chip holder.

Therefore, developing a packaging structure that can reduce the risk of delamination of plastic packaging materials under stress has become an important and urgent problem in the industry.

The present disclosure provides a packaging structure in which the plastic packaging material and the chip holder can have sufficient contact area through the spacer layer, thereby reducing the risk of delamination of the plastic packaging material when subjected to stress.

According to an embodiment of the present disclosure, a packaging structure is provided, which includes a lead frame, at least two chips, at least one spacer layer and a plastic packaging material. The leadframe includes a chip holder. The chip is placed on the chip seat of the lead frame. A spacer layer is provided between at least one of the wafers and the wafer holder. The plastic packaging material is placed on the lead frame and covers the chip. There is a first minimum margin between one of the edges of the spacer layer and one of the edges of the wafer holder, and there is a first minimum edge distance between one of the edges of the wafer and one of the edges of the wafer holder. The second minimum margin, and the first minimum margin is greater than the second minimum margin.

According to the packaging structure of the embodiment described in the previous paragraph, the first minimum margin may be at least 40 microns.

According to the packaging structure of the embodiment described in the previous paragraph, the spacer layer can be disposed between the chip and the chip base at the same time.

According to the packaging structure of the embodiment described in the previous paragraph, the number of spacer layers may be at least two, and each spacer layer is disposed between each chip and the chip holder.

According to the packaging structure of the embodiment described in the previous paragraph, the thickness of one of the spacer layers and the thickness of the other spacer layer may be different.

According to the packaging structure of the embodiment described in the previous paragraph, the thickness of the spacer layer may be greater than or equal to 40 microns and less than or equal to 500 microns.

According to the packaging structure of the embodiment described in the previous paragraph, the material of the spacer layer may be silicon.

According to the packaging structure of the embodiment described in the previous paragraph, the area of one of the wafers may be different from the area of the other wafer.

According to the packaging structure of the embodiment described in the previous paragraph, the area of the spacer layer may be smaller than the total area of the chip.

According to an embodiment of the present disclosure, a packaging structure is provided, which includes a lead frame, a chip, a spacer layer and a plastic packaging material. The leadframe includes a chip holder. The chip is placed on the chip seat of the lead frame. The spacer layer is disposed between the wafer and the wafer holder. The plastic packaging material is placed on the lead frame and covers the chip. The area of the spacer layer is smaller than the area of the wafer.

According to the packaging structure of the embodiment described in the previous paragraph, the thickness of the spacer layer may be greater than or equal to 40 microns and less than or equal to 500 microns.

According to the packaging structure of the embodiment described in the previous paragraph, there is a first minimum margin between one of the edges of the spacer layer and one of the edges of the chip holder, and the first minimum margin can be at least 40 Micron.

According to the packaging structure of the embodiment described in the previous paragraph, the material of the spacer layer may be silicon.

Please refer to FIGS. 1 and 2 , wherein FIG. 1 is a schematic plan view of the packaging structure 100 according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the packaging structure 100 of the first embodiment in FIG. 1 . As can be seen from Figures 1 and 2, the packaging structure 100 includes a lead frame (not shown), two chips 121, 122, a spacer layer 130 and a plastic packaging material 140, wherein the plastic packaging material 140 is disposed on the lead frame , and cover the wafers 121 and 122.

Furthermore, the lead frame includes a chip seat 111 and a plurality of pins 112, and the chips 121 and 122 respectively include a plurality of pads 151, wherein the chips 121 and 122 are arranged on the chip seat 111, and a plurality of wires 152 connect the pins 112 and the pads. 151, and the spacer layer 130 is simultaneously disposed between the wafers 121, 122 and the wafer holder 111.

There is a first minimum edge distance L1 between one of the edges of the spacer layer 130 and one of the edges of the wafer holder 111. One of the edges of the wafers 121, 122 is between one of the edges of the wafer holder 111 There is a second minimum margin L2 between one of them, wherein the first minimum margin L1 is greater than the second minimum margin L2, and the first minimum margin L1 may be at least 40 microns. In the first embodiment, the second minimum margin L2 is located between one of the edges of the wafer 121 and one of the edges of the wafer holder 111 . Thereby, when the chips 121 and 122 are juxtaposed on the chip pedestal 111, the plastic packaging material 140 and the wafer pedestal 111 still have sufficient contact area to reduce the risk of delamination of the plastic packaging material 140 when the packaging structure 100 is stressed. The contact range increased by the spacer layer 130 is shown as the thick chain line in Figure 2. Furthermore, the area of the spacer layer 130 may be smaller than the total area of the wafers 121 and 122 , and the area of the wafer 121 and the area of the wafer 122 may be different.

Furthermore, the spacer layer 130 can increase the flexibility of the placement of the chips 121 and 122 , that is, the placement of the chips 121 and 122 is not limited to the area size of the chip base 111 , thereby increasing the design flexibility of the packaging structure 100 , especially when the area is reduced. A situation where a larger chip is placed in a smaller package structure. Furthermore, the spacer layer 130 has the effect of protecting the chips 121 and 122, thereby preventing the chips 121 and 122 from being damaged when external stress impacts the packaging structure 100.

In detail, the thickness T of the spacer layer 130 may be greater than or equal to 40 microns, and may be less than or equal to 500 microns. When the thickness T of the spacer layer 130 is less than the above numerical range, the spacer layer 130 cannot achieve the effect of increasing the sufficient contact area between the plastic packaging material 140 and the chip holder 111; when the thickness T of the spacer layer 130 is greater than the above numerical range, the packaging structure 100 has the risk of exceeding specification thickness, or having the wires 152 too close to the plastic encapsulation material 140 .

The material of the spacer layer 130 may be silicon. Specifically, the spacer layer 130 can be a blank wafer made of silicon, but is not limited thereto.

Furthermore, the packaging structure 100 of the first embodiment is a QFN packaging type, but the packaging structure of this disclosure can be applied not only to QFN, but also to TSOP, SO, and QFP packaging types, but this is not the case. is limited.

Please refer to Figures 3 and 4. Figure 3 is a schematic plan view of the packaging structure 200 according to the second embodiment of the present invention, and Figure 4 is a cross-sectional view of the packaging structure 200 of the second embodiment of Figure 3. As can be seen from Figures 3 and 4, the packaging structure 200 includes a lead frame (not shown), two chips 221, 222, two spacer layers 231, 232 and a plastic packaging material 240, wherein the plastic packaging material 240 is disposed on the wire on the rack and cover the wafers 221 and 222.

Furthermore, the lead frame includes a chip seat 211 and a plurality of pins 212, and the chips 221 and 222 respectively include a plurality of pads 251, wherein the chips 221 and 222 are arranged on the chip seat 211, and a plurality of wires 252 connect the pins 212 and the pads. 251, the spacer layer 231 is provided between the wafer 221 and the wafer seat 211, and the spacer layer 232 is provided between the wafer 222 and the wafer seat 211.

There is a first minimum margin L1 between one of the edges of the spacer layers 231 and 232 and one of the edges of the wafer holder 211 . There is a second minimum margin L2 between one of the edges, wherein the first minimum margin L1 is greater than the second minimum margin L2. In the second embodiment, the first minimum margin L1 is located between one of the edges of the spacer layer 231 and one of the edges of the wafer holder 211 , and the second minimum margin L2 is located between one of the edges of the wafer 221 and one of the edges of the wafer holder 211 . Thereby, when the chips 221 and 222 are juxtaposed on the chip seat 211, the plastic packaging material 240 and the chip seat 211 still have sufficient contact area to reduce the risk of delamination of the plastic packaging material 240 when the packaging structure 200 is stressed. The increased contact range due to layers 231 and 232 is as shown in the thick chain line in Figure 4.

In addition, the structure and arrangement relationship of the remaining components of the second embodiment are the same as those of the first embodiment, and will not be described again here.

Please refer to FIGS. 5 and 6 , wherein FIG. 5 shows a schematic plan view of the packaging structure 300 according to the third embodiment of the present invention, and FIG. 6 shows a cross-sectional view of the packaging structure 300 of the third embodiment in FIG. 5 . As can be seen from Figures 5 and 6, the packaging structure 300 includes a lead frame (not shown), two chips 321, 322, two spacer layers 331, 332 and a plastic packaging material 340, where the plastic packaging material 340 is disposed on the wire on the rack and cover the wafers 321 and 322.

Furthermore, the lead frame includes a chip seat 311 and a plurality of pins 312, and the chips 321 and 322 respectively include a plurality of pads 351, wherein the chips 321 and 322 are arranged on the chip seat 311, and a plurality of wires 352 connect the pins 312 and the pads. 351, the spacer layer 331 is provided between the wafer 321 and the wafer seat 311, and the spacer layer 332 is provided between the wafer 322 and the wafer seat 311.

There is a first minimum margin L1 between one of the edges of the spacer layers 331 and 332 and one of the edges of the wafer holder 311 . There is a second minimum margin L2 between one of the edges, wherein the first minimum margin L1 is greater than the second minimum margin L2. In the third embodiment, the first minimum margin L1 is located between one of the edges of the spacer layer 331 and one of the edges of the wafer holder 311 , and the second minimum margin L2 is located between one of the edges of the wafer 321 and one of the edges of the wafer holder 311 . Thereby, when the chips 321 and 322 are arranged side by side on the chip holder 311, the plastic packaging material 340 and the chip holder 311 still have sufficient contact area to reduce the risk of delamination of the plastic packaging material 340 when the packaging structure 300 is stressed. The contact range increased by layers 331 and 332 is as shown in the thick chain line in Figure 6.

Furthermore, the thickness T1 of the spacer layer 331 is different from the thickness T2 of the spacer layer 332, wherein the thickness T1 is smaller than the thickness T2. When the total area of the wafers 321 and 332 is similar to the area of the wafer holder 311, the vertical distance between the wafers 321 and 322 can be further increased through the spacer layers 331 and 332 of different thicknesses to prevent the wafers 321 and 322 from being too close. This leads to the problem of insufficient distance between wires 352. Specifically, by increasing the vertical distance between the chips 321 and 322, the horizontal distance between the chips 321 and 322 can be shortened to maintain the connection strength of the wires 352.

In addition, the structures and arrangements of the remaining components of the third embodiment are the same as those of the first embodiment, and will not be described again here.

Please refer to FIGS. 7 and 8 . FIG. 7 is a schematic plan view of the packaging structure 400 according to the fourth embodiment of the present invention, and FIG. 8 is a cross-sectional view of the packaging structure 400 of the fourth embodiment in FIG. 7 . As can be seen from Figures 7 and 8, the packaging structure 400 includes a lead frame (not shown), two chips 421, 422, a spacer layer 430 and a plastic packaging material 440, wherein the plastic packaging material 440 is disposed on the lead frame , and cover the wafers 421 and 422.

Furthermore, the lead frame includes a chip seat 411 and a plurality of pins 412, and the chips 421 and 422 respectively include a plurality of pads 451, wherein the chips 421 and 422 are arranged on the chip seat 411, and a plurality of wires 452 connect the pins 412 and the pads. 451, and the spacer layer 430 is disposed between the wafer 422 and the wafer holder 411.

There is a first minimum edge distance L1 between one of the edges of the spacer layer 430 and one of the edges of the wafer holder 411, and one of the edges of the wafers 421, 422 is between There is a second minimum margin L2 between one of them, wherein the first minimum margin L1 is greater than the second minimum margin L2. In the fourth embodiment, the second minimum margin L2 is located between one of the edges of the wafer 422 and one of the edges of the wafer holder 411 . By disposing the spacer layer 430 between the chip 422 and the chip seat 411 and not disposing the spacer layer 430 between the chip 421 and the chip seat 411, the vertical distance between the chips 421 and 422 is increased, thereby maintaining the connection strength of the wire 452. Thereby, when the chips 421 and 422 are juxtaposed on the chip seat 411, the plastic packaging material 440 and the chip seat 411 still have sufficient contact area to reduce the risk of delamination of the plastic packaging material 440 when the packaging structure 400 is stressed. The increased contact range of layer 430 is as shown in the thick chain line in Figure 8.

In addition, the structures and arrangements of the remaining components of the fourth embodiment are the same as those of the first embodiment, and will not be described again here.

Please refer to Figures 9 and 10. Figure 9 illustrates a schematic plan view of the packaging structure 500 according to the fifth embodiment of the present invention, and Figure 10 illustrates a cross-sectional view of the packaging structure 500 of the fifth embodiment of Figure 9. As can be seen from Figures 9 and 10, the packaging structure 500 includes a lead frame (not shown), a chip 520, a spacer layer 530 and a plastic packaging material 540, where the plastic packaging material 540 is disposed on the lead frame, and Cover wafer 520.

Further, the lead frame includes a chip seat 511 and a plurality of pins 512, and the chip 520 includes a plurality of pads 551, wherein the chip 520 is disposed on the chip seat 511, a plurality of wires 552 connect the pins 512 and the pads 551, and the spacing layer 530 is disposed between the chip 520 and the chip holder 511 .

The area of the spacer layer 530 is smaller than the area of the wafer 520 . Furthermore, there is a first minimum edge distance L1' between one of the edges of the spacer layer 530 and one of the edges of the wafer holder 511, and one of the edges of the wafer 520 is separated from the wafer holder 511. There is a second minimum margin L2' between one of the edges, the first minimum margin L1' is greater than the second minimum margin L2', and the first minimum margin L1' may be at least 40 microns.

Please refer to Figure 11, which is an ultrasonic scanning analysis (SAT) image of the packaging structure 500 in the fifth embodiment of Figure 9. Specifically, when the area of the chip 520 is similar to the area of the chip seat 511, the contact area between the plastic packaging material 540 and the chip seat 511 can be increased through the spacer layer 530, that is, the plastic packaging material 540 and the chip seat 511 have sufficient contact area. It can reduce the risk of delamination of the plastic packaging material 540 under stress. As shown in Figure 11, there is almost no delamination after ultrasonic scanning analysis, and the delamination part D is scattered on one side of the chip holder 511. . Furthermore, the contact range increased by the spacer layer 530 is as shown by the thick chain line in Figure 10 .

Furthermore, the spacer layer 530 can increase the flexibility of the placement of the chip 520 , that is, the placement of the chip 520 is not limited to the area size of the chip seat 511 , thereby increasing the design flexibility of the packaging structure 500 , especially when placing a larger chip. When installed in a smaller package structure. Furthermore, the spacer layer 530 has the effect of protecting the chip 520, thereby preventing the chip 520 from being damaged when external stress impacts the packaging structure 500.

In detail, the thickness T of the spacer layer 530 may be greater than or equal to 40 microns, and may be less than or equal to 500 microns. When the thickness T of the spacer layer 530 is less than the above numerical range, the spacer layer 530 cannot achieve the effect of increasing the sufficient contact area between the plastic packaging material 540 and the chip holder 511; when the thickness T of the spacer layer 530 is greater than the above numerical range, the packaging structure 500 has the problem of exceeding the specification thickness, or the risk that the wire 552 is too close to the plastic encapsulation material 540.

The material of the spacer layer 530 may be silicon. Specifically, the spacer layer 530 can be a blank wafer made of silicon, but is not limited thereto.

It must be noted that Figures 1, 3, 5, 7, 9 and 11 are omitted for the convenience of expressing the arrangement relationship of other components (such as lead frames, chips and spacers, etc.) Labeling of plastic packaging materials.

In summary, regardless of the packaging type of single-chip packaging or multi-chip packaging, the spacer layer can be used to ensure that the plastic packaging material and the chip holder have sufficient contact area, thereby reducing the delamination of the plastic packaging material when the packaging structure is stressed. Risks, and applying spacers to single-chip packaging and multi-chip packaging can increase the flexibility of chip placement. That is, the chip placement is not limited to the area size of the chip holder, thereby increasing the design flexibility of the packaging structure. Furthermore, the spacer layer has the effect of protecting the chip, thereby preventing the chip from being damaged when external stress hits the packaging structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100,200,300,400,500:Package structure 111,211,311,411,511: Chip holder 112,212,312,412,512: pin 121,122,221,222,321,322,421,422,520: Chip 130,231,232,331,332,430,530: Spacer layer 140,240,340,440,540: Plastic packaging materials 151,251,351,451,551: Pad 152,252,352,452,552: Wire D: layered part L1,L1': first minimum margin L2,L2': second minimum margin T, T1, T2: Thickness

Figure 1 is a schematic plan view of a packaging structure according to the first embodiment of the present invention; Figure 2 shows a cross-sectional view of the packaging structure in the first embodiment of Figure 1; Figure 3 is a schematic plan view of a packaging structure according to a second embodiment of the present invention; Figure 4 shows a cross-sectional view of the packaging structure in the second embodiment of Figure 3; Figure 5 is a schematic plan view of a packaging structure according to a third embodiment of the present invention; Figure 6 shows a cross-sectional view of the packaging structure in the third embodiment of Figure 5; Figure 7 is a schematic plan view of a packaging structure according to a fourth embodiment of the present invention; Figure 8 shows a cross-sectional view of the packaging structure in the fourth embodiment of Figure 7; Figure 9 is a schematic plan view of a packaging structure according to a fifth embodiment of the present invention; Figure 10 shows a cross-sectional view of the packaging structure in the fifth embodiment of Figure 9; and FIG. 11 shows an ultrasonic scanning analysis image of the packaging structure in the fifth embodiment of FIG. 9 .

100:Package structure

111:Chip holder

112: pin

121,122: Chip

130: Spacer layer

140:Plastic packaging materials

152:Wire

L1: first minimum margin

L2: second minimum margin

T:Thickness

Claims (13)

An encapsulated structure containing: One lead frame, including: a chip holder; At least two chips are arranged on the chip holder of the lead frame; At least one spacer layer is disposed between at least one of the at least two wafers and the wafer holder; and A plastic packaging material is provided on the lead frame and covers the at least two chips; Wherein, there is a first minimum margin between one of the edges of the at least one spacer layer and one of the edges of the wafer holder, and one of the edges of the at least two wafers and the wafer holder There is a second minimum margin between the edges, and the first minimum margin is greater than the second minimum margin. The packaging structure of claim 1, wherein the first minimum margin is at least 40 microns. The packaging structure of claim 1, wherein the at least one spacer layer is simultaneously disposed between the at least two wafers and the wafer holder. The packaging structure of claim 1, wherein the number of the at least one spacer layer is at least two, and each spacer layer is disposed between each of the wafers and the chip holder. The packaging structure of claim 4, wherein a thickness of one of the at least two spacer layers is different from a thickness of the other of the at least two spacer layers. The packaging structure of claim 1, wherein the thickness of the at least one spacer layer is greater than or equal to 40 microns and less than or equal to 500 microns. The packaging structure of claim 1, wherein the material of the at least one spacer layer is silicon. The packaging structure of claim 1, wherein the area of the one of the at least two chips is different from the area of the other of the at least two chips. The packaging structure of claim 1, wherein the area of the at least one spacer layer is smaller than the total area of the at least two wafers. An encapsulated structure containing: One lead frame, including: a chip holder; A chip is arranged on the chip holder of the lead frame; a spacer layer disposed between the wafer and the wafer holder; and A plastic packaging material is provided on the lead frame and covers the chip; Wherein, the area of the spacer layer is smaller than the area of the wafer. The packaging structure of claim 10, wherein the thickness of the spacer layer is greater than or equal to 40 microns and less than or equal to 500 microns. The packaging structure of claim 10, wherein there is a first minimum margin between one of the edges of the spacer layer and one of the edges of the chip holder, and the first minimum margin is At least 40 microns. The packaging structure of claim 10, wherein the material of the spacer layer is silicon.

Images