TW202341107A - Display driving circuit applied to cholesteric liquid crystal display apparatus - Google Patents

Abstract

A display driving circuit applied to a cholesteric liquid crystal display apparatus including three positive buffer groups, three negative buffer groups and a level shifter and an output switch is disclosed. The three positive buffer groups receive a first reference voltage to a third reference voltage and output a first positive driving voltage to a third positive driving voltage respectively. The three negative buffer groups receive a fourth reference voltage to a sixth reference voltage and output a first negative driving voltage to a third negative driving voltage respectively. The level shifter and the output switch are coupled to the three positive buffer groups and the three negative buffer groups respectively for receiving the first positive driving voltage to the third positive driving voltage and the first negative driving voltage to the third negative driving voltage and generating an output signal accordingly.

Description

Display driving circuit applied to cholesteric liquid crystal display device

The present invention relates to display devices, and in particular to a display driving circuit applied to a cholesteric liquid crystal display (ChLCD).

The current cholesterol liquid crystal full-color display system uses a three-layer stack of red (R)/green (G)/blue (B) pixels. Its advantages include: relatively mature technology development, single pixel color rendering The blocks are larger and the colors are more saturated.

However, in the current cholesteric liquid crystal full-color display system, a considerable number of active and passive components need to be installed on the printed circuit board (PCB) as the driving voltage source to provide the driving voltage to the display driving circuit. In addition, The three-layer stacking method of red (R)/green (G)/blue (B) pixels also greatly increases the cost.

For example, as shown in Figure 1, for a single-color (such as red) pixel panel, at least three positive buffer groups PBF and three negative buffer groups NBF need to be provided on the printed circuit board (PCB) to generate The first positive driving voltage VP1 ~ the third positive driving voltage VP3 and the first negative driving voltage VN1 ~ the third negative driving voltage VN3 are supplied to the display driving circuit, and as shown in Figure 2A and Figure 2B, each positive buffer group PBF/ The negative buffer group NBF needs to include 2 feedback resistors R1~R2 and 1 buffer BF. Therefore, a single-color (such as red) pixel panel needs to include 12 feedback resistors and 6 buffers. In other words, a three-color (i.e. red, green and blue) pixel panel needs to include a total of 36 feedback resistors and 18 buffers, which is a considerable number. In addition, the connection lines and pull lines of the positive buffer group PBF and negative buffer group NBF on the printed circuit board (PCB) also need to consider their own current resistance and resistance, which will also increase the cost of the entire system.

To sum up, the above problems encountered by previous technologies still need to be further solved.

Therefore, the present invention proposes a display driving circuit applied to a cholesteric liquid crystal display device, thereby effectively solving the above-mentioned problems encountered in the prior art.

A preferred embodiment according to the present invention is a display driving circuit applied to a cholesteric liquid crystal display device. In this embodiment, the display driving circuit includes three positive buffer groups, three negative buffer groups, a potential converter and an output switch. The three positive buffer groups are used to receive the first reference voltage, the second reference voltage and the third reference voltage respectively and to output the first positive driving voltage, the second positive driving voltage and the third positive driving voltage respectively. The three negative buffer groups are used to receive the fourth reference voltage, the fifth reference voltage and the sixth reference voltage respectively and to output the first negative driving voltage, the second negative driving voltage and the third negative driving voltage respectively. The potential converter and the output switch are respectively coupled to the three positive buffer groups and the three negative buffer groups for receiving the first positive driving voltage, the second positive driving voltage, the third positive driving voltage, and the first negative driving voltage. voltage, the second negative driving voltage and the third negative driving voltage and generate an output signal accordingly. Among them, the three positive buffer groups, the three negative buffer groups, the potential converter and the output switch all receive positive power supply voltage and negative power supply voltage.

In one embodiment, the display driving circuit further includes a receiving circuit, a shift register, a control logic circuit, a decoder and a data latch circuit. The receiving circuit receives the input data signal and the input clock signal respectively. The shift register and the control logic circuit are coupled between the receiving circuit, the decoder and the data latch circuit. The decoder and the data latch circuit are coupled between the shift register and the control logic circuit, the potential converter and the output switch.

In one embodiment, the cholesteric liquid crystal display device includes a reference voltage generating circuit coupled to the display driving circuit for generating a first reference voltage, a second reference voltage, a third reference voltage, a fourth reference voltage, a fifth reference voltage and The sixth reference voltage is supplied to the display driving circuit.

In one embodiment, the reference voltage generating circuit is disposed on a printed circuit board (PCB).

In one embodiment, the cholesteric liquid crystal display device further includes at least one display driving circuit that is the same as the display driving circuit. The at least one display driving circuit is coupled to the reference voltage generating circuit and receives the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage and the sixth reference voltage.

In one embodiment, the cholesteric liquid crystal display device includes a positive power supply voltage generating circuit and a negative power supply voltage generating circuit coupled to the display driving circuit for respectively generating positive power supply voltage and negative power supply voltage to the display driving circuit.

In one embodiment, the cholesteric liquid crystal display device further includes at least one display driving circuit that is the same as the display driving circuit. The at least one display driving circuit is coupled to the positive power supply voltage generating circuit and the negative power supply voltage generating circuit and receives the positive power supply voltage and the negative power supply voltage generating circuit. supply voltage.

In one embodiment, the positive power supply voltage generating circuit and the negative power supply voltage generating circuit are disposed on a printed circuit board (PCB).

Compared with the prior art, the display driving circuit proposed by the present invention for use in a cholesteric liquid crystal display device integrates one or more driving voltage source groups with passive and active components into its interior, which not only utilizes the advantages of the original display driving circuit. Process compatibility can reduce design risks and effectively simplify the design complexity of printed circuit boards (PCBs), thus significantly reducing their production costs.

A preferred embodiment according to the present invention is a display driving circuit applied to a cholesteric liquid crystal display device. Please refer to FIGS. 4 and 5 . FIG. 4 shows a schematic diagram of the cholesteric liquid crystal display device 4 in this embodiment. FIG. 5 shows a schematic diagram of the display driving circuit 41 applied to the cholesteric liquid crystal display device 4 .

As shown in Figure 4, the cholesterol liquid crystal display device 4 includes a positive power supply voltage generating circuit BOOST, a negative power supply voltage generating circuit BUCK, a reference voltage generating circuit P-GAMMA, a low voltage dropout voltage stabilizing circuit LDO and N display driving circuits 41~4N. Where N is a positive integer. The positive power supply voltage generating circuit BOOST, the negative power supply voltage generating circuit BUCK, the reference voltage generating circuit P-GAMMA and the low voltage dropout voltage stabilizing circuit LDO are all set on the printed circuit board PCB and are coupled to the +12V power supply, but they are not used as limit. The printed circuit board PCB is coupled to the N display driving circuits 41 to 4N through the flexible circuit board FPC and the array backplane circuit (Wring On Array) WOA.

The positive power supply voltage generating circuit BOOST is coupled to the N display driving circuits 41~4N respectively, and is used to generate the positive power supply voltage VPP to the N display driving circuits 41~4N. The negative power supply voltage generating circuit BUCK is coupled to the N display driving circuits 41~4N respectively, and is used to generate the negative power supply voltage VNN to the N display driving circuits 41~4N. The low dropout voltage stabilizing circuit LDO is coupled to the N display driving circuits 41~4N respectively, and is used to generate the operating voltage VDD to the N display driving circuits 41~4N. The reference voltage generating circuit P-GAMMA is coupled to the N display driving circuits 41~4N respectively to generate the first reference voltage REF1, the second reference voltage REF2, the third reference voltage REF3, the fourth reference voltage REF4, and the fifth reference voltage. REF5 and the sixth reference voltage REF6 to N display driving circuits 41~4N.

Next, the display driving circuit 41 will be described as an example. As shown in Figure 5, the display driving circuit 41 includes three positive buffer groups PBF, three negative buffer groups NBF, a receiving circuit 410, a shift register and a control logic circuit 411, a decoder and a data latch circuit 412 and potential converter and output switch 413.

The receiving circuit 410 is coupled to the shift register and the control logic circuit 411 for receiving the input data signal DAT_IN and the input clock signal CLK_IN. The shift register and control logic circuit 411 are coupled to the decoder and data latch circuit 412 for transmitting/receiving the data output input indication signal DIO. The decoder and data latch circuit 412 is coupled to the potential converter and the output switch 413 for receiving the control signal STB/SDOE/SDOZ related to decoding and data latching and performing data decoding and latch operations.

The three positive buffer groups PBF are coupled to the potential converter and the output switch 413 to respectively receive the first reference voltage REF1, the second reference voltage REF2 and the third reference voltage REF3 from the reference voltage generating circuit P-GAMMA and respectively The first positive driving voltage VP1, the second positive driving voltage VP2 and the third positive driving voltage VP3 are output to the potential converter and the output switch 413.

The three negative buffer groups NBF are coupled to the potential converter and the output switch 413 to respectively receive the fourth reference voltage REF4, the fifth reference voltage REF5 and the sixth reference voltage REF6 from the reference voltage generating circuit P-GAMMA and respectively The first negative driving voltage VN1, the second negative driving voltage VN2 and the third negative driving voltage VN3 are output to the potential converter and the output switch 413.

In addition, the three positive buffer groups PBF, the three negative buffer groups NBF, the potential converter and the output switch 413 also receive the positive power supply voltage VPP/from the positive power supply voltage generating circuit BOOST/negative power supply voltage generating circuit BUCK respectively. Negative supply voltage VNN.

The potential converter and the output switch 413 are respectively coupled to the three positive buffer groups PBF and the three negative buffer groups NBF for receiving the first positive driving voltage VP1, the second positive driving voltage VP2, and the third positive driving voltage. VP3, the first negative driving voltage VN1, the second negative driving voltage VN2 and the third negative driving voltage VN3 and generate the output signal OUT accordingly.

According to FIG. 4 and FIG. 5 , it can be seen that the cholesteric liquid crystal display device 4 in this embodiment uses the positive buffer group PBF and the negative buffer group NBF to share the same process with each display driving circuit 41 ~ 4N (both can use LV/HV =3.3V/50V), three positive buffer groups PBF and three negative buffer groups NBF are integrated into the display driving circuit 41 to become three positive buffer groups PBF and three negative buffer groups embedded in the display driving circuit 41 A negative buffer group NBF is provided to provide the first to third positive driving voltages VP1 to VP3 and the first to third negative driving voltages VN1 to VN3 required by the display driving circuit 41 itself. As for the other display driving circuits 42 to 4N of the cholesterol liquid crystal display device 4 , the same can be said and will not be described again here.

Since the printed circuit board PCB in this embodiment does not need to be equipped with a large number of active and passive components to provide driving voltage to each display driving circuit as in the prior art, it only needs to provide the first reference voltage REF1 through the reference voltage generating circuit P-GAMMA. The sixth reference voltage REF6 can be supplied to the three positive buffer groups PBF and three negative buffer groups NBF embedded in each display driving circuit. Therefore, the circuit design on the printed circuit board PCB can be greatly simplified and production can be effectively saved. cost.

Another preferred embodiment according to the present invention is also a display driving circuit applied to a cholesteric liquid crystal display device. Please refer to FIG. 6 and FIG. 7A to FIG. 7C. FIG. 6 illustrates a schematic diagram of the cholesteric liquid crystal display device 6 in this embodiment. FIGS. 7A to 7C respectively illustrate three display driving circuits 61 applied to the cholesteric liquid crystal display device 6. Schematic diagram of ~63.

As shown in Figure 6, the cholesterol liquid crystal display device 6 includes a positive power supply voltage generating circuit BOOST, a negative power supply voltage generating circuit BUCK, a reference voltage generating circuit P-GAMMA, a low voltage dropout voltage stabilizing circuit LDO, a bus BUS and N display driving circuits 61~6N, where N is a positive integer and a multiple of 3 (that is, every three display driving circuits are a group). The positive power supply voltage generating circuit BOOST, the negative power supply voltage generating circuit BUCK, the reference voltage generating circuit P-GAMMA and the low voltage dropout voltage stabilizing circuit LDO are all set on the printed circuit board PCB and are coupled to the +12V power supply, but they are not used as limit. The printed circuit board PCB is coupled to the N display driving circuits 61 to 6N through the flexible circuit board FPC and the array backplane circuit WOA. The bus BUS is installed on the flexible circuit board FPC.

The positive power supply voltage generating circuit BOOST is coupled to the N display driving circuits 61 ~ 6N respectively, and is used to generate the positive power supply voltage VPP to the N display driving circuits 61 ~ 6N. The negative power supply voltage generating circuit BUCK is coupled to the N display driving circuits 61 ~ 6N respectively, and is used to generate the negative power supply voltage VNN to the N display driving circuits 61 ~ 6N. The low dropout voltage stabilizing circuit LDO is coupled to the N display driving circuits 61 ~ 6N respectively, and is used to generate the operating voltage VDD to the N display driving circuits 61 ~ 6N. The reference voltage generating circuit P-GAMMA is coupled to the N display driving circuits 61 to 6N respectively. The bus BUS is coupled to the N display driving circuits 61 to 6N respectively.

Taking the same display driving circuits 61 to 63 as an example, the reference voltage generating circuit P-GAMMA generates the first reference voltage REF1 and the fourth reference voltage REF4 to the display driving circuit 61, and generates the second reference voltage REF2 and the fifth reference voltage REF2. The reference voltage REF5 is sent to the display driving circuit 62, and the third reference voltage REF3 and the sixth reference voltage REF6 are generated to the display driving circuit 63; the bus BUS receives the first positive driving voltage VP1 and the first negative driving voltage from the display driving circuit 61 respectively. voltage VN1, the second positive driving voltage VP2 and the second negative driving voltage VN2 from the display driving circuit 62, and the third positive driving voltage VP3 and the third negative driving voltage VN3 from the display driving circuit 63, and the bus BUS can The first to third positive driving voltages VP1 to VP3 and the first to third negative driving voltages VN1 to VN3 are provided to each of the display driving circuits 61 to 63 respectively. The same can be said for other display driving circuits 64 to 6N, which will not be described again here.

Next, please refer to FIG. 7A , which is a schematic diagram of the display driving circuit 61 in FIG. 6 . As shown in FIG. 7A , the display driving circuit 61 includes a positive buffer group PBF, a negative buffer group NBF, a receiving circuit 610, a shift register and a control logic circuit 611, a decoder and a data latch circuit 612 and a potential Converter and output switch 613.

The receiving circuit 610 is coupled to the shift register and the control logic circuit 611 for receiving the input data signal DAT_IN and the input clock signal CLK_IN. The shift register and control logic circuit 611 is coupled to the decoder and data latch circuit 612 for transmitting/receiving the data output input indication signal DIO. The decoder and data latch circuit 612 is coupled to the potential converter and the output switch 613 for receiving the control signal STB/SDOE/SDOZ related to decoding and data latching and performing data decoding and latch operations.

The positive buffer group PBF is used to receive the first reference voltage REF1 from the reference voltage generating circuit P-GAMMA and output the first positive driving voltage VP1 to the bus BUS. The negative buffer group NBF is used to receive the fourth reference voltage REF4 from the reference voltage generating circuit P-GAMMA and output the first negative driving voltage VN1 to the bus BUS. The potential converter and the output switch 613 are coupled to the bus BUS for receiving the first positive driving voltage VP1 to the third positive driving voltage VP3 and the first negative driving voltage VN1 to the third negative driving voltage VN3 from the bus BUS and according to the Generates an output signal OUT.

As for FIG. 7B and FIG. 7C , respectively, schematic diagrams of the display driving circuits 62 to 63 in FIG. 6 are shown. Their circuit structure and operation can be deduced from the text descriptions in FIG. 7A and the previous three paragraphs, so they will not be described again here.

According to FIG. 6 and FIG. 7A to FIG. 7C , it can be seen that if the same display driving circuits 61 to 63 are used as an example, the cholesteric liquid crystal display device 6 in this embodiment uses a positive buffer group PBF and a negative buffer group NBF. The three positive buffer groups PBF and three negative buffer groups NBF can be integrated into the three display driving circuits 61~63 due to the shared process with the display driving circuit (both can use LV/HV=3.3V/50V). It becomes three positive buffer groups PBF and three negative buffer groups NBF respectively embedded in the display driving circuits 61 to 63. The display driving circuit 61 is then connected to the display driving circuit 61 through the bus BUS and pull wires provided on the flexible circuit board FPC. The first positive driving voltage VP1 and the first negative driving voltage VN1 are provided, the second positive driving voltage VP2 and the second negative driving voltage VN2 provided by the display driving circuit 62, and the third positive driving voltage VP3 provided by the display driving circuit 63 and The third negative driving voltage VN3 is simultaneously shared by the three display driving circuits 61 to 63, thereby effectively reducing the area of each display driving circuit 61 to 63. The same can be said for other display driving circuits 64 to 6N, which will not be described again here.

Since the printed circuit board PCB in this embodiment does not need to be equipped with a large number of active and passive components to provide driving voltages to each display driving circuit as in the prior art, it only needs to provide different sets of reference voltages through the reference voltage generating circuit P-GAMMA. Different positive buffer groups PBF and negative buffer groups NBF are embedded in each display driving circuit and are used with the bus BUS and pull wires on the flexible circuit board FPC to share the driving voltage to each display driving circuit, so the printed circuit can be greatly simplified. The circuit design on the board PCB can effectively save production costs.

Compared with the prior art, the display driving circuit proposed by the present invention for use in a cholesteric liquid crystal display device integrates one or more driving voltage source groups with passive and active components into its interior, which not only utilizes the advantages of the original display driving circuit. Process compatibility can reduce design risks and effectively simplify the design complexity of printed circuit boards (PCBs), thus significantly reducing their production costs.

1:Cholesterol LCD device 11~1N: Display drive circuit BOOST: Positive supply voltage generating circuit BUCK: Negative supply voltage generating circuit P-GAMMA: Reference voltage generation circuit LDO: low dropout voltage regulator circuit PCB: printed circuit board FPC: flexible circuit board WOA: array backplane circuit PBF: positive buffer group NBF: negative buffer group BUS: bus VPP: Positive supply voltage VNN: negative supply voltage VDD: working voltage REF1~REF6: first reference voltage~sixth reference voltage VP1~VP3: first positive driving voltage~third positive driving voltage VN1~VN3: first negative driving voltage~third negative driving voltage R1~R2: feedback resistor BF: buffer 110: Receiving circuit 111: Shift register and control logic circuit 112: Decoder and data latch circuit 113: Potential converter and output switch OUT: output signal VPP: Positive supply voltage VNN: negative supply voltage DAT_IN: input data signal CLK_IN: input clock signal STB/SDOE/SDOZ: control signal DIO: data output input indication signal 4:Cholesterol LCD device 41~4N: Display drive circuit 410: Receiving circuit 411: Shift register and control logic circuit 412: Decoder and data latch circuit 413: Potential converter and output switch 6:Cholesterol LCD device 61~6N: Display drive circuit 610: Receiving circuit 611: Shift register and control logic circuit 612: Decoder and data latch circuit 613: Potential converter and output switch 620: Receiving circuit 621: Shift register and control logic circuit 622: Decoder and data latch circuit 623: Potential converter and output switch 630: Receiving circuit 631: Shift register and control logic circuit 632: Decoder and data latch circuit 633: Potential converter and output switch

FIG. 1 is a schematic diagram of a prior art cholesteric liquid crystal display device.

FIG. 2A and FIG. 2B are schematic diagrams of the positive buffer group and the negative buffer group in FIG. 1 respectively.

FIG. 3 is a schematic diagram of the display driving circuit in FIG. 1 .

FIG. 4 is a schematic diagram of a cholesteric liquid crystal display device in an embodiment of the present invention.

FIG. 5 is a schematic diagram of a display driving circuit applied to a cholesteric liquid crystal display device.

FIG. 6 is a schematic diagram of a cholesteric liquid crystal display device in another specific embodiment of the present invention.

7A to 7C respectively illustrate schematic diagrams of three display driving circuits applied to a cholesteric liquid crystal display device.

41:Display drive circuit

410: Receiving circuit

411: Shift register and control logic circuit

412: Decoder and data latch circuit

413: Potential converter and output switch

PBF: positive buffer group

NBF: negative buffer group

REF1~REF6: first reference voltage~sixth reference voltage

VP1~VP3: first positive driving voltage~third positive driving voltage

VN1~VN3: first negative driving voltage~third negative driving voltage

OUT: output signal

VPP: Positive supply voltage

VNN: negative supply voltage

DAT_IN: input data signal

CLK_IN: input clock signal

STB/SDOE/SDOZ: control signal

DIO: data output input indication signal

Claims (8)

A display driving circuit applied to a cholesteric liquid crystal display device, the display driving circuit includes: Three positive buffer groups are used to receive the first reference voltage, the second reference voltage and the third reference voltage respectively and to output the first positive driving voltage, the second positive driving voltage and the third positive driving voltage respectively; Three negative buffer groups are used to receive the fourth reference voltage, the fifth reference voltage and the sixth reference voltage respectively and to output the first negative driving voltage, the second negative driving voltage and the third negative driving voltage respectively; and The potential converter and the output switch are respectively coupled to the three positive buffer groups and the three negative buffer groups for receiving the first positive driving voltage, the second positive driving voltage, the third positive driving voltage, the first negative driving voltage, the second negative driving voltage and the third negative driving voltage and generate an output signal accordingly; Among them, the three positive buffer groups, the three negative buffer groups, the potential converter and the output switch all receive positive power supply voltage and negative power supply voltage. The display driving circuit as described in claim 1 also includes a receiving circuit, a shift register, a control logic circuit, a decoder and a data latch circuit; the receiving circuit receives the input data signal and the input clock signal respectively; the shift circuit A bit register and a control logic circuit are coupled between the receiving circuit and the decoder and data latch circuit; the decoder and data latch circuit are coupled between the shift register and control logic circuit and the potential between converter and output switch. The display driving circuit of claim 1, wherein the cholesteric liquid crystal display device includes a reference voltage generating circuit coupled to the display driving circuit for generating the first reference voltage, the second reference voltage, and the third reference voltage. , the fourth reference voltage, the fifth reference voltage and the sixth reference voltage to the display driving circuit. The display driving circuit of claim 3, wherein the cholesteric liquid crystal display device further includes at least one display driving circuit that is the same as the display driving circuit, and the at least one display driving circuit is coupled to the reference voltage generating circuit and receives the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage and the sixth reference voltage. The display driving circuit of claim 3, wherein the reference voltage generating circuit is disposed on a printed circuit board. The display driving circuit of claim 1, wherein the cholesteric liquid crystal display device includes a positive power supply voltage generating circuit and a negative power supply voltage generating circuit, coupled to the display driving circuit, for respectively generating positive power supply voltage and negative power supply voltage to the Display driver circuit. The display driving circuit of claim 6, wherein the cholesteric liquid crystal display device further includes at least one display driving circuit that is the same as the display driving circuit, and the at least one display driving circuit is coupled to the positive power supply voltage generating circuit and the negative power supply voltage. A circuit is generated and receives the positive supply voltage and the negative supply voltage. The display driving circuit of claim 6, wherein the positive power supply voltage generating circuit and the negative power supply voltage generating circuit are disposed on a printed circuit board.

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