TW202349740A - Optoelectronic semiconductor device - Google Patents

Abstract

An optoelectronic semiconductor device is provided. The optoelectronic semiconductor device includes a base, a stack of semiconductor layers, an insulating structure, a first electrode, a second electrode and a first conductive structure. The base has an edge. The stack of semiconductor layers is positioned on the base. The stack of semiconductor layers includes a first sidewall. The insulating structure has a first insulating portion covering the first sidewall. The first electrode and the second electrode are respectively positioned on the stack of semiconductor layers. The first conductive structure is physically separated from the first electrode and the second electrode. In addition, the first conductive structure covers the first insulating portion. The first conductive structure has a first area and a second area physically separated from each other.

Description

Optoelectronic semiconductor components

The present disclosure relates to an optoelectronic semiconductor component, and in particular to a light emitting diode component.

Semiconductor components are used in a wide range of applications, and research and development on related materials continues. For example, III-V semiconductor materials containing Group III and Group V elements can be used in various optoelectronic semiconductor components such as light-emitting wafers (such as light-emitting diodes or laser diodes), light-absorbing wafers (photodetectors) or solar cells) or non-luminous wafers (such as power components of switches or rectifiers), which can be used in lighting, medical, display, communications, sensing, power systems and other fields.

With the advancement of technology, the size of optoelectronic semiconductor components is gradually becoming smaller. In recent years, due to breakthroughs in the size of light-emitting diodes (LEDs), micro-LED displays, which are made by arranging light-emitting diodes in an array, are gradually gaining popularity in the market. attach great importance to. Compared with organic light-emitting diode (OLED) displays, micro-light-emitting diode displays are more power-saving, have better reliability, longer service life and better contrast performance , and can be viewed in sunlight. With the development of science and technology, there are still many technical research and development needs for optoelectronic semiconductor components. Although existing optoelectronic semiconductor devices have generally met various needs, they are not satisfactory in all aspects and require further improvement.

An embodiment of the present disclosure provides an optoelectronic semiconductor device. The above-mentioned optoelectronic semiconductor element includes a substrate, a semiconductor stack, an insulating structure, a first electrode, a second electrode, and a first conductive structure. The base has an edge, and the semiconductor stack is located on the base and includes a first sidewall. The insulation structure has a first insulation portion covering the first side wall. The first electrode and the second electrode are respectively located on the semiconductor stack. The first conductive structure is physically separated from the first electrode and the second electrode, and covers the first insulating part. The first conductive structure has a first region and a second region that are separated from each other.

The present disclosure will be more fully explained below with reference to the drawings of embodiments of the present disclosure. However, the present disclosure can also be implemented in various different implementations and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers refer to the same or similar elements in the various drawings.

Embodiments of the present disclosure provide an optoelectronic semiconductor device. The optoelectronic semiconductor element includes a semiconductor stack located on a substrate, an insulating structure covering sidewalls of the semiconductor stack, a first electrode and a second electrode located on the semiconductor stack and separated from each other, and physically connected to the first electrode and the second electrode. Separate conductive structures. The conductive structure located on the sidewall of the semiconductor stack has a first portion and a second portion separated from each other. When the first electrode and the second electrode of the optoelectronic semiconductor element are assembled and electrically connected to the external circuit respectively, the first part and the second part of the conductive structure can avoid the process of forming the first electrode, the second electrode and the conductive structure. may remain on the sidewalls of the semiconductor stack, causing short circuit problems in optoelectronic semiconductor components.

Figure 1 is a schematic top view of an optoelectronic semiconductor device 500a according to some embodiments of the present disclosure. Figure 2 is a schematic cross-sectional view of the optoelectronic semiconductor device 500a taken along the tangent line AA' in Figure 1 according to some embodiments of the present disclosure. In some embodiments, the length of the optoelectronic semiconductor element 500a is no more than 150 microns, preferably in the range of 10 microns to 150 microns, or 10 microns to 60 microns, or 60 microns to 150 microns, and the width is no more than 100 microns, preferably The preferred range is 5 microns to 100 microns, or 5 microns to 30 microns, or 30 microns to 75 microns.

As shown in Figures 1 and 2, the optoelectronic semiconductor element 500a includes a substrate 204, a semiconductor stack 208, an insulating structure 236, a first electrode 246, a second electrode 248, and a first conductive structure 242.

As shown in Figures 1 and 2, the base 204 has a top surface 201 and a bottom surface 203 opposite to each other, and an edge 205. In some embodiments, the substrate 204 may include a growth substrate, a bonding substrate. The material of the substrate 204 may include sapphire (Sapphire), gallium arsenide (GaAs), silicon (Si), gallium nitride (GaN), indium phosphide (InP), glass (glass), ceramic materials or metals. As shown in FIG. 2 , the optoelectronic semiconductor device 500 a optionally includes a bonding layer 206 between the substrate 204 and the semiconductor stack 208 . The materials of the bonding layer 206 include benzocyclobutene (BCB), polyimide (PI), silicon dioxide (SiO ₂ ), silicon nitride (SiNx), titanium dioxide (TiO ₂ ), pentoxide Tantalum (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), or a combination of the above materials.

As shown in Figure 2, the semiconductor stack 208 is an epitaxial structure layer, which includes a first-type semiconductor layer 208a, a second-type semiconductor layer 208c, and is located between the first-type semiconductor layer 208a and the second-type semiconductor layer 208c. active layer 208b. In some embodiments, the first-type semiconductor layer 208a and the second-type semiconductor layer 208c have opposite conductivity types. For example, the first-type semiconductor layer 208a is an n-type semiconductor layer and the second-type semiconductor layer 208c is a p-type. semiconductor layer. Alternatively, the first type semiconductor layer 208a may be a p-type semiconductor layer, and the second type semiconductor layer 208c may be an n-type semiconductor layer. The materials of the first type semiconductor layer 208a, the second type semiconductor layer 208c and the active layer 208b may include gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), aluminum gallium nitride (AlGaN), Indium gallium nitride (InGaN), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), or aluminum indium gallium phosphide (AlGaInP).

In FIG. 2 , the semiconductor stack 208 includes a first mesa area 210 , a second mesa area 212 , a first flat area 216 , a second flat area 214 and a third flat area 218 . The first flat area 216 is located between the first elevated area 210 and the second elevated area 212 , the first elevated area 210 is located between the first flat area 216 and the second flat area 214 , and the second elevated area 212 is located between the first flat area 216 and the second flat area 214 . between area 216 and the third flat area 218. Specifically, the first mesa area 210 and the second mesa area 212 include a first type semiconductor layer 208a, a second type semiconductor layer 208c and an active layer 208b; a first flat area 216, a second flat area 214 and a third flat area. 218 includes only the first type semiconductor layer 208a.

As shown in FIG. 2 , the semiconductor stack 208 includes a plurality of sidewalls 220 and 224 since it includes a plurality of mesas and flat areas. In detail, the side wall 220 may include the side wall 220a of the second flat area 214 and the side wall 220b of the third flat area 218. The side wall 224 may include the side walls 224a1 and 224a2 of the first elevated area 210 and the side walls 224b1 and 224b1 of the second elevated area 212. 224b2. As shown in Figures 1 and 2, side walls 220 and 224 are not flush with each other. The side wall 220 is closer to the edge 205 of the base 204 than the side wall 224 , and the angle θ between the side wall 220 and the top surface 201 of the base 204 may be between 60 degrees and 90 degrees.

As shown in FIGS. 1 and 2 , the insulating structure 236 covers the semiconductor stack 208 and extends to cover a portion of the top surface 201 of the substrate 204 . The insulation structure 236 may cover the top surface and side walls 220a of the second flat area 214, the top surface and side walls 224a1, 224a2 of the first elevated area 210, part of the top surface of the first flat area 216, and the side walls 224b1, 224b1, of the second elevated area 212. 224b2 and part of the top surface, as well as the top surface and side walls 220b of the third flat area 218. In some embodiments, the insulation structure 236 has a first insulation portion 236a covering the sidewall 220 and a second insulation portion 236b covering the sidewall 224. The first insulating part 236a and the second insulating part 236b are connected to each other. The insulating structure 236 has openings on the top surfaces of the first flat area 216 and the second mesa area 212 respectively, so as to expose part of the first type semiconductor layer 208a and part of the second type semiconductor layer 208c respectively. In some embodiments, the insulation structure 236 may be composed of a stack of two or more materials with different refractive indexes. For example, the material of the insulating structure 236 may include silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), silicon nitride (SiN _x ), or stack combinations thereof. Insulating structure 236 may include a Bragg reflector (DBR).

As shown in FIGS. 1 and 2 , the optoelectronic semiconductor device 500 a includes a first contact layer 230 and a second contact layer 234 located on the semiconductor stack 208 . The first contact layer 230 and the second contact layer 234 are respectively located at the openings of the insulating structure 236 on the first flat area 216 and the second elevated area 212 and cover part of the top surfaces of the first flat area 216 and the second elevated area 212, and The first type semiconductor layer 208a and the second type semiconductor layer 208c are electrically connected respectively. The width of the first contact layer 230 may be smaller than the width of the first flat region 216 , and the width of the second contact layer 234 may be smaller than the width of the second mesa region 212 . The insulating structure 236 is spaced apart from and not in direct contact with the first contact layer 230 and the second contact layer 234 .

In some embodiments, the first contact layer 230 and the second contact layer 234 may be a single layer or multiple layers. The first contact layer 230 and the second contact layer 234 may include metal, alloy, or metal oxide. The metal first contact layer and the second contact layer include gold (Au), copper (Cr), titanium (Ti), aluminum (Al), nickel (Ni), platinum (Pt), silver (Ag), zinc (Zn), Germanium (Ge), beryllium (Be). Alloys are combinations of the above metals. Metal oxides include indium tin oxide (ITO), indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or indium gallium oxide. In some embodiments, the first contact layer 230 and the second contact layer 234 may be selectively formed one after another, and they may be formed of the same or different materials.

As shown in FIGS. 1 and 2 , the optoelectronic semiconductor element 500 a includes a first electrode 246 and a second electrode 248 that are physically separated from each other and are respectively located on the semiconductor stack 208 and away from the substrate 204 . The first electrode 246 compliantly covers the first flat area 216 and the first contact layer 230 , and extends to cover a portion of the insulating structure 236 located on the first elevated area 210 and the second elevated area 212 . The second electrode 248 compliantly covers the second mesa area 212 and the second contact layer 234 , and extends to cover part of the insulation structure 236 on the second mesa area 212 . The first electrode 246 may have a first thickness T1, and the second electrode 248 may have a second thickness T2. The first thickness T1 and the first thickness T2 may be the same or different. For example, the first electrode 246 located in the first mesa area 210 may have a first thickness T1 along the normal direction of the substrate 204, and the second electrode 248 located in the second mesa area 212 may also have a thickness T1 along the normal direction of the substrate 204. Having a second thickness T2, the first thickness T1 is equal to the second thickness T2. In the top view of FIG. 1 , the first electrode 246 and the second electrode 248 are spaced apart from each other by a distance W2. In some embodiments, the first electrode 246 is electrically connected to the first type semiconductor layer 208a of the semiconductor stack 208 through the first contact layer 230, and the second electrode 248 is electrically connected to the semiconductor stack 208 through the second contact layer 234. second type semiconductor layer 208c.

In some embodiments, the first electrode 246 and the second electrode 248 may be a single layer or multiple layers. The first electrode 246 and the second electrode 248 may include metals, alloys, or metal oxides. In some embodiments, the first electrode 246 and the second electrode 248 are transparent to the light emitted by the active layer 208b. Therefore, the light can be emitted out of the optoelectronic semiconductor device 500a through the direction 250 of the first electrode 246 and the second electrode 248. The first electrode 246 and the second electrode 248 may be of the same or different materials.

As shown in FIGS. 1 and 2 , the optoelectronic semiconductor element 500 a includes a first conductive structure 242 and a second conductive structure 244 that are physically separated from the first electrode 246 and the second electrode 248 . The first conductive structure 242 covers the first insulating portion 236 a of the insulating structure 236 and the second conductive structure 244 covers the second insulating portion 236 b of the insulating structure 236 . In some embodiments, as viewed from the top view of FIG. 1 , the first conductive structure 242 has a first region 242 a and a second region 242 b that are physically separated from each other. Specifically, the first area 242a covers the side wall 220a of the second flat area 214, and the second area 242b covers the side wall 220b of the third flat area 218. In some embodiments, as viewed from the top view of FIG. 1 , the second conductive structure 244 has a third region 244a and a fourth region 244b that are separated from each other. Specifically, the third area 244a covers the side wall 224a1 of the first raised platform area 210, and the fourth area 244b covers the side wall 224b1 of the second raised platform area 212.

As shown in FIG. 1 , the third region 244a and the fourth region 244b of the second conductive structure 244 are spaced apart from each other by a distance W1, and the first region 242a and the second region 242b of the first conductive structure 242 are spaced apart from each other by a distance W1', a distance W1 and spacing W1' may be equal to each other or different from each other. In some embodiments, the distance W1 and the distance W1' are less than the distance W2 between the first electrode 246 and the second electrode 248. As shown in FIG. 2 , the first region 242a of the first conductive structure 242 may have a third thickness T3. For example, the first region 242a may have a third thickness T3 along the normal direction of the side wall 220a, and the second portion 242b may have a third thickness T3 along the normal direction of the side wall 220a. The side wall 220b has a fourth thickness T4 in the normal direction, and the third thickness T3 and the fourth thickness T4 may be the same or different. Similarly, the third region 244a of the second conductive structure 244 has a fifth thickness T5 along the normal direction of the side wall 224a1, and the fourth region 244b of the second conductive structure 244 has a sixth thickness T6 along the normal direction of the side wall 224b1. The fifth thickness T5 and the sixth thickness T6 may be the same or different. In some embodiments, the thickness of the first conductive structure 242 (the third thickness T3 or/and the fourth thickness T4 or/and the fifth thickness T5 or/and the sixth thickness T6) is smaller than the thickness of the first electrode or the second electrode. . For example, the thickness of the first conductive structure 242 is 0.3 times to 0.8 times the thickness of the first electrode or the second electrode (for example, the third thickness T3/the first thickness T1, the fourth thickness T4/the first thickness T1, The fifth thickness T5/the first thickness T1, the sixth thickness T6/the first thickness T1, the third thickness T3/the second thickness T2, the fourth thickness T4/the second thickness T2, the fifth thickness T5/the second thickness T2, Sixth thickness T6/second thickness T2). In some embodiments, the first electrode 246, the second electrode 248, the first conductive structure 242 and the second conductive structure 244 have the same material. In one embodiment, the thickness of the first conductive structure 242 may be gradually changed, for example, the third thickness T3, the fourth thickness T4, the fifth thickness T5, or/and the sixth thickness T6 are from the first electrode 246 to the substrate 204. The direction is increasing or decreasing. When the thickness of the first conductive structure 242 is gradient, its maximum thickness is defined as the above-mentioned third thickness T3, fourth thickness T4, fifth thickness T5, or/and sixth thickness T6.

Figure 3 is a schematic top view of an optoelectronic semiconductor device 500b according to some embodiments of the present disclosure. Figure 4 is a schematic cross-sectional view of the optoelectronic semiconductor device 500b taken along the tangent line AA' in Figure 3 according to some embodiments of the present disclosure. The same or similar component symbols in Figures 3 and 4 as those in Figures 1 and 2 represent the same or similar components. The difference between the optoelectronic semiconductor element 500b and the optoelectronic semiconductor element 500a is that the optoelectronic semiconductor element 500b uses a third contact layer 232 instead of the second contact layer 234 as an electrical connection between the second electrode 248 and the second type semiconductor layer 208c. . In some embodiments, the third contact layer 232 completely covers the top surface of the first type semiconductor layer 208a in the second mesa region 212, and the width of the third contact layer 232 may be equal to or smaller than the width of the first type semiconductor layer 208a in the second mesa region 212. The width of the type-I semiconductor layer 208a. The third contact layer 232 is located between the semiconductor stack 208 and the second electrode 248 and is partially covered by the insulating structure 236 , and the top surface of the third contact layer 232 simultaneously contacts the insulating structure 236 and the second electrode 248 .

Figures 5A, 6A, 7A, and 8 are schematic top views of intermediate stages of manufacturing the optoelectronic semiconductor device 500a according to some embodiments of the present disclosure. Figures 5B, 6B, and 7B are schematic cross-sectional views taken along the tangent line AA' in Figures 5A, 6A, and 7A respectively. The following uses the optoelectronic semiconductor element 500a as an example, and illustrates the formation method of the first electrode 246 and the second electrode 248 of the conductive structures 242 and 244 of the optoelectronic semiconductor element 500a with reference to Figures 5A, 5B, 6A, 6B, 7A, 7B, and 8. .

Please refer to FIGS. 5A and 5B . After forming the semiconductor stack 208 , the first contact layer 230 , the second contact layer 234 and the insulating structure 236 on the substrate 204 , a conductive material layer 240 is compliantly formed on the semiconductor stack 208 . The conductive material layer 240 comprehensively covers the semiconductor stack 208 , the first contact layer 230 , the second contact layer 234 and the insulating structure 236 , and extends to cover part of the substrate 204 . In some embodiments, the conductive material layer 240 may be formed by a deposition process. The deposition process includes evaporation, sputtering, or other suitable vacuum coating processes. In an embodiment where the deposition process is an evaporation process, due to the principle of the evaporation process, the thickness of the deposited conductive material layer 240 on the sidewalls 220 and 224 of the semiconductor stack 208 may be less than or equal to the thickness of the conductive material layer 240 on the semiconductor stack 208 The thickness on the top surface of the first elevated area 210 , the second elevated area 212 , the first flat area 216 , the second flat area 214 and the third flat area 218 .

Please refer to Figures 6A and 6B. Next, masks 310 and 320 separated from each other are formed on the conductive material layer 240. The masks 310 and 320 are respectively located directly above the first flat area 216 and the second elevated area 212 to define the formation position and size of the first electrode 246 and the second electrode 248 . In some embodiments, the mask 310 covers the first flat area 216 and the first contact layer 230 , and extends to cover parts of the first and second mesa areas 210 and 212 adjacent to the first flat area 216 . The mask 320 covers part of the second mesa area 212 and the second contact layer 232 . In some embodiments, masks 310, 320 are spaced apart from each other by a spacing W2.

Please refer to FIGS. 7A and 7B. Next, a first etching process is performed on the conductive material layer 240 to form the first electrode 246 and the first electrode 246 on the top surface of the first flat area 216 and the second mesa area 212 of the semiconductor stack 208. Two electrodes 248 are formed on the sidewalls 220 and 224 of the semiconductor stack 208 respectively to form conductive structures 242 and 244. The conductive structure 242 surrounds and covers the sidewall 220 of the semiconductor stack 208 , and the conductive structure 244 surrounds and covers the sidewall 224 of the semiconductor stack 208 . In some embodiments, the first etching process includes dry etching. After performing the first etching process, the masks 310 and 320 are removed.

Please refer to FIG. 8. Next, separate masks 330 and 340 are formed on the first electrode 246 and the second electrode 248 to cover the first electrode 246 and the second electrode 248 respectively. In some embodiments, the top-view area of the masks 330, 340 is greater than the top-view area 8 of the first electrode 246 and the second electrode 248, respectively. As shown in FIG. 8 , the mask 330 is located directly above the first electrode 246 and extends to cover part of the sidewalls 220 and 224 of the semiconductor stack 208 . In detail, the mask 330 completely covers the first electrode 246, and covers the top surface and sidewalls 224a1 of the first mesa area 210, and the top surface and sidewalls 220a of the second flat area 214. The mask 340 is located directly above the second electrode 248 and extends to cover portions of the sidewalls 220 and 224 of the semiconductor stack 208 . In detail, the mask 340 completely covers the second electrode 248, and covers the top surface and sidewalls 224b of the second mesa area 212, and the top surface and sidewalls 220b of the third flat area 218. As shown in FIG. 8 , the masks 330 and 340 are spaced apart from each other by a distance W1 to expose portions of the conductive structures 242 and 244 on the sidewalls 220 and 224 of the semiconductor stack 208 . Next, a second etching process is performed on the conductive structures 242 and 244 to remove part of the conductive structures 242 and 244 on the sidewalls 220 and 224 surrounding the semiconductor stack 208, so that the conductive structure 242 has an isolated first region 242a and The second region 242b and the conductive structure 244 have separate third regions 244a and fourth regions 244b. After performing the second etching process, the masks 330 and 340 are removed to form the optoelectronic semiconductor device 500a shown in FIG. 1 . In some embodiments, the distance W1 between the masks 330 and 340 is smaller than the distance W2 between the first electrode 246 and the second electrode 248 to ensure that during the second etching process, this step will not damage the first electrode 246 and second electrode 248 causing damage. In some embodiments, the second etching process and the first etching process are different etching processes, such as a wet etching process, to completely remove the sidewalls 220, 224 of the semiconductor stack 208 that are not covered by the masks 330, 340. conductive structures 242 and 244 to ensure that when the first electrode 246 and the second electrode 248 of the finally formed optoelectronic semiconductor element 500a are assembled and electrically connected to an external circuit, they are not electrically connected to the surrounding semiconductor stack 208 The conductive structures 242 and 244 on the side walls 220 and 224 cause short circuit problems for the optoelectronic semiconductor components.

Figure 9 is a schematic top view of an optoelectronic semiconductor device 500c according to some embodiments of the present disclosure. Figure 10 is a schematic cross-sectional view of the optoelectronic semiconductor device 500c taken along the tangent line AA' in Figure 9 according to some embodiments of the present disclosure. The same or similar component symbols in Figures 9 and 10 as those in Figures 1 and 2 represent the same or similar components. The difference between the optoelectronic semiconductor element 500c and the optoelectronic semiconductor element 500a is that the semiconductor stack 208 of the optoelectronic semiconductor element 500c does not include the second flat area 214 and the third flat area 218, that is, the semiconductor stack 208 only includes the first plateau area 210. , the second high platform area 212 and the first flat area 216 . Semiconductor stack 208 includes sidewalls 226 . In detail, the side walls 226 may include side walls 226a1 and 226a2 of the first raised platform area 210 and side walls 226b1 and 226b2 of the second raised platform area 212. The insulating structure 236 may cover the top surface and side walls 226a1, 226a2 of the first elevated area 210, part of the top surface of the first flat area 216, side walls 226b1, 226b2 and part of the top surface of the second elevated area 212. The first conductive structure 242 has a first region 242a and a second region 242b that are physically separated from each other. The first area 242a covers the side wall 226a1, and the second area 242b covers the side wall 226b1.

Although the disclosure is disclosed in the foregoing embodiments, this is not intended to limit the disclosure. Those skilled in the art may make slight changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope of the appended patent application.

200:Base 201:Top surface 203: Bottom 204: Laminated substrate 205: Edge 206:Jointing layer 208: Semiconductor stack 208a: First type semiconductor layer 208b:Active layer 208c: Second type semiconductor layer 210:The first high platform area 212:Second Gaotai District 214: The second flat area 216:First flat area 218:The third flat area 220,220a,220b,224,224a1,224a2,224b1,224b2,226,226a1,226a2,226b1,226b2: side wall 230: First contact layer 232:Third contact layer 234: Second contact layer 236:Insulation structure 236a: First insulation part 236b: Second insulation part 240: Conductive material layer 242,244:Conductive structure 242a:First area 242b:Second area 244a:The third area 244b:The fourth area 246:First electrode 248:Second electrode 250: direction 310,320,330,340: Mask 500a, 500b, 500c: Optoelectronic semiconductor components A-A': Tangent line T1: first thickness T2: second thickness T3: The third thickness T4: The fourth thickness T5: fifth thickness T6: sixth thickness W1,W1',W2: spacing θ: included angle

The embodiments of the disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of elements may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present disclosure. Figure 1 is a schematic top view of an optoelectronic semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view of an optoelectronic semiconductor device according to some embodiments of the present disclosure, taken along the tangent line AA′ in FIG. 1 . Figure 3 is a schematic top view of an optoelectronic semiconductor device according to some embodiments of the present disclosure. FIG. 4 is a schematic cross-sectional view of an optoelectronic semiconductor device taken along the tangent line AA' in FIG. 3 according to some embodiments of the present disclosure. Figures 5A, 6A, 7A, and 8 are schematic top views of intermediate stages of manufacturing optoelectronic semiconductor devices according to some embodiments of the present disclosure. Figures 5B, 6B, and 7B are respectively schematic cross-sectional views taken along the tangent line AA' in Figures 5A, 6A, and 7A during an intermediate stage of manufacturing an optoelectronic semiconductor device according to some embodiments of the present disclosure. Figure 9 is a schematic top view of an optoelectronic semiconductor device according to some embodiments of the present disclosure. FIG. 10 is a schematic cross-sectional view of an optoelectronic semiconductor device according to some embodiments of the present disclosure, taken along the tangent line AA′ in FIG. 9 .

200:Base

205: Edge

208: Semiconductor stack

220,220a,220b,224,224a1,224b1: side wall

230: First contact layer

234: Second contact layer

236:Insulation structure

236a: First insulation part

236b: Second insulation part

242,244:Conductive structure

242a:First area

242b:Second area

244a:The third area

244b:The fourth area

246:First electrode

248:Second electrode

500a: Optoelectronic semiconductor components

A-A': Tangent line

W1,W1',W2: spacing

Claims (10)

An optoelectronic semiconductor component, including: a base with an edge; a semiconductor stack located on the substrate and including a first sidewall; An insulating structure having a first insulating portion covering the first side wall; A first electrode and a second electrode are respectively located on the semiconductor stack; and a first conductive structure, physically separated from the first electrode and the second electrode, and covering the first insulating part; The first conductive structure has a first region and a second region that are physically separated from each other. The optoelectronic semiconductor device of claim 1, wherein the first conductive structure and the first electrode or the second electrode have the same material. The optoelectronic semiconductor element of claim 1, wherein the first region and the second region of the first conductive structure are spaced apart from each other by a first spacing, the first electrode and the second electrode are spaced apart from each other by a second spacing, and the The first distance is smaller than the second distance. For example, the optoelectronic semiconductor component of claim 1 further includes: A second conductive structure, wherein the semiconductor stack further includes a second sidewall and the insulating structure has a second insulating portion covering the second sidewall, and the second conductive structure covers the second insulating portion. The optoelectronic semiconductor device of claim 4, wherein the second conductive structure has a third region and a fourth region that are physically separated from each other. The optoelectronic semiconductor device of claim 5, wherein the third region and the fourth region of the second conductive structure are spaced apart from each other by a third spacing, the first electrode and the second electrode are spaced apart from each other by a second spacing, and the third region is spaced apart from each other by a third spacing. The third pitch is smaller than the second pitch. The optoelectronic semiconductor device of claim 4, wherein the first conductive structure is physically separated from the first electrode and the second electrode. For example, the optoelectronic semiconductor component of claim 1 further includes: A contact layer is located between the semiconductor stack and the second electrode. The optoelectronic semiconductor element of claim 1, wherein the first electrode and the second electrode are made of transparent conductive material, and the optoelectronic semiconductor element emits a light in a direction of the first electrode and the second electrode. The optoelectronic semiconductor device of claim 1, wherein the first electrode has a first thickness, and the first portion of the first conductive structure has a second thickness smaller than the first thickness.

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