TW202349517A - Semiconductor substrate structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor substrate structure includes a first group of circuit structure and a second group of circuit structure. The first group of circuit structure includes a plurality of first wiring layers and a first bonding layer. The second group of circuit structure includes a plurality of second wiring layers and a second bonding layer. The second group of circuit structure is disposed on the first group of circuit structure and is electrically connected to the first group of circuit structure. The first bonding layer is bonded to the second bonding layer to form a multilayer redistribution structure. A manufacturing method of the semiconductor substrate structure is also provided.

Description

Semiconductor substrate structure and manufacturing method thereof

The invention relates to a semiconductor substrate structure and a manufacturing method thereof.

In integrated circuit applications, the redistribution line layer (RDL) is a multi-layer structure formed by conductive materials and dielectric materials, and the RDL is often produced on a temporary carrier. However, the materials used in the aforementioned multi-layer structure are not the same as the temporary carrier. The materials used in the carrier will have a coefficient of thermal expansion (CTE) mismatch, so the process of continuously forming the aforementioned multi-layer structure (continuously forming at least four layers) on the temporary carrier can easily lead to warping problems. And the warpage problem will be more obvious as the number of layers increases, which will have a negative impact on the yield and electrical performance of the semiconductor substrate structure.

The present invention provides a semiconductor substrate structure and a manufacturing method thereof, which can maintain better yield and electrical performance while having a multi-layer rewiring structure.

A semiconductor substrate structure of the present invention includes a first group of circuit structures and a second group of circuit structures. The first group of circuit structures includes a plurality of first circuit layers and first bonding layers. The second set of circuit structures includes multiple layers of second circuit layers and second bonding layers. The second group of circuit structures is disposed on the first group of circuit structures and is electrically connected to the first group of circuit structures. The first bonding layer is bonded to the second bonding layer to form a multi-layer redistribution structure.

A semiconductor substrate structure of the present invention includes a first group of circuit structures, a second group of circuit structures and a third group of circuit structures. The first set of circuit structures includes a plurality of first circuit layers and first bonding layers. The second set of circuit structures includes multiple layers of second circuit layers and second bonding layers. The second group of circuit structures is disposed on the first group of circuit structures and is electrically connected to the first group of circuit structures. The first bonding layer is bonded to the second bonding layer. The third group of circuit structures includes multiple third circuit layers and third bonding layers. The second group of circuit structures is disposed between the first group of circuit structures and the third group of circuit structures and are electrically connected to each other. The second group of circuit structures has another bonding layer relative to the first group of circuit structures, and the other bonding layer The layer is bonded to a third bonding layer to form a multi-layer redistribution structure.

A method for manufacturing a semiconductor substrate structure of the present invention at least includes the following steps. A first group of circuit structures is formed on the first temporary carrier, wherein the first group of circuit structures includes multiple layers of first circuit layers and first bonding layers. A second set of circuit structures is formed on the second temporary carrier, wherein the second set of circuit structures includes multiple layers of second circuit layers and second bonding layers. The first group of circuit structures and the second group of circuit structures are directly bonded, so that the first bonding layer is bonded to the second bonding layer.

A method for manufacturing a semiconductor substrate structure of the present invention at least includes the following steps. A first group of circuit structures is formed on the first temporary carrier, wherein the first group of circuit structures includes multiple layers of first circuit layers and first bonding layers. A second set of circuit structures is formed on the second temporary carrier, wherein the second set of circuit structures includes multiple layers of second circuit layers and second bonding layers. The first group of circuit structures and the second group of circuit structures are directly bonded, so that the first bonding layer is bonded to the second bonding layer. A third group of circuit structures is formed on the second group of circuit structures. The third group of circuit structures includes multiple third circuit layers and third bonding layers. Join the second set of circuit structures to the third set of circuit structures. The second group of circuit structures has another bonding layer relative to the first group of circuit structures, and the other bonding layer is bonded to the third bonding layer to form a multi-layer redistribution structure.

A method for manufacturing a semiconductor substrate structure of the present invention at least includes the following steps. forming a second group of line structures on the second temporary carrier; forming a third group of line structures on the second group of line structures; joining the second group of line structures and the third group of line structures; removing the second temporary carrier; forming a first A set of circuit structures is placed on a first temporary carrier; directly joining the first group of circuit structures and a second group of circuit structures; removing the first temporary carrier; forming conductive pillars and conductive covers on the surface of the first group of circuit structures, and forming an external The terminals are on the surface of the third set of circuit structures.

A semiconductor substrate structure of the present invention includes a first group of circuit structures and a second group of circuit structures, wherein the second group of circuit structures is disposed on the first group of circuit structures and is electrically connected to the first group of circuit structures to form A multi-layer rewiring structure, and the dielectric layer in the first group of circuit structures and the dielectric layer in the second group of circuit structures are organic films.

Based on the above, the present invention first separately manufactures multiple sets of circuit structures on temporary carriers, and then directly joins and assembles the aforementioned multiple sets of circuit structures into a multi-layer rewiring structure. In this way, compared with the multi-layer rewiring structure produced continuously at one time In terms of structure, the degree of warpage can be effectively reduced, allowing the semiconductor substrate structure to maintain better yield and electrical performance while having a multi-layer rewiring structure.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Exemplary embodiments of the present invention will be fully described below with reference to the accompanying drawings, although the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the sizes and thicknesses of various regions, locations and layers are not drawn to actual scale for clarity. To facilitate understanding, the same components in the following description will be labeled with the same symbols.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention may also be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size, or dimensions of layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar components, and will not be repeated one by one in the following paragraphs.

Directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply absolute orientation.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

1A to 1I are partially schematic cross-sectional views illustrating a method of manufacturing a semiconductor substrate structure according to some embodiments of the present invention. 1J, 1K, and 1L are partially schematic cross-sectional views illustrating a method of manufacturing an alternative embodiment of the first set of circuit structures of FIG. 1D. 1M, 1N, and 1O are partial schematic cross-sectional views showing the structure of a semiconductor substrate according to other embodiments of the present invention. FIG. 1P is a schematic diagram illustrating semiconductor substrate structures when bonded according to some embodiments of the present invention. 1Q is a schematic diagram illustrating a semiconductor substrate structure after bonding according to some embodiments of the invention. FIG. 1R is a schematic diagram showing a conventional semiconductor substrate structure after bonding. Referring to FIG. 1A , multiple first circuit layers 111 are formed on the first temporary carrier 10 . The first temporary carrier 10 can be made of glass, plastic, silicon, metal or other suitable materials, as long as the material can withstand subsequent processes. And at the same time, it can carry the structure formed on it.

In some embodiments, a first release layer 12 (such as a photothermal conversion film or other suitable release layer) may optionally be coated between the first temporary carrier 10 and the first set of circuit structures 110 to enhance the The peelability between the first temporary carrier 10 and the first set of circuit structures 110 in the subsequent process can improve the flatness of the first set of circuit structures 110, but the invention is not limited thereto.

In this embodiment, a multi-layer first circuit layer 111 (six layers are schematically shown in FIG. 1A) and a first micro-bump 12a located on the first circuit layer 111 (followed by For forming the first joint member 112a) as shown in FIG. 1D, each first circuit layer 111 may include a first conductive pattern 111a, a first dielectric layer 111b and/or a first conductive via 111c. Here, the first conductive patterns 111a and the first conductive vias 111c may be embedded in the first dielectric layer 111b, and the first micro-bumps 12a may be electrically connected to the first circuit layer 111. However, the present invention Not limited to this.

In some embodiments, a deposition process, a lithography process, an etching process or other suitable processes may be used to form the first conductive pattern 111a on the first temporary carrier 10 . Next, a first dielectric layer 111b including a plurality of openings may be formed on the first temporary carrier 10 using, for example, a coating process, a photolithography etching process, or other suitable processes, wherein the openings expose at least a portion of the first conductive pattern 111a. part for electrical connections. Then, a conductive material may be formed within the opening of the first dielectric layer 111b to form the first conductive via 111c using a suitable deposition process. Then, the above steps are performed multiple times to form multiple first circuit layers 111 . Next, a suitable deposition process may be used to form the first microbumps 12a. It should be noted that the first group of circuit structures 110 shown in FIG. 1A is only exemplary, and more or fewer layers of the first circuit layer 111 may be formed according to circuit design requirements, as long as the first circuit layer 111 includes At least two layers belong to the protection scope of the present invention.

In some embodiments, the materials of the first conductive pattern 111a and the first conductive via 111c may include copper, gold, nickel, aluminum, platinum, tin, combinations thereof, alloys thereof, or other suitable conductive materials, and the first dielectric The material of the electrical layer 111b may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), inorganic dielectric materials (such as silicon oxide, nitride silicon, etc.) or other suitable electrical insulating materials, but the invention is not limited thereto.

Referring to FIG. 1B , a first connection bump 12b is formed on the first micro-bump 12a. When the material of the first micro-bump 12a is substantially the same as the material of the first connection bump 12b, the first micro-bump 12a There may be no substantial interface with the first connection bump 12b, but the present invention is not limited thereto. The material of the first micro-bump 12a and the first connection bump 12b may also be different. In addition, other film layers (such as a seed layer, not shown) may also be included between the first microbump 12a and the first circuit layer 111.

Referring to FIG. 1C and FIG. 1D, the first bonding dielectric material layer 12c is formed to cover the first micro-bump 12a and the first connection bump 12b. That is, the height of the first bonding dielectric material layer 12c will be higher than that of the first bonding dielectric material layer 12c. The stacking height of a micro-bump 12a and the first connection bump 12b. Then, a planarization process (such as a grinding process, a chemical mechanical polishing process or a combination thereof) is performed to form the first joining member 112a and the first joining dielectric layer 112b, wherein the first joining member 112a and the first joining dielectric layer 112b It can be regarded as the first bonding layer 112 . Furthermore, the grinding wheel 101 can be used to perform a planarization process (grinding and polishing) until the top surface of the first connecting bump 12b is exposed, and a coplanar top surface of the first joint member 112a and the first connecting block 12b are formed. Bonding dielectric layer 112b. Here, the multilayer first circuit layer 111 and the first bonding layer 112 can be regarded as the first group of circuit structures 110 .

In some embodiments, the first joint member 112a may be formed by sequentially stacking a seed layer of material such as titanium/copper (Ti/Cu) and an electroplating layer of material such as copper, but the invention is not limited thereto. In other embodiments, the first joint 112a may include other suitable conductive materials such as silver, gold, nickel or alloys thereof, for example, Cu, Cu/Ni/Au, Cu/Ti, Cu/Ag Or the like, and a second layer of material, such as titanium, can be formed on the first layer of material, such as copper, and then a material, such as silver, can be formed on the second layer by electroplating, sputtering or other suitable deposition methods. The third layer, wherein the thickness of the second layer may be smaller than the thickness of the third layer, but the invention is not limited thereto. In addition, the first connecting member 112a may be in the form of a pad or a conductive pillar.

In some embodiments, the first bonding dielectric layer 112b may be a two-stage curing material (such as polyimide). Therefore, at this stage, the aforementioned material may be semi-cured by controlling the curing temperature and/or process parameters. In this state, the first joining dielectric layer 112b may have a certain degree of elasticity and softness at this stage, but the present invention is not limited thereto, and the first joining dielectric layer 112b may also be directly cured.

In this embodiment, the first group of circuit structures 110 includes a first surface 110t and a second surface 110b opposite to each other, wherein the second surface 110b is close to the first temporary carrier 10, and the first conductive pattern at the second surface 110b 111a and first dielectric layer 111b may be substantially flush. In addition, the first conductive via 111 c gradually becomes thicker (eg, the width or diameter gradually becomes thicker) toward the plurality of first bonding layers 112 . In other words, the first conductive via 111 c becomes gradually thicker toward the first temporary carrier 10 gradually taper in the direction (such as the width or diameter gradually tapers), but the present invention is not limited thereto.

In some embodiments, the distribution density of the first conductive patterns 111a on the second surface 110b of the first group of circuit structures 110 must be sufficient for subsequent mounting of semiconductor chips, but the invention is not limited thereto.

Referring to FIG. 1E , multiple second circuit layers 121 are formed on the second temporary carrier 20 . In this embodiment, multiple second circuit layers 121 (six layers are schematically shown in FIG. 1E) and second micro-bumps 22a located on the second circuit layer 121 (referred to below) can be formed on the second temporary carrier 20. After forming the second joint member 122a) as shown in FIG. 1H, each second circuit layer 121 may include a second conductive pattern 121a, a second dielectric layer 121b and/or a second conductive via 121c. Here, the second conductive patterns 121a and the second conductive vias 121c may be embedded in the second dielectric layer 121b, and the second microbumps 22a may be electrically connected to the second circuit layer 121. However, the present invention Not limited to this.

Referring to FIG. 1F, a second connection bump 22b is formed on the second micro-bump 22a. Other film layers (such as a seed layer, not shown) may also be included between the second micro-bump 22a and the second circuit layer 121. Show). Here, the second micro-bumps 22a and the second connection bumps 22b are similar to the materials of the first micro-bumps 12a and the first connection bumps 12b, and will not be described again.

Referring to FIG. 1G and FIG. 1H, the second bonding dielectric material layer 22c is formed to cover the second micro-bump 22a and the second connection bump 22b. That is, the height of the second bonding dielectric material layer 22c will be higher than the second bonding dielectric material layer 22c. The stacking height of the two micro-bumps 22a and the second connection bumps 22b. Then, a planarization process (such as a grinding process, a chemical mechanical polishing process or a combination thereof) is performed to form the second joining member 122a and the second joining dielectric layer 122b, wherein the second joining member 122a and the second joining dielectric layer 122b It can be regarded as the second bonding layer 122 . Furthermore, a planarization process (grinding and polishing) can be performed by using the grinding wheel 101 until the top surface of the second connection bump 22b is exposed, and the second joint member 122a and the second joint dielectric are formed with coplanar top surfaces. Layer 122b. Here, the multiple second circuit layers 121 and the second bonding layer 122 can be regarded as the second group of circuit structures 120 .

In this embodiment, the second group of circuit structures 120 includes a third surface 120t and a fourth surface 120b opposite to each other, wherein the fourth surface 120b is close to the second temporary carrier 20, and the second conductive pattern at the fourth surface 120b 121a and the second dielectric layer 121b may be substantially flush. In addition, the second conductive via 121 c gradually becomes thicker (eg, the width or diameter gradually becomes thicker) toward the plurality of second bonding layers 122 . In other words, the second conductive via 121 c becomes gradually thicker toward the second temporary carrier 20 gradually taper in the direction (such as the width or diameter gradually tapers), but the present invention is not limited thereto.

In some embodiments, the first conductive pattern 121a on the fourth surface 120b of the second group of circuit structures 120 may be used for subsequent mounting of a substrate or an external terminal, but the invention is not limited thereto.

In some embodiments, the dielectric layers of the first group of circuit structures 110 (such as the first dielectric layer 111b and the first bonding dielectric layer 112b) and the dielectric layers of the second group of circuit structures 120 (such as the second dielectric layer The layer 121b and the second bonding dielectric layer 122b) are organic thin films, but the invention is not limited thereto.

In some embodiments, the material of the dielectric layer of the first set of circuit structures 110 (such as the first dielectric layer 111b and the first bonding dielectric layer 112b) is different from the material of the dielectric layer of the second set of circuit structures 120 (such as the second The dielectric layer 121b and the second bonding dielectric layer 122b are made of the same material (for example, the dielectric (material) thermal expansion coefficient is the same), but the invention is not limited thereto. In other embodiments, the first group of circuit structures 110 The material of the dielectric layer (such as the first dielectric layer 111b and the first bonding dielectric layer 112b) and the dielectric layer (such as the second dielectric layer 121b and the second bonding dielectric layer 122b) of the second set of circuit structures 120 The materials may be different (for example, the dielectric thermal expansion coefficients are different), and the difference may include being similar but not exactly the same.

In some embodiments, the dielectric thermal expansion coefficient of the dielectric layer of the first set of circuit structures 110 (such as the first dielectric layer 111b and the first bonding dielectric layer 112b) is the same as the dielectric thermal expansion coefficient of the dielectric layer of the second set of circuit structures 120 (such as the first dielectric layer 111b and the first bonding dielectric layer 112b). For example, the difference between the dielectric thermal expansion coefficients of the second dielectric layer 121b and the second bonding dielectric layer 122b) may be less than 10%, but the present invention is not limited thereto.

It should be noted that other specific details of forming the second group of circuit structures 120 (such as materials, formation methods, and arrangement of the second release layer 22) are similar to forming the first group of circuit structures 110, and will not be described again here.

Referring to FIG. 1I , the structure shown in FIG. 1D is flipped upside down, and the first group of circuit structures 110 and the second group of circuit structures 120 are directly connected, so that the first bonding layer 112 is bonded to the second bonding layer. Layer 122 constitutes a multi-layer redistribution structure RDL. Through the above fabrication, the semiconductor substrate structure 100 of this embodiment has been substantially completed. The semiconductor substrate structure 100 of this embodiment includes a first group of circuit structures 110 and a second group of circuit structures 120 . The first group of circuit structures 110 includes multiple layers of first circuit layers 111 and first bonding layers 112 . The second group of circuit structures 120 includes multiple layers of second circuit layers 121 and second bonding layers 122 . The second group of circuit structures 120 is disposed on the first group of circuit structures 110 and is electrically connected to the first group of circuit structures 110 . The first bonding layer 112 is bonded to the second bonding layer 122 to form a multi-layer redistribution structure RDL. According to this, in this embodiment, multiple groups of circuit structures (the first group of circuit structures 110 and the second group of circuit structures 120) are first separated. It is made on a temporary carrier (the first temporary carrier 10 and the second temporary carrier 20), and then multiple sets of circuit structures are directly joined and assembled into a multi-layer rewiring structure (multi-layer rewiring structure RDL). In this way, compared with a disposable Continuously manufacturing a multi-layer redistribution structure can effectively reduce the degree of warpage, so that the semiconductor substrate structure 100 can maintain better yield and electrical performance while having a multi-layer redistribution structure RDL.

Furthermore, due to process limitations, the difficulty is positively correlated with the number of layers to be produced. Therefore, when more layers are produced, the probability of the entire rewiring structure being damaged during the manufacturing process is higher, making it impossible to effectively control To solve the problem of yield and cost, this embodiment splits the multi-layer rewiring structure RDL into multiple groups of circuit structures with a smaller number of layers and fabricates them separately. Therefore, it can avoid the problem of continuously stacking multiple layers and being unable to effectively control the yield and cost. , but the present invention is not limited to this.

In some embodiments, warping will occur due to differences in coefficients of thermal expansion (CTE), and the situation will become more severe as more layers are stacked. Therefore, when a multi-layer rewiring structure is continuously fabricated at one time, warping will occur. The amplitude will accumulate and become larger and larger. As shown in Figure 1R, a multi-layer rewiring structure 2 is formed on the temporary carrier 1. In this embodiment, the multi-layer rewiring structure RDL is divided into multiple groups of line structures (the first group After the circuit structure 110 and the second group of circuit structures 120) are made separately, one group is turned up and down for jointing (the joint plane can be made horizontal by up and down pressure later). In this way, through the up and down warping Different directions can effectively offset the stress and thereby slow down the warping phenomenon, as shown in Figure 1P and Figure 1Q. It should be noted that in FIG. 1Q , the first temporary carrier 10 is omitted for simplicity and simplicity, and the degree of warpage in FIGS. 1P to 1R is only for illustrative purposes and is not intended to limit the present invention. The actual degree of warpage depends on the actual process conditions.

In some embodiments, direct bonding may be performed through a Cu to Cu hybrid bonding process or a Cu to Cu direct bonding process, so that the plurality of first bonding members 112 a and The plurality of second joining members 122a are in direct contact, and the first joining dielectric layer 112b is in direct contact with the second joining dielectric layer 122b, where the first joining members 112a and the second joining members 122a may be joined in a one-to-one manner, For example, the first joining member 112a is substantially aligned with the second joining member 122a. However, due to the design of process conditions, the first joining member 112a may also be substantially partially staggered with the second joining member 122a. Here, since no solder material is used for bonding between the first bonding layer 112 and the second bonding layer 122, the connection of the multi-layer redistribution structure RDL can be regarded as a solderless connection.

In some embodiments, when the line length/spacing (L/S) (such as line width) of the lines becomes thinner, the process requirements will be more stringent, so forming a multi-layer heavy wiring structure will encounter more difficulties. , and this embodiment uses the method of joining and assembling multiple sets of circuit structures to produce a fine pitch/spacing structure, which can have greater advantages in yield and electrical performance than a continuously formed structure. For example, the first set of circuits The structure 110 and the second group of circuit structures 120 can each have a fine line pitch/spacing of at least less than 10 microns. Therefore, the first group of circuit structures 110 and the second group of circuit structures 120 can be multi-layered with fine line pitch/spacing after being directly assembled. Rewiring structure RDL, but the invention is not limited thereto.

In some embodiments, as shown in Figure 1I, each first circuit layer 111 includes two adjacent first circuits, and there is a first spacing 111s between the center points of the two adjacent first circuits. The second circuit layer 121 includes two adjacent second circuits. There is a second spacing 121s between the center points of the two adjacent second circuits. The first spacing 111s of each first circuit layer 111 is smaller than that of each second circuit. The second spacing 121s of the second circuit layer 121, and the spacing between each layer gradually becomes larger from the first group of circuit structures 110 toward the second group of circuit structures 120, for example, from the second surface 110b of the first group of circuit structures 110 toward the second group. The direction of the fourth surface 120b of the circuit structure 120 passes through the first surface 110t of the first group of circuit structures 110 and the third surface 120t of the second group of circuit structures 120, wherein the first surface 110t is joined to the third surface 120t. Here, the first spacing 111s and the second spacing 121s are the minimum spacing of each layer, but the invention is not limited thereto. In other embodiments, the first spacing 111s and the second spacing 121s can be the average spacing of each layer.

4A is a partially schematic cross-sectional view showing the pitch of the line structure. Fig. 4B is a partial schematic top view corresponding to Fig. 4A. Furthermore, as shown in FIGS. 4A and 4B , the line layer may have fine pitch F and coarse pitch C, and the pitch may be, for example, the distance between the center points of two adjacent lines, such as two adjacent lines. The distance between the center points of a line L1 is a fine pitch F, and the distance between the center points of two adjacent lines L2 is a coarse pitch C, or the distance between two adjacent pads, such as The distance between the center points of two adjacent pads P1 is the fine pitch F, and the distance between the center points of the two adjacent pads P2 is the coarse pitch C. Therefore, the aforementioned first pitch 111s and the second pitch 121s These designs can be used according to actual design requirements and are not limited by the present invention.

In some embodiments, when the first bonding dielectric layer 112b and the second bonding dielectric layer 122b are made of a two-stage curing material (such as polyimide), during the foregoing bonding process, the first bonding layer 112 and the second bonding dielectric layer 122b are made of a two-stage curing material. The second bonding layer 122 applies heat and/or force. For example, the bonding interface of the first bonding layer 112 and the second bonding layer 122 can be applied with a glass transition temperature greater than the glass transition temperature of the first bonding layer 112 and the second bonding layer 122 ( Tg), so the first bonding dielectric layer 112b and the second bonding dielectric layer 122b will change from a semi-solidified state to a solidified state at this stage, so the bonding between the first bonding layer 112 and the second bonding layer 122 can be enhanced. force, but the invention is not limited thereto.

In some embodiments, the material of the first bonding dielectric layer 112b and the second bonding dielectric layer 122b may be the same, so there is substantially no gap between the first bonding dielectric layer 112b and the second bonding dielectric layer 122b. It will be observed that there is an interface, but the invention is not limited thereto.

In some embodiments, the first conductive via 111 c gradually becomes thicker (eg, the width or diameter gradually becomes thicker) in the direction toward the first bonding layer 112 , and the second conductive via 112 c becomes gradually thicker in the direction toward the second bonding layer 122 gradually becomes thicker (such as the width or diameter gradually becomes thicker), in other words, the first conductive via hole 111c gradually becomes thinner (such as the width or diameter gradually becomes smaller) toward the first temporary carrier 10, and the second conductive via hole 111c gradually becomes thinner (such as the width or diameter gradually becomes smaller), and the second conductive via hole 111c The hole 112c is gradually tapered (such as the width or diameter is gradually tapered) toward the second temporary carrier 20. That is to say, after the bonding process, the tapering direction of the first conductive via hole 111c is consistent with the direction of the second conductive via hole. 112c tapers in the opposite direction.

It should be noted that, according to actual application requirements, the first temporary carrier 10 and/or the second temporary carrier 20 can be optionally removed to expose the first conductive pattern 111a and/or the second conductive pattern 121a and connect them to Other components are electrically connected. Here, the release layer can be peeled off by applying external energy between the bottom surface of the circuit structure and the temporary carrier.

Referring to FIGS. 1J to 1L , in alternative embodiments, the first bonding layer 112 may use other manufacturing methods. First, the first photosensitive dielectric layer 12d can be formed on the multi-layer first circuit layer 111. Next, the first photosensitive dielectric layer 12d is patterned using a lithographic tool, such as a stepper, and the first photosensitive dielectric layer 12d is cured to form a third exposed layer below. A plurality of openings 12e of the circuit layer 111 are shown in Figure 1J. Next, a first seed layer 12f is formed to cover the patterned first photosensitive dielectric layer 12d, and part of the first seed layer 12f is filled in the plurality of openings 12e, as shown in FIG. 1K. Then, an electroplating process is performed to form the first metal layer 12g, and a planarization process is performed using the grinding wheel 101 to form the first joining member 112a and the first joining dielectric layer 112b with coplanar top surfaces, as shown in FIG. 1L and As shown in Figure 1D. It should be noted that, for the sake of simplicity, it is not shown here. The second bonding layer 122 can be formed using a manufacturing method similar to the above, for example, forming a second photosensitive dielectric layer on the multi-layer second circuit layer 122. The second photosensitive dielectric layer is patterned and cured to form a plurality of openings exposing the underlying second circuit layer 122, and a second seed layer is formed to cover the patterned The second photosensitive dielectric layer is filled with part of the second seed layer into the plurality of openings, an electroplating process is performed to form a second metal layer, and a planarization process is performed using the grinding wheel 101 to form the top surface. The coplanar second bonding member 122a and the second bonding dielectric layer 122b.

In some embodiments, the material of the first seed layer 12f is, for example, Ti (thickness is, for example, 0.1 micron)/Cu (thickness is, for example, 0.3 micron), and the material of the first metal layer 12g is, for example, Cu. However, the present invention does not Limited to this.

In some embodiments, the number of circuit structure groups is not limited to two groups. For example, the multi-layer redistribution structure RDL1 of the semiconductor substrate structure 100A shown in FIG. 1M may further include a third group of circuit structures 130, where The third group of circuit structures 130 includes multiple third circuit layers 131 and third bonding layers 132 . Furthermore, the second group of circuit structures 120 is disposed between the first group of circuit structures 110 and the third group of circuit structures 130 and is electrically connected to each other. The second group of circuit structures 120 has another structure relative to the first group of circuit structures. One bonding layer 123, and the other bonding layer 123 is bonded to the third bonding layer 132, but the invention is not limited thereto. In addition, the third group of circuit structures 110 includes fifth and sixth surfaces 130t and 130b opposite to each other.

In addition, the semiconductor substrate structure 100A may continue with FIG. 1H , remove the second temporary carrier 20 and the second release layer 22 , and join the third temporary carrier 30 and the third release layer 32 on the second set of circuit structures 110 The third group of line structures 130 is used to form a multi-layer redistribution structure RDL1, but the invention is not limited thereto.

In some embodiments, the number of the first circuit layers 111 of the first group of circuit structures 110 (six-layer structure) is the same as the number of the second circuit layers 121 of the second group of circuit structures 120 (six-layer structure), but they may also be There are different implementation aspects. For example, in the semiconductor substrate structure 100A shown in FIG. 1M, the number of the first circuit layers 111 of the first group of circuit structures 110 and the number of the second circuit layers 121 of the second group of circuit structures 120. Different from the number of the third group of line structures 130 (five-layer structure), the aforementioned number difference may be one layer or two layers, but the invention is not limited thereto.

In some embodiments, the thickness of the first circuit layer 111 of the first group of circuit structures 110 (six-layer structure) is the same as the thickness of the second circuit layer 121 of the second group of circuit structures 120 (six-layer structure), but they may also be There are different implementation aspects. For example, in the semiconductor substrate structure 100B shown in FIG. 1N , the thickness of the first circuit layer 111 of the first group of circuit structures 110 and the thickness of the second circuit layer 121 of the second group of circuit structures 120 Different from the thickness of the third group of circuit structures 130B, where the thickness of the third group of circuit structures 130B may be twice the thickness of the first circuit layer 111 or the thickness of the second circuit layer 121 of the second group of circuit structures 120, to form Multi-layer redistribution structure RDL2. In addition, in this embodiment, the second group of circuit structures 120 and the third group of circuit structures 130B are bonded using a copper-to-copper hybrid bonding process or a copper-to-copper direct bonding process. However, the invention is not limited thereto. , in other embodiments, as shown in FIG. 1O in the semiconductor substrate structure 100C, the second group of circuit structures 120 and the third group of circuit structures 130B can be joined using solders 124 and 134 to form a multi-layer redistribution structure RDL3, However, the present invention is not limited to this.

In some embodiments, as shown in Figure 1M and Figure 1N, each third circuit layer 131 of the third group of circuit structures includes two adjacent third circuits, and the center point of the two adjacent third circuits is between There is a third spacing 131s between them, the third spacing 131s is larger than the first spacing 111s and the second spacing 121s, and the spacing between each layer gradually becomes larger from the first group of circuit structures 110 to the third group of circuit structures 130, for example, from the first group of circuit structures 110 to the third group of circuit structures 130. The second surface 110b of the structure 110 faces the direction of the sixth surface 130b of the third group of circuit structures 130 and passes through the first surface 110t of the first group of circuit structures 110, the third surface 120t of the second group of circuit structures 120, and the second surface 110b of the second group of circuit structures 120. The fourth surface 120b of the set of circuit structures 120 and the fifth surface 130t of the third set of circuit structures 130, wherein the fourth surface 120b is joined to the fifth surface 130t. In addition, the coefficient of dielectric thermal expansion (CTE) of the third bonding layer 132 is smaller than the coefficient of dielectric thermal expansion of the first bonding layer 112 and the coefficient of dielectric thermal expansion of the second bonding layer 122 , but the invention is not limited thereto.

It must be noted here that the following embodiments follow the component numbers and part of the content of the above embodiments, where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. Regarding the description of the omitted parts Reference may be made to the foregoing embodiments, and details will not be repeated in the following embodiments.

2A to 2D are partially schematic cross-sectional views illustrating a method of manufacturing a semiconductor structure according to further embodiments of the present invention. Figure 2E is a partial fabrication flow diagram illustrating a semiconductor structure in accordance with some embodiments of the invention. 2F is a partially schematic cross-sectional view illustrating a semiconductor structure in accordance with some embodiments of the invention. Please refer to Figure 2A and Figure 2E. Following the assembly of the first set of circuit structures and the second set of circuit structures in Figure 1E (step S110), the first temporary carrier is removed through the first release layer (step S120), for example The manufacturing method of the semiconductor substrate structure can further remove the first release layer 12 and the first temporary carrier 10 (for example, by a laser process), and can remove the remaining first release layer 12 by a plasma process. layer 12) to expose the first conductive pattern 111a and the first dielectric layer 111b on the second surface 110b of the first set of circuit structures 110 (which can be regarded as the chip end of the multi-layer redistribution structure RDL). Next, after the first temporary carrier 10 is removed, a plurality of conductive connectors are formed on the first set of circuit structures (step S130). For example, a plurality of conductive connections can be formed on the first surface of the second surface 110b of the first set of circuit structures 110. A plurality of conductive connectors 240 are formed on the conductive pattern 111a, where the conductive connectors 240 include conductive pillars 241 and conductive caps 242 formed thereon. Here, the conductive pillars 241 can be made of copper, and the conductive cover 242 can be made of solder, but the present invention is not limited thereto. The conductive pillars 241 and the conductive cover 242 can also be made of other suitable materials. For example, the conductive cover 242 may be Sn/Ag lead-free solder. Through the above-mentioned fabrication, another semiconductor substrate structure for electrically connecting the semiconductor chip and the external terminal can be completed, but the invention is not limited thereto.

In some embodiments, adjacent conductive connections 240 may have a fine pitch to correspond to the wafer to be subsequently mounted, but the invention is not limited thereto.

Referring to FIGS. 2B and 2E , the semiconductor chip is bonded to the semiconductor substrate structure (step S140 ). For example, the semiconductor chip 301 may be connected to the second surface 110 b of the first set of circuit structures 110 using flip-chip bonding. For example, the conductive bumps 302 of the semiconductor wafer 301 (which may further include solder) may be bonded to the conductive cover 242 of the conductive connector 240. In other words, the conductive bumps 302 of the semiconductor wafer 301 may be connected to the conductive connector 240. The conductive cover 242 is in direct contact to form a heterogeneous integration module or system. Furthermore, the semiconductor chip 301 can be bonded to the second set of circuit structures 120 through a thermal compression bonding process.

In some embodiments, the semiconductor chip 301 is, for example, a logic chip, a memory chip, a three-dimensional integrated circuit (3DIC) chip (such as a high bandwidth memory chip), and/or Similarly, the 3DIC chip includes multiple layers stacked on each other, and through-silicon vias (TSVs) are formed to provide vertical electrical connections between the layers, but the invention is not limited thereto.

In some embodiments, the height 302h of the conductive bump 302 may be greater than the height 240h of the corresponding conductive connector 240, but the invention is not limited thereto. The height 302h of the conductive bump 302 and the height 240h of the conductive connector 240 may be determined according to actual conditions. Depends on design needs.

In some embodiments, an underfill is formed on the semiconductor substrate structure (step S150). For example, an underfill 40 can be formed on the second surface 110b of the first group of circuit structures 110 to fill the second surface. 110b and the semiconductor wafer 301, thereby enhancing the reliability of flip-chip bonding. In some embodiments, more than one semiconductor die 301 performing the same or different functions may be disposed on the first set of circuit structures 110 . In this case, the plurality of semiconductor chips 301 may be electrically connected to the first set of circuit structures 110 and to each other through the first set of circuit structures 110 . The number of semiconductor wafers 301 disposed on the first set of circuit structures 110 does not constitute a limitation of the present disclosure.

Please refer to FIG. 2C and FIG. 2E to encapsulate the semiconductor substrate structure and the semiconductor chip (step S160). For example, a sealing body 250 is formed on the second surface 110b of the first group of circuit structures 110 to encapsulate the semiconductor chip 301 and the semiconductor chip. The sealant 250 of the primer 40 may be a molding compound formed by a molding process. Here, the sealing body 250 may be formed of an insulating material such as epoxy resin or other suitable resin, but the present invention is not limited thereto.

Referring to FIG. 2D and FIG. 2E, the second release layer and the second temporary carrier are removed (step S170). For example, the second release layer 22 and the second temporary carrier 20 are removed to expose the second set of The second conductive pattern 121a and the second dielectric layer 121b of the fourth surface 120b of the circuit structure 120 (can be regarded as the terminal ends of the multi-layer redistribution structure RDL). Then, external terminals are formed on the second set of circuit structures (step S180). For example, bottom connection pads can be formed by metallization on the second conductive pattern 121a, and solder can be formed on the bottom connection pads to form multi-layer layers. A plurality of external terminals 260 are formed on the terminal end of the wiring structure RDL, in which the second group of circuit structures 120 is disposed between the external terminals 260 and the first group of circuit structures 110, and the external terminals 260 are electrically connected to the second group of circuit structures 120. . Through the above fabrication, the semiconductor structure 200 of this embodiment has been substantially completed.

In some embodiments, as shown in FIG. 2F , after removing the second release layer 22 and the second temporary carrier 20 , a third set of circuit structures 130 can be further formed, and then external terminals are formed on the third set of circuit structures 130 Above, the semiconductor structure 200A is completed, in which the material details and formation method of the third group of circuit structures 130 are similar to those described in FIG. 1M and FIG. 2D and will not be described again here.

In some embodiments, the external terminal 260 may be a solder ball and may be formed using a ball placement process to be placed on the second conductive pattern 121a of the second set of circuit structures 120, and a soldering process and reflow may be selectively performed ( reflow) process to enhance the adhesion between the external terminal 260 and the second conductive pattern 121a, but the invention is not limited thereto.

In embodiments not shown, the semiconductor structure 200 may be further disposed on a circuit carrier (such as a printed circuit board (PCB), a system board, a motherboard, etc.), a package, and/or other components to form an electronic device. For example, the external terminal 260 is provided on the circuit carrier, and the semiconductor chip 301 is electrically connected to the circuit carrier or other components in the circuit carrier through the multi-layer redistribution structure RDL, but the invention is not limited thereto.

In some embodiments, the semiconductor structure 200 is a wafer level semiconductor packaging structure, but the invention is not limited thereto.

3A is a partially schematic cross-sectional view illustrating a semiconductor structure according to further embodiments of the present invention. 3B and 3C are partial schematic cross-sectional views showing some specific implementation aspects of the connection layer of FIG. 3A. Please refer to FIG. 3A. Compared with the semiconductor structure 200 of FIG. 2D, the semiconductor structure 300 of this embodiment further includes a connection layer 370 and a substrate 380 between the multi-layer redistribution structure RDL and the external terminal 260. The multi-layer redistribution structure RDL The RDL is coupled to the substrate 380 through the connection layer 370 (the multilayer redistribution structure RDL and the substrate 380 may be collectively referred to as a 2.2D integrated substrate), and the substrate 380 may be a ceramic substrate, a laminated organic substrate, a packaging substrate, an integrated substrate, or other Similar.

In some embodiments, the connection layer 370 may be connected to other components using solder. For example, as shown in FIG. 3B , the connection layer 370 may include copper pads 371 (which may also be in direct contact with the multi-layer redistribution structure RDL). copper pillars), copper pads 372 in direct contact with the substrate 380, and solder 373 disposed between the copper pads 371 and 372, where the surface of the copper pads 372 may be composed of Cu/Ni/Au and also It can be surrounded by solder mask ink 374 to improve electrical performance, but the invention is not limited thereto. Solderless connections can also be used between the connection layer 370 and other components. For example, as shown in FIG. 3C , the connection layer 370 The connection method is, for example, a hybrid bonding process or a copper-to-copper direct bonding process. The connection layer 370 may include a copper pad 371 in direct contact with the multi-layer redistribution structure RDL and a copper pad 372 in direct contact with the substrate 380, and the copper pads 371 and the copper pad 372 may be in direct contact and joined together, but the invention is not limited thereto.

In some embodiments, the substrate 380 includes a core layer 381, a build-up structure 382 and a plurality of through holes 381a, wherein the build-up structures 382 are respectively formed on two sides of the build-up structure 382, and the plurality of through holes 381a penetrate the core. The layer 381 is electrically connected to the build-up structures 382 on both sides. The build-up structure 382 includes a conductive pattern 382a embedded in the dielectric layer. However, the present invention is not limited thereto. In an embodiment not shown, the substrate 380 The core layer 381 may not be provided.

Figure 5A is a partial manufacturing flow diagram illustrating a semiconductor substrate structure in accordance with some embodiments of the invention. Figure 5B is a partially schematic cross-sectional view illustrating a semiconductor substrate structure according to some embodiments of the present invention. Please refer to Figure 2A, Figure 2F, Figure 5A and Figure 5B. The semiconductor substrate structure 100D of this embodiment can have different manufacturing methods. The steps include: providing a second group of circuit structures disposed on a second temporary carrier, and bonding The third group of circuit structures and the second group of circuit structures (step S210); remove the second temporary carrier (step S220); join the first group of circuit structures provided on the first temporary carrier to the second group of circuit structures (step S220); S230); remove the first temporary carrier (step S240); form conductive pillars and conductive covers on the surface of the first group of circuit structures, and form external terminals on the surface of the third group of circuit structures (step 250). Through the above fabrication, the semiconductor structure 100D of this embodiment has been substantially completed.

In this embodiment, the manufacturing method of the semiconductor structure 100D can also correspond to the following steps: forming a second group of circuit structures on the second temporary carrier; forming a third group of circuit structures on the second group of circuit structures; bonding the second group of circuit structures. A set of line structures and a third set of line structures; removing the second temporary carrier; forming the first set of line structures on the first temporary carrier; directly joining the first set of line structures and the second set of line structures; removing the first temporary carrier ; Form conductive pillars and conductive covers on the surface of the first group of circuit structures, and form external terminals on the surface of the third group of circuit structures.

In this embodiment, the semiconductor structure 100D includes a multi-layer redistribution structure RDL1 composed of a first group of circuit structures 110, a second group of circuit structures 120, and a third group of circuit structures 130, and the second group of the first group of circuit structures 110 Conductive pillars 241 and conductive covers 242 are formed on the surface 110b, and external terminals 260 are formed on the sixth surface 130b of the third group of circuit structures 130. The third group of circuit structures 130 are not placed on a temporary carrier during the manufacturing process. It has a supportive plate-like structure, but the invention is not limited thereto. Here, the same or similar reference numerals are used to represent the same or similar components. Therefore, please refer to the above-mentioned embodiments for details and will not be repeated here.

It should be noted that the above various embodiments can be combined in different ways, and this is not a limitation of this case. As long as multiple sets of circuit structures are separately produced separately and then joined and assembled into a multi-layer rewiring structure, they all belong to the present invention. scope of protection. In addition, the temporary carrier (such as the first temporary carrier, the second temporary carrier, the third temporary carrier or other temporary carriers used in the manufacturing process) will not become part of the final structure.

To sum up, the present invention first manufactures multiple sets of circuit structures separately on temporary carriers, and then joins and assembles the aforementioned multiple sets of circuit structures into a multi-layer rewiring structure. In this way, compared with the multi-layer rewiring structure produced continuously at one time, As for the wiring structure, the degree of warpage can be effectively reduced, so that the semiconductor substrate structure can maintain better yield and electrical performance while having a multi-layer rewiring structure.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

1, 10, 20, 30: temporary carrier 12, 22: Release layer 12a, 22a: micro bumps 12b, 22b: connecting bumps 12c, 22c: Joining dielectric material layer 12d: Photosensitive dielectric layer 12e:Open your mouth 12f: seed layer 12g: metal layer 302h, 240h: height 40: Bottom glue 100, 100A, 100B, 100C, 100D: Semiconductor substrate structure 101:Grinder wheel 110, 120, 120A, 130: Line structure 110t, 120t, 130t, 110b, 120b, 130b: surface 111, 121, 131: line layer 111a, 121a, 382a: conductive pattern 111b, 121b: dielectric layer 111c, 121c: Conductive vias 111s, 121s, 131s, F, C: spacing 112, 122, 132, 113: Bonding layer 112a, 122a: joints 112b, 122b: bonding dielectric layer 200, 200A, 300: Semiconductor structure 240: Conductive connectors 241:Conductive pillar 242: Conductive cover 250:Sealed body 260:External terminal 301:Semiconductor wafer 302: Conductive bumps 370: Connection layer 371, 372: Copper pad 124, 134, 373: solder 374: Solder mask ink 380:Substrate 381:Core layer 381a: perforation 382:Added layer structure L1, L2: Line P1, P2: pads 2. RDL, RDL1, RDL2, RDL3: multi-layer rewiring structure S110, S120, S130, S140, S150, S160, S170, S180, S190: Steps

1A to 1I are partially schematic cross-sectional views illustrating a method of manufacturing a semiconductor substrate structure according to some embodiments of the present invention. 1J, 1K, and 1L are partially schematic cross-sectional views illustrating a method of manufacturing an alternative embodiment of the first set of circuit structures of FIG. 1D. 1M, 1N, and 1O are partial schematic cross-sectional views showing the structure of a semiconductor substrate according to other embodiments of the present invention. FIG. 1P is a schematic diagram illustrating semiconductor substrate structures when bonded according to some embodiments of the present invention. 1Q is a schematic diagram illustrating a semiconductor substrate structure after bonding according to some embodiments of the invention. FIG. 1R is a schematic diagram showing a conventional semiconductor substrate structure after bonding. 2A to 2D are partially schematic cross-sectional views illustrating a method of manufacturing a semiconductor structure according to further embodiments of the present invention. Figure 2E is a partial fabrication flow diagram illustrating a semiconductor structure in accordance with some embodiments of the invention. 2F is a partially schematic cross-sectional view illustrating a semiconductor structure in accordance with some embodiments of the invention. 3A is a partially schematic cross-sectional view illustrating a semiconductor structure according to further embodiments of the present invention. 3B and 3C are partial schematic cross-sectional views showing some specific implementation aspects of the connection layer of FIG. 3A. 4A is a partially schematic cross-sectional view showing the pitch of the line structure. Fig. 4B is a partial schematic top view corresponding to Fig. 4A. Figure 5A is a partial manufacturing flow diagram illustrating a semiconductor substrate structure in accordance with some embodiments of the invention. Figure 5B is a partially schematic cross-sectional view illustrating a semiconductor substrate structure according to some embodiments of the present invention. It should be noted that FIG. 3B and FIG. 3C may be the enlarged portion of the dotted frame in FIG. 3A .

10, 20: Temporary carrier

12, 22: Release layer

100:Semiconductor substrate structure

110, 120: Line structure

110b, 120b: surface

112, 122: joint layer

112a, 122a: joints

112b, 122b: bonding dielectric layer

111s, 121s: spacing

RDL: multi-layer rewiring structure

Claims (48)

A semiconductor substrate structure including: A first set of circuit structures includes a plurality of first circuit layers and a first bonding layer; and The second set of circuit structures includes a plurality of second circuit layers and a second bonding layer, wherein the second set of circuit structures are disposed on the first set of circuit structures and are electrically connected to the first set of circuit structures, and The first bonding layer is bonded to the second bonding layer to form a multi-layer redistribution structure. The semiconductor substrate structure of claim 1, wherein the first bonding layer includes a plurality of first bonding members and a first bonding dielectric layer, and the second bonding layer includes a plurality of second bonding members and a second A bonding dielectric layer, the plurality of first bonding members are in direct contact with the plurality of second bonding members, and the first bonding dielectric layer is in direct contact with the second bonding dielectric layer. The semiconductor substrate structure according to claim 1, wherein the dielectric layer in the first group of circuit structures and the dielectric layer in the second group of circuit structures are organic films. The semiconductor substrate structure according to claim 1, wherein the material of the dielectric layer in the first group of circuit structures is the same as the material of the dielectric layer in the second group of circuit structures. The semiconductor substrate structure of claim 1, wherein the material of the dielectric layer in the first group of circuit structures is different from the material of the dielectric layer in the second group of circuit structures. The semiconductor substrate structure according to claim 1, wherein each first circuit layer includes two adjacent first circuits, and there is a first spacing between the center points of the two adjacent first circuits, Each second circuit layer includes two adjacent second circuits, and there is a second spacing between the center points of the two adjacent second circuits. The first circuit layer of each first circuit layer A pitch is smaller than the second pitch of each second circuit layer, and the first group of circuit structures includes an opposing first surface and a second surface, and the second group of circuit structures includes an opposing third surface. surface and the fourth surface, the first surface is joined to the third surface, and each layer spacing is in a direction from the second surface toward the fourth surface and passes through the first surface and the third surface. The semiconductor substrate structure according to claim 3, wherein the first pitch and the second pitch are the minimum pitch of each layer. The semiconductor substrate structure according to claim 1, wherein the number of the first circuit layers of the first group of circuit structures is the same as the number of the second circuit layers of the second group of circuit structures. The semiconductor substrate structure according to claim 1, wherein the number of the first circuit layers of the first group of circuit structures is different from the number of the second circuit layers of the second group of circuit structures. The semiconductor substrate structure according to claim 9, wherein the difference in quantity between the number of the first circuit layers of the first group of circuit structures and the number of the second circuit layers of the second group of circuit structures is one layer Or two layers. A semiconductor substrate structure including: The first group of circuit structures includes multiple first circuit layers and first bonding layers; The second set of circuit structures includes a plurality of second circuit layers and a second bonding layer, wherein the second set of circuit structures are disposed on the first set of circuit structures and are electrically connected to the first set of circuit structures, and the first bonding layer is bonded to the second bonding layer; and The third group of circuit structures includes a multi-layer third circuit layer and a third bonding layer, wherein the second group of circuit structures are disposed between the first group of circuit structures and the third group of circuit structures and are electrically interconnected with each other. Connecting, the second group of circuit structures has another bonding layer relative to the first group of circuit structures, and the other bonding layer is bonded to the third bonding layer to form a multi-layer redistribution structure. The semiconductor substrate structure according to claim 11, wherein the dielectric layer in the first group of circuit structures and the dielectric layer in the second group of circuit structures are organic films. The semiconductor substrate structure of claim 11, wherein the material of the dielectric layer in the first group of circuit structures is the same as the material of the dielectric layer in the second group of circuit structures. The semiconductor substrate structure of claim 11, wherein the material of the dielectric layer in the first group of circuit structures is different from the material of the dielectric layer in the second group of circuit structures. The semiconductor substrate structure according to claim 11, wherein the number of the first circuit layers of the first group of circuit structures is the same as the number of the second circuit layers of the second group of circuit structures. The semiconductor substrate structure according to claim 11, wherein the number of the first circuit layers of the first group of circuit structures is different from the number of the second circuit layers of the second group of circuit structures. The semiconductor substrate structure according to claim 16, wherein the difference between the number of the first circuit layers of the first group of circuit structures and the number of the second circuit layers of the second group of circuit structures is one layer Or two layers. The semiconductor substrate structure according to claim 11, wherein the thickness of the third group of circuit structures is greater than the thickness of the first group of circuit structures and the thickness of the second group of circuit structures, and the third group of circuit structures includes There are multiple third circuit layers and third bonding layers, each of the first circuit layers includes two adjacent first circuits, and there is a first spacing between the center points of the two adjacent first circuits. One of the second circuit layers includes two adjacent second circuits, and there is a second spacing between the center points of the two adjacent second circuits. Each of the third circuit layers includes two adjacent second circuits. a third line, there is a third spacing between the center points of the two adjacent third lines, the third spacing is greater than the first spacing and the second spacing, the first group of circuit structures It includes an opposing first surface and a second surface, the second group of circuit structures includes an opposing third surface and a fourth surface, the third group of circuit structures includes an opposing fifth surface and a sixth surface, and the A surface is bonded to the third surface, the fourth surface is bonded to the fifth surface, and is directed from the second surface toward the sixth surface and passes through the first surface, the third surface three surfaces, the fourth surface and the fifth surface, and the dielectric thermal expansion coefficient of the third joint layer is smaller than the dielectric thermal expansion coefficient of the first joint layer and the dielectric thermal expansion coefficient of the second joint layer coefficient. A method for manufacturing a semiconductor substrate structure, including: Forming a first group of circuit structures on the first temporary carrier, wherein the first group of circuit structures includes multiple layers of first circuit layers and first bonding layers; Forming a second group of circuit structures on the second temporary carrier, wherein the second group of circuit structures includes a plurality of second circuit layers and a second bonding layer; and The first group of circuit structures and the second group of circuit structures are directly bonded, so that the first bonding layer is bonded to the second bonding layer. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein the direct bonding is performed by a copper-to-copper hybrid bonding process or a copper-to-copper direct bonding process. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein forming the first bonding layer further includes: Forming first micro-bumps on the multi-layered first circuit layer; Forming a first connection bump on the first micro-bump; forming a first layer of bonding dielectric material to cover the first microbump and the first connection bump; and A planarization process is performed to form the first bonding member and the first bonding dielectric layer. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein the planarization process is performed with a grinding wheel until the top surface of the first connection bump is exposed to form the first coplanar top surface. The bonding member is bonded to the first bonding dielectric layer. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein forming the second bonding layer further includes: Forming second microbumps on the multilayer second circuit layer; Forming a second connection bump on the second micro-bump; forming a second layer of bonding dielectric material to cover the second microbump and the second connection bump; and A planarization process is performed to form the second bonding member and the second bonding dielectric layer. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein the planarization process is performed with a grinding wheel until the top surface of the second connection bump is exposed to form the second second connection bump with a coplanar top surface. The bonding member is bonded to the second bonding dielectric layer. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein forming the first bonding layer further includes: Forming a first photosensitive dielectric layer on the multi-layer first circuit layer; Patterning the first photosensitive dielectric layer and curing the first photosensitive dielectric layer to form a plurality of openings exposing the underlying first circuit layer; Forming a first seed layer to cover the patterned first photosensitive dielectric layer, and partially filling the first seed layer into the plurality of openings; and An electroplating process is performed to form a first metal layer, and a planarization process is performed using a grinding wheel to form a first joint member and a first joint dielectric layer with coplanar top surfaces. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein forming the second bonding layer further includes: forming a second photosensitive dielectric layer on the multilayer second circuit layer; Patterning the second photosensitive dielectric layer and curing the second photosensitive dielectric layer to form a plurality of openings exposing the underlying second circuit layer; Forming a second seed layer to cover the patterned second photosensitive dielectric layer, and partially filling the second seed layer into the plurality of openings; and An electroplating process is performed to form a second metal layer, and a planarization process is performed using a grinding wheel to form a second joining member and a second joining dielectric layer with coplanar top surfaces. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein after assembling the first group of circuit structures and the second group of circuit structures, the first temporary carrier is removed through a first release layer. The manufacturing method of a semiconductor substrate structure as claimed in claim 27, wherein after removing the first temporary carrier, a plurality of conductive connections are formed on the first set of circuit structures, wherein each of the conductive connections It includes a conductive pillar and a conductive cover, and the conductive cover is formed on the conductive pillar. The manufacturing method of a semiconductor substrate structure as claimed in claim 28, wherein the semiconductor substrate structure is used to provide semiconductor wafers and external terminals on two opposite sides, and includes: bonding the semiconductor chip to the semiconductor substrate structure; Forming a primer on the semiconductor substrate structure; Encapsulating the semiconductor substrate structure and the semiconductor wafer; Remove the second release layer and the second temporary carrier; and The external terminals are formed on the second set of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein the dielectric layer in the first group of circuit structures and the dielectric layer in the second group of circuit structures are organic films. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein the material of the dielectric layer in the first group of circuit structures is the same as the material of the dielectric layer in the second group of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein the material of the dielectric layer in the first group of circuit structures is different from the material of the dielectric layer in the second group of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein the number of the first circuit layers of the first group of circuit structures is the same as the number of the second circuit layers of the second group of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 19, wherein the number of the first circuit layers of the first group of circuit structures is different from the number of the second circuit layers of the second group of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 34, wherein the number of the first circuit layers of the first group of circuit structures is equal to the number of the second circuit layers of the second group of circuit structures. The difference is one or two layers. The semiconductor substrate structure according to claim 19, wherein each first circuit layer includes two adjacent first circuits, and there is a first spacing between the center points of the two adjacent first circuits, Each second circuit layer includes two adjacent second circuits, and there is a second spacing between the center points of the two adjacent second circuits. The first circuit layer of each first circuit layer A pitch is smaller than the second pitch of each second circuit layer, and the first group of circuit structures includes an opposing first surface and a second surface, and the second group of circuit structures includes an opposing third surface. surface and the fourth surface, the first surface is joined to the third surface, and each layer spacing is in a direction from the second surface toward the fourth surface and passes through the first surface and the third surface. A method for manufacturing a semiconductor substrate structure, including: Forming a first group of circuit structures on the first temporary carrier, wherein the first group of circuit structures includes multiple layers of first circuit layers and first bonding layers; Forming a second group of circuit structures on the second temporary carrier, wherein the second group of circuit structures includes a plurality of second circuit layers and a second bonding layer; Directly bonding the first group of circuit structures and the second group of circuit structures so that the first bonding layer is bonded to the second bonding layer; Forming a third group of circuit structures on the second group of circuit structures, wherein the third group of circuit structures includes a plurality of third circuit layers and a third bonding layer; and Bonding the second set of circuit structures and the third set of circuit structures, wherein the second set of circuit structures has another bonding layer relative to the first set of circuit structures, and the other bonding layer is bonded to The third bonding layer. The manufacturing method of a semiconductor substrate structure as claimed in claim 37, wherein the thickness of the third group of circuit structures is greater than the thickness of the first group of circuit structures and the thickness of the second group of circuit structures, and each of the third group of circuit structures A circuit layer includes two adjacent first circuits. There is a first spacing between the center points of the two adjacent first circuits. Each of the second circuit layers includes two adjacent second circuits. , there is a second spacing between the center points of the two adjacent second lines, each of the third line layers includes two adjacent third lines, and the two adjacent third lines have There is a third spacing between center points, the third spacing is greater than the first spacing and the second spacing, the first group of line structures includes opposite first surfaces and second surfaces, and the second group The circuit structure includes opposing third and fourth surfaces, the third set of circuit structures includes opposing fifth and sixth surfaces, the first surface is bonded to the third surface, and the fourth surface is bonded to On the fifth surface, the direction from the second surface toward the sixth surface passes through the first surface, the third surface, the fourth surface and the fifth surface. The manufacturing method of a semiconductor substrate structure as claimed in claim 37, wherein the dielectric thermal expansion coefficient of the third bonding layer is smaller than the dielectric thermal expansion coefficient of the first bonding layer and the dielectric thermoelectric expansion of the second bonding layer. coefficient. The manufacturing method of a semiconductor substrate structure as claimed in claim 37, wherein the dielectric layer in the first group of circuit structures and the dielectric layer in the second group of circuit structures are organic films. The manufacturing method of a semiconductor substrate structure as claimed in claim 37, wherein the material of the dielectric layer in the first group of circuit structures is the same as the material of the dielectric layer in the second group of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 37, wherein the material of the dielectric layer in the first group of circuit structures is different from the material of the dielectric layer in the second group of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 37, wherein the number of the first circuit layers of the first group of circuit structures is the same as the number of the second circuit layers of the second group of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 37, wherein the number of the first circuit layers of the first group of circuit structures is different from the number of the second circuit layers of the second group of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 44, wherein the number of the first circuit layers of the first group of circuit structures is equal to the number of the second circuit layers of the second group of circuit structures. The difference is one or two layers. A method for manufacturing a semiconductor substrate structure, including: Forming a second set of circuit structures on the second temporary carrier; Forming a third group of circuit structures on the second group of circuit structures; joining the second group of circuit structures and the third group of circuit structures; Remove the second temporary carrier; Forming a first set of circuit structures on the first temporary carrier; Directly joining the first set of circuit structures and the second set of circuit structures; removing the first temporary carrier; and Conductive pillars and conductive covers are formed on the surface of the first group of circuit structures, and external terminals are formed on the surface of the third group of circuit structures. The manufacturing method of a semiconductor substrate structure as claimed in claim 46, wherein the third group of circuit structures is not placed on a temporary carrier during the manufacturing process and is a supportive plate-shaped structure. The manufacturing method of a semiconductor substrate structure as claimed in claim 46, wherein the dielectric layer in the first group of circuit structures and the dielectric layer in the second group of circuit structures are organic films.

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