TW202335176A - Method for fabricating semiconductor device having a shielding line for signal crosstalk suppression - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided. The method includes disposing a mandrel layer on a dielectric layer and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. The minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nm. The method also includes etching the dielectric layer by using the first spacer, the second spacer, the third spacer, and the fourth spacer as etching masks to form a first dielectric element, a second dielectric element, a third dielectric element, and a fourth dielectric element. The method also includes forming a first shielding line between the second dielectric element and the third dielectric element.

Description

Method for manufacturing semiconductor device with mask lines to suppress signal crosstalk

This application claims priority to U.S. Patent Application Nos. 17/679,302 and 17/679,482 (that is, the priority date is "February 24, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device with mask lines to suppress signal crosstalk.

Typical memory devices, such as dynamic random access memory (DRAM) devices, include signal lines, such as word lines and bit lines crossing the word lines.

As DRAM devices shrink, the size and/or spacing of signal lines become smaller and smaller, and capacitive coupling and/or inductive magnetic coupling become more significant. Electromagnetic noise or crosstalk between signal lines may also become more severe, thus degrading component performance.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a semiconductor device. The semiconductor element includes: a substrate having a surface; a first signal line disposed on the surface of the substrate; and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line open. The semiconductor device also includes a first mask line between the first signal line and the second signal line. The minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).

Another aspect of the present disclosure provides a semiconductor device. The semiconductor element includes: a substrate having a surface; a first signal line disposed on the surface of the substrate; and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line open. The semiconductor device also includes a first mask line between the first signal line and the second signal line. The minimum distance between the first signal line and the first mask line is equal to or less than about 40 nanometers.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes: arranging a mandrel layer on a dielectric layer, and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. The minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nanometers. The preparation method also includes: forming a first spacer adjacent to a first side of the first mandrel, a second spacer adjacent to a second side of the first mandrel, and the third spacer. a third spacer adjacent to a first side of the two mandrels, and a fourth spacer adjacent to a second side of the second mandrel. The preparation method also includes: etching the dielectric layer using the first spacer, the second spacer, the third spacer and the fourth spacer as etching masks to form a first dielectric element , a second dielectric component, a third dielectric component and a fourth dielectric component. The preparation method also includes: forming a first mask line between the second dielectric component and the third dielectric component.

By forming a dummy line between two signal lines (such as an aggressor line and a victim line) and connecting the dummy line to power or ground, the interference between the signal lines can be reduced or prevented. Electromagnetic noise or crosstalk.

In addition, the manufacturing technology of the dummy lines and signal lines may include a pitch doubling process, such as a self-aligned pitch doubling technology or a self-aligned dual patterning technology. Compared with conventional lithography techniques, the disclosed process overcomes scaling-related lithography issues and creates denser memory arrays. Therefore, the performance of the component can be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, as well as any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment, even if they share the same reference number.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections, these elements, elements, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly dictates otherwise. It should be further understood that the terms "include" and "include", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other Characteristic, integer, step, operation, element, component, or group thereof.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device 1 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 1 may include a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell).

In addition, the semiconductor device 1 may be or include part of an integrated circuit (IC) chip, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, and diodes. , p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors ( BJT), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFET), other suitable IC components or combinations thereof.

As shown in FIG. 1 , in some embodiments, the semiconductor element 1 may include a substrate 10 , a conductive element 11 , signal lines 12 , 15 , dielectric elements 13 , 13 ′, 16 , 16 ′, and mask lines 14 a , 14 b , and 14c.

In some embodiments, the substrate 10 may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP) or other Group IV-IV, Group III-V or Group II-VI semiconductor materials. In other embodiments, the substrate 10 may include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

Depending on the IC preparation stage, substrate 10 may include various material layers (eg, dielectric layers, semiconductor layers, and/or conductive layers) configured to form an IC feature (eg, doped regions, isolation features, gate features, source or drain features, interconnect features, other features, or combinations thereof).

For example, the conductive element 11 may be disposed in the substrate 10 . The manufacturing technology of the conductive element 11 can come from a doped region of a bulk semiconductor substrate or an epitaxial layer. The conductive element 11 may be connected to, for example, the terminals of a MOSFET (eg gate, source or drain), the terminals of a BJT (eg emitter, collector or base) or other IC features in the semiconductor element 1 (eg DRAM cells) are electrically connected.

The conductive element 11 may be at least partially exposed from the substrate 10 . The signal lines 12 and 15 can be electrically connected to one or more conductive elements 11 to control the operation of the semiconductor element 1 (such as a DRAM cell).

In some embodiments, operation of the semiconductor element 1 may include a change of state from a binary one to a binary zero, or vice versa. For example, the state change may involve the accumulation and/or storage of a charge, or the release of a stored charge.

In some embodiments, the conductive element 11 may include, for example, polycrystalline silicon (poly-Si), metal (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or metal alloys. In some embodiments, the conductive element 11 may include, for example, titanium-based material (such as titanium nitride (TiN) or titanium aluminum nitride (TiAlN)), tantalum-based material (such as tantalum nitride (TaN), tantalum nitride Aluminum (TaAlN), or tantalum carbide (Ta2C)), or silicide (such as PtSi, TiSi2, CoSi, NiSi, MoSi2, TaSi, WSi2, etc.).

Although two conductive elements are illustrated, it will be understood that the semiconductor element 1 may comprise any suitable number of conductive elements.

The signal line 12 may be disposed on the surface 101 of the substrate 10 . The signal line 12 can be electrically connected to the conductive element 11 . The width "w2" of the signal line 12 is measured in a direction substantially parallel to the surface 101 of the substrate 10 . Width w2 may be equal to or less than about 20 nanometers (nm). In some embodiments, width w2 may be greater than width "w1" of conductive element 11 measured in a direction substantially parallel to surface 101 of substrate 10 . However, in some other embodiments, width w2 may be equal to or less than width w1.

The signal line 15 may be disposed on the surface 101 of the substrate 10 and spaced apart from the signal line 12 . The signal lines 15 may be electrically connected to conductive elements in the substrate 10 . The signal line 15 may have a width that is substantially equal to the width w2 of the signal line 12 .

The signal line 12 and the signal line 15 may respectively become part of the word line and bit line of the semiconductor device 1 . The signal line 12 and the signal line 15 may each include, for example, polycrystalline silicon (poly-Si), metal (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or metal alloy.

Although two signal lines are illustrated in the figure, it is understood that the semiconductor device 1 may include any suitable number of signal lines.

The signal line 12 may have a side 121 and a side 122 opposite to the side 121 . The side surfaces 121 and 122 may each be substantially perpendicular to the surface 101 of the substrate 10 . The signal line 15 may have a side 151 and a side 152 opposite to the side 151 . The side surfaces 151 and 152 may each be substantially perpendicular to the surface 101 of the substrate 10 .

In some embodiments, the minimum distance “w5” between the signal line 12 and the signal line 15 is measured in a direction substantially parallel to the surface 101 of the substrate 10 . For example, the minimum distance w5 may be measured between the side 122 of the signal line 12 and the side 151 of the signal line 15 . The minimum distance w5 may be equal to or less than about 90 nanometers.

The dielectric component 13 may contact, cover, seal or encapsulate the side 121 of the signal line 12 . The dielectric component 13' may contact, cover, seal or encapsulate the side 122 of the signal line 12. The dielectric component 16 may contact, cover, seal or encapsulate the side 151 of the signal line 15 . The dielectric component 16' may contact, cover, seal or encapsulate the side 152 of the signal line 15.

In some embodiments, the dielectric element 13 , the dielectric element 13 ′, the dielectric element 16 and the dielectric element 16 ′ may each be a spacer. In some embodiments, dielectric element 13 , dielectric element 13 ′, dielectric element 16 and dielectric element 16 ′ may each include, for example, nitride, oxide, oxynitride, amorphous silicon, polycrystalline silicon Or another material suitable for the desired patterning operation as in Figure 4H. Exemplary gap materials may include, but are not limited to, hafnium silicate (HfSiOx), hafnium oxide (HfO2), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon nitride (Si3N4), silicon oxynitride (SiON) Or silicon oxide (SiO2), tetrachlorosilicic acid (TEOS), carbon-doped silicon, etc.

In some embodiments, the dielectric element 13 , the dielectric element 13 ′, the dielectric element 16 and the dielectric element 16 ′ may each be a single-layer structure.

The width “w3” of each of dielectric element 13 , dielectric element 13 ′, dielectric element 16 and dielectric element 16 ′ is measured in a direction substantially parallel to surface 101 of substrate 10 . Width w3 may be equal to or less than about 40 nanometers. For example, width w3 may be between approximately 10 nanometers and approximately 40 nanometers. In some embodiments, dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' may have the same width.

The mask lines 14a, 14b and 14c may each be disposed on the surface 101 of the substrate 10. Mask lines 14a, 14b, and 14c may be part of mask structure 14. The mask lines 14a, 14b, and 14c may be electrically connected to each other. The mask lines 14a, 14b, and 14c may be electrically connected to a power source or ground.

The mask line 14 a and the mask line 14 b may be disposed on opposite sides of the signal line 12 . The signal line 12 may be between the mask line 14a and the mask line 14b. The mask line 14b may be between the signal line 12 and the signal line 15 . The mask line 14b and the mask line 14c may be disposed on opposite sides of the signal line 15. The signal line 15 may be between the mask line 14b and the mask line 14c.

The mask line 14a, the mask line 14b, and the mask line 14c may each be called a dummy line.

Mask lines 14a, 14b, and 14c may not be used to form conductive interconnections with conductive element 11. In contrast, the signal lines 12 and 15 can be disposed on the conductive element 11 and can be used to form conductive interconnections with the conductive element 11 .

Shield lines 14a, 14b, and 14c may be configured to provide signal lines 12 and 15 an electromagnetic interference (EMI) shielding protection. For example, shield lines 14a, 14b, and 14c may be configured to provide an EMI shield to prevent signal line 12 from being interfered with by signal line 15, and vice versa.

The mask lines 14a, 14b, and 14c may each include, for example, polycrystalline silicon (poly-Si), metal (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc. ), or metal alloys. Mask line 14a, mask line 14b and mask line 14c may have the same material. The mask lines 14 a , 14 b and 14 c may have the same material as the signal lines 12 and 15 . In some embodiments, the mask lines 14a, 14b, and 14c may be formed in the same operation as the signal lines 12 and 15.

The width w3 of the dielectric element 13 may be the minimum distance between the mask line 14a and the signal line 12. The width w3 of the dielectric element 13' may be the minimum distance between the mask line 14b and the signal line 12. The width w3 of the dielectric element 16 may be the minimum distance between the mask line 14b and the signal line 15. The width w3 of the dielectric element 16' may be the minimum distance between the mask line 14c and the signal line 15.

The width “w4” of each of the mask lines 14a, 14b, and 14c is measured in a direction substantially parallel to the surface 101 of the substrate 10. Width w4 may be equal to or less than about 70 nanometers. For example, width w4 may be between approximately 10 nanometers and 70 nanometers. In some embodiments, width w4 may be the minimum width of each of mask line 14a, mask line 14b, and mask line 14c. In some embodiments, the width w4 may be defined by a pitch multiplication process, such as a self-aligned pitch doubling technology or a self-aligned double patterning technology. In some embodiments, width w4 may be greater than width w3.

In some embodiments, the minimum distance w5 between the signal line 12 and the signal line 15 may be the sum of the width w4 of the mask line 14b, the width w3 of the dielectric element 13', and the width w3 of the dielectric element 16.

As mentioned, width w3 can be between about 10 nanometers and about 40 nanometers, and width w4 can be between about 10 nanometers and about 70 nanometers. However, the minimum distance w5 between the signal line 12 and the signal line 15 remains equal to or less than about 90 nanometers.

As DRAM devices (such as semiconductor devices 1) shrink, the size and/or spacing of signal lines become smaller and smaller, and capacitive coupling and/or inductive magnetic coupling become significant. Electromagnetic noise or crosstalk between signal lines can become severe, thus degrading component performance.

According to some embodiments of the present disclosure, by forming a dummy line between two signal lines (such as an aggressor line and a victim line) and connecting the dummy line to power or ground, it is possible to Reduce or prevent electromagnetic noise or crosstalk between signal lines.

In addition, the manufacturing technology of dummy lines and signal lines includes a pitch doubling process, such as a self-aligned pitch doubling technology or a self-aligned dual patterning technology. Compared with conventional lithography techniques, the disclosed process overcomes scaling-related lithography issues and creates denser memory arrays. Therefore, the performance of the component can be improved.

FIG. 1B is a schematic top view illustrating a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the cross-sectional view shown in FIG. 1A (or the cross-sectional view shown in FIG. 2, or the cross-sectional view shown in FIG. 3) may be a cross-sectional view of a portion of the semiconductor device shown in FIG. IB.

For example, the semiconductor element 1 shown in FIG. 1A may be a top view highlighted by a dashed frame. For example, the semiconductor device 1 shown in FIG. 1A may be formed at a periphery of a memory array. In some embodiments, the circuit density of the perimeter may be less than the density of the memory array (eg, densely spaced area). For example, the minimum distance between the signal line 12 and the signal line 15 may be greater than the minimum distance between the two lines in the memory array.

In some embodiments, the cross-sectional view shown in Figure 1A (or the cross-sectional view shown in Figure 2, or the cross-sectional view shown in Figure 3) can be in two directions, the "X" direction (corresponding to the character line along its elongation direction) and the "Y" direction (corresponding to the direction along which the bit line elongates). In some embodiments, the word line direction may be substantially orthogonal to the bit line direction. In other embodiments, the word line direction may not be orthogonal to the bit line direction.

In some embodiments, the signal lines (such as the signal lines 12 and the signal lines 15 ) of the semiconductor device 1 may be parallel. In some embodiments, the mask lines of the semiconductor device 1 (such as the mask lines 14a, 14b, and 14c) may be parallel. In some embodiments, the signal lines and mask lines of the semiconductor device 1 may be parallel.

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device 2 according to some embodiments of the present disclosure. The semiconductor element 2 of FIG. 2 is similar to the semiconductor element 1 of FIG. 1A except for the differences described below.

In FIG. 2 , the width w3 of each of the dielectric elements 13 , 13 ′, 16 , and 16 ′ may be larger than that of the mask lines 14 a , 14 b , and 14 c The width of each is w4.

FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device 3 according to some embodiments of the present disclosure. The semiconductor element 3 of FIG. 3 is similar to the semiconductor element 1 of FIG. 1A except for the differences described below.

In FIG. 3 , the width w3 of each of the dielectric element 13 , the dielectric element 13 ′, the dielectric element 16 and the dielectric element 16 ′ may be substantially equal to the mask line 14 a , the mask line 14 b and the mask line The width of each of 14c is w4.

4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J and 4K illustrate stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. In order to better understand various aspects of the present disclosure, at least some of the figures have been simplified. In some embodiments, the semiconductor element 1 in FIG. 1A, the semiconductor element 2 in FIG. 2, and the semiconductor element 3 in FIG. 4F, 4G, 4H, 4I, 4J and 4K.

Referring to Figure 4A, a substrate 10 is provided in which one or more conductive elements 11 may be formed. The manufacturing technology of the conductive element 11 can come from a doped region of a piece of semiconductor substrate, or an epitaxial layer. The conductive element 11 may be at least partially exposed from the substrate 10 .

In some embodiments, the manufacturing technology of the shallow trench isolation (STI) region (not shown in the figure) may include, for example, lithography, etching, deposition and chemical mechanical polishing (CMP) processes to form within the substrate 10 to form Electrically isolate subsequently formed signal lines.

The dielectric layer 40 may be disposed on the surface 101 of the substrate 10 . In some embodiments, the dielectric layer 40 may be disposed on the surface 101 of the substrate 10 in a blanket shape. In some embodiments, the fabrication technique of dielectric layer 40 may include a thermal oxidation operation, a chemical vapor deposition (CVD) operation, a low pressure chemical vapor deposition (LPCVD) operation, a plasma enhanced chemical vapor deposition (CVD) operation. PECVD) operation, other feasible operations, or combinations thereof. Dielectric layer 40 may include materials as listed above for dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' in FIG. 1A.

The mandrel layer 42 may be disposed on the dielectric layer 40 . The mandrel layer 42 may be disposed on the dielectric layer 40 in a blanket manner. In some embodiments, the fabrication technique of the mandrel layer 42 may include a thermal oxidation operation, a CVD operation, a LPCVD operation, a PECVD operation, other feasible operations, or a combination thereof. The mandrel layer 42 may include, for example, a nitride, an oxide, an oxynitride amorphous silicon, a polycrystalline silicon, or other material suitable for the desired patterning operation as shown in FIG. 4C.

In some embodiments, etch stop layer 41 may be formed on dielectric layer 40 prior to forming mandrel layer 42 . In some other embodiments, etch stop layer 41 may be omitted. For the sake of simplicity, the etching stop layer 41 is not illustrated in the following operations.

Referring to FIG. 4B , the mask layer 43 may be disposed on the mandrel layer 42 . Mask layer 43 may include, for example, nitride, oxide, oxynitride amorphous silicon, polycrystalline silicon, or other materials suitable for use in the patterning operation as shown in Figure 4C. In some embodiments, the manufacturing technology of the mask layer 43 may include, for example, a CVD operation, a LPCVD operation, a PECVD operation, other feasible operations, or a combination thereof.

In some embodiments, a photoresist (not shown) and another sacrificial mask material, such as an anti-reflective coating (ARC) material, may be deposited on the mask layer 43 .

Referring to FIG. 4C , the patterning technology of the mask layer 43 may include photolithography and etching processes to form the mask pattern 43p. Patterning techniques for mandrel layer 42 may include using mask pattern 43p as an etch mask. Therefore, mandrels 42a and 42b can be formed.

In some embodiments, mask layer 43 and mandrel layer 42 may be anisotropically etched. In some embodiments, mask layer 43 and mandrel layer 42 may be etched in the same operation. In some embodiments, mask layer 43 and mandrel layer 42 may be etched in different operations. For example, etching techniques for mask layer 43 and mandrel layer 42 may include, for example, reactive ion etching (RIE) using different chemistries.

Spindles 42a and 42b may have a width w2 as described with respect to Figure 1A. Width w2 may be equal to or less than about 20 nanometers. Spindles 42a and 42b may be spaced apart from each other by a minimum distance w5, as described in Figure 1A. The minimum distance w5 may be equal to or less than about 90 nanometers.

The spindle 42a may have a side 421 and a side 422 opposite the side 421. The spindle 42b may have a side 423 and a side 424 opposite the side 423.

Referring to FIG. 4D, the removal technique for removing the mask pattern 43p from the mandrels 42a and 42b may include, for example, an etching process.

Referring to FIG. 4E , the conformal gap sublayer 44 may be disposed on the dielectric layer 40 to cover the mandrels 42 a and 42 b. Fabrication techniques for conformal spacer layer 44 may include silicon nitride, silicon oxide, silicon oxynitride, or any type of organic or inorganic material that has etch selectivity relative to mandrels 42a and 42b. The fabrication technique of the conformal gap sub-layer 44 may include, for example, an atomic layer deposition (ALD) operation, a CVD operation, a LPCVD operation, a PECVD operation, other feasible operations, or combinations thereof.

4F, the conformal spacer layer 44 may be partially removed to form spacers 44a adjacent side 421 of mandrel 42a, spacers 44a' adjacent side 422 of mandrel 42a, and spacers 44a' adjacent side 422 of mandrel 42a. The spacer 44b is adjacent to the side surface 423 of the mandrel 42b, and the spacer 44b' is adjacent to the side surface 424 of the mandrel 42b. For example, the etching technique for conformal interstitial sublayer 44 may include a RIE operation based on chemicals CHF3 or CF4 to etch silicon oxide or silicon oxynitride, or a CHF3/O2-based etching of silicon nitride.

Spacers 44a, 44a', 44b, and 44b' are each formed with a width w3 described with respect to FIG. 1A. Width w3 may be equal to or less than about 40 nanometers. For example, width w3 may be between approximately 10 nanometers and approximately 40 nanometers.

Since the minimum distance w5 between the signal line 12 and the signal line 15 remains equal to or less than about 90 nanometers, the width w4 can be between about 10 nanometers and about 70 nanometers.

Referring to FIG. 4G , mandrels 42 a and 42 b may be removed from the dielectric layer 40 , leaving spacers 44 a , 44 a ′, 44 b , and 44 b ′ on the dielectric layer 40 . For example, the etching technique for mandrels 42a and 42b may include a RIE operation.

Removing mandrels 42a and 42b results in a gap between spacer 44a and spacer 44a', and a gap between spacer 44b and spacer 44b'. The width w2 of the spindles 42a and 42b can be controlled to determine the width w2 of the gap.

Referring to FIG. 4H , the patterning technique of dielectric layer 40 may include etching using spacers 44a, 44a', 44b, and 44b' as etch masks. Therefore, dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' can be formed.

Dielectric element 13 , dielectric element 13 ′, dielectric element 16 and dielectric element 16 ′ are each formed with a width w3 described with respect to FIG. 1A . Width w3 may be equal to or less than about 40 nanometers. For example, width w3 may be between approximately 10 nanometers and 40 nanometers.

Referring to FIG. 4I , the removal technique of spacers 44 a , 44 a ′, 44 b , and 44 b ′ may include, for example, an etching process.

Referring to FIG. 4J , the conductive layer 45 may be disposed on the substrate 10 to cover the dielectric element 13 , the dielectric element 13 ′, the dielectric element 16 and the dielectric element 16 ′. The conductive layer 45 may include, for example, polycrystalline silicon (poly-Si), metal (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or a metal alloy. The fabrication technology of the conductive layer 45 may include, for example, an ALD operation, a CVD operation, a LPCVD operation, a PECVD operation, other feasible operations, or a combination thereof.

Referring to FIG. 4K , the conductive layer 45 may be partially removed to form mask lines 14a, 14b, and 14c. In addition, the production of the signal line 12 and the signal line 15 can be included in the same operation.

The width w4 can be defined by a pitch doubling process, such as a self-aligned pitch doubling technology or a self-aligned dual patterning technology. Since the minimum distance w5 between the signal line 12 and the signal line 15 remains equal to or less than about 90 nanometers, the width w4 can be between about 10 nanometers and about 70 nanometers.

FIG. 5 is a flowchart illustrating a method 50 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, the preparation method 50 may include step S51 of disposing a mandrel layer on a dielectric layer. For example, as shown in FIG. 4A , the mandrel layer 42 may be disposed on the dielectric layer 40 .

In some embodiments, the preparation method 50 may include step S52 of patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. For example, as shown in FIG. 4C , the patterning technique of the mandrel layer 42 may include etching using the mask pattern 43 p as an etch. Therefore, mandrels 42a and 42b can be formed. In some embodiments, the minimum distance w5 between spindles 42a and 42b is equal to or less than about 90 nanometers.

In some embodiments, the preparation method 50 may include step S53 of forming a first spacer adjacent to a first side of the first mandrel, and a first spacer adjacent to a second side of the first mandrel. A second spacer, a third spacer adjacent a first side of the second mandrel, and a fourth spacer adjacent a second side of the second mandrel. For example, as shown in Figure 4F, conformal spacer layer 44 may be partially removed to form spacers 44a adjacent side 421 of mandrel 42a, spacers 44a' adjacent side 422 of mandrel 42a , a spacer 44b adjacent to the side 423 of the mandrel 42b, and a spacer 44b adjacent to the side 424 of the mandrel 42b.

In some embodiments, the preparation method 50 may include step S54 of etching the dielectric layer using the first spacer, the second spacer, the third spacer and the fourth spacer as etching masks to A first dielectric component, a second dielectric component, a third dielectric component and a fourth dielectric component are formed. For example, as shown in FIG. 4H , the patterning technique of the dielectric layer 40 may include etching using the spacers 44a, the spacers 44a', the spacers 44b, and the spacers 44b' as etching masks. Therefore, dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' can be formed.

In some embodiments, the manufacturing method 50 may include step S55 of forming a first mask line between the second dielectric component and the third dielectric component. For example, as shown in FIG. 4K , a mask line 14b is formed between the dielectric element 13' and the dielectric element 16.

One aspect of the present disclosure provides a semiconductor device. The semiconductor element includes: a substrate having a surface; a first signal line disposed on the surface of the substrate; and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line open. The semiconductor device also includes a first mask line between the first signal line and the second signal line. The minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).

Another aspect of the present disclosure provides a semiconductor device. The semiconductor element includes: a substrate having a surface; a first signal line disposed on the surface of the substrate; and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line open. The semiconductor device also includes a first mask line between the first signal line and the second signal line. The minimum distance between the first signal line and the first mask line is equal to or less than about 40 nanometers.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes: arranging a mandrel layer on a dielectric layer, and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. The minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nanometers. The preparation method also includes: forming a first spacer adjacent to a first side of the first mandrel, a second spacer adjacent to a second side of the first mandrel, and the third spacer. a third spacer adjacent to a first side of the two mandrels, and a fourth spacer adjacent to a second side of the second mandrel. The preparation method also includes: etching the dielectric layer using the first spacer, the second spacer, the third spacer and the fourth spacer as etching masks to form a first dielectric element , a second dielectric component, a third dielectric component and a fourth dielectric component. The preparation method also includes: forming a first mask line between the second dielectric component and the third dielectric component.

By forming a dummy line between two signal lines (such as an aggressor line and a victim line) and connecting the dummy line to power or ground, the signal lines can be reduced or prevented. electromagnetic noise or crosstalk.

In addition, the manufacturing technology of the dummy lines and signal lines may include a pitch doubling process, such as a self-aligned pitch doubling technology or a self-aligned dual patterning technology. Compared with conventional lithography techniques, the disclosed process overcomes scaling-related lithography issues and creates denser memory arrays. Therefore, the performance of the component can be improved.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1: Semiconductor components 2: Semiconductor components 3: Semiconductor components 10: Base 11:Conductive components 12:Signal line 13:Dielectric components 13': Dielectric components 14: Mask structure 14a: Mask line 14b: Mask line 14c: Mask line 15:Signal line 16:Dielectric components 16': Dielectric components 40:Dielectric layer 41: Etch stop layer 42: mandrel layer 42a: mandrel 42b: mandrel 43:Mask layer 43p:mask pattern 44: Conformal gap sublayer 44a: Gap 44a': spacer 44b: Gap 44b': spacer 50:Preparation method 101:Surface 121:Side 122:Side 151:Side 152:Side 421:Side 422:Side 423:Side 424:Side S51: Steps S52: Steps S53: Steps S54: Steps S55: Steps w1:width w2:width w3:width w4:width w5:width

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1A is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 1B is a schematic top view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 4A illustrates one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 4B illustrates one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 4C illustrates one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 4D illustrates one or more stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4E illustrates one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. 4F illustrates one or more stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure. 4G illustrates one or more stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure. 4H illustrates one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. 4I illustrates one or more stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure. 4J illustrates one or more stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure. 4K illustrates one or more stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 5 is a flow chart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

1: Semiconductor components

10: Base

11:Conductive components

12:Signal line

13:Dielectric components

13': Dielectric components

14: Mask structure

14a: Mask line

14b: Mask line

14c: Mask line

15:Signal line

16:Dielectric components

16': Dielectric components

101:Surface

121:Side

122:Side

151:Side

152:Side

w1:width

w2:width

w3:width

w4:width

w5:width

Claims (18)

A method for preparing semiconductor components, including: disposing a mandrel layer on a dielectric layer; Patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel, wherein a minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nanometers; A first spacer is formed adjacent to a first side of the first mandrel, a second spacer adjacent to a second side of the first mandrel, and a first spacer adjacent to the second mandrel. a third spacer adjacent to one side, and a fourth spacer adjacent to a second side of the second mandrel; The dielectric layer is etched using the first spacer, the second spacer, the third spacer and the fourth spacer as etching masks to form a first dielectric element and a second dielectric element. component, a third dielectric component and a fourth dielectric component; and A first mask line is formed between the second dielectric component and the third dielectric component. The preparation method as described in claim 1 further includes: An etching stop layer is disposed on the dielectric layer. The preparation method as described in claim 1 further includes: A conformal gap sub-layer is provided to cover the first mandrel and the second mandrel. The preparation method as described in claim 1 further includes: The conformal spacer layer is partially removed to form the first spacer, the second spacer, the third spacer and the fourth spacer. The preparation method of claim 1, wherein the minimum width of each of the first spacer, the second spacer, the third spacer and the fourth spacer is between about 10 nanometers and about 40 nanometers. meters. The preparation method as described in claim 1 further includes: Before etching the dielectric layer, the first mandrel and the second mandrel are removed from the dielectric layer. The preparation method of claim 1, wherein the minimum width of each of the first dielectric element, the second dielectric element, the third dielectric element and the fourth dielectric element is about 10 nanometers and about 40 nm. The preparation method as described in claim 1 further includes: A conductive layer is provided to cover the first dielectric component, the second dielectric component, the third dielectric component and the fourth dielectric component. The preparation method as described in claim 8 further includes: The conductive layer is partially removed to form a first signal line and a second signal line. The preparation method of claim 1, wherein the minimum width of the first mask line is between about 10 nanometers and about 70 nanometers. The preparation method as described in claim 1 further includes: A second mask line is formed, wherein the first signal line is disposed between the first mask line and the second mask line. The preparation method as claimed in claim 11, wherein the first mask line and the second mask line are electrically connected. The preparation method as described in claim 11 further includes: A third mask line is formed, wherein the second signal line is disposed between the first mask line and the third mask line. The preparation method as claimed in claim 13, wherein the first mask line and the third mask line are electrically connected. The preparation method as claimed in claim 11, wherein the first mask line, the second mask line and the third mask line are substantially parallel. The preparation method as described in claim 11 further includes: forming a first dielectric element in contact with a first side of the first signal line; and A second dielectric component is in contact with a second side of the first signal line, the second side being opposite to the first side. The manufacturing method of claim 16, wherein the minimum width of the first dielectric element is substantially equal to the minimum width of the second dielectric element. The preparation method of claim 16, wherein the first side and the second side of the first signal line are substantially perpendicular to the surface of the substrate.