TW202133363A - Embedded semiconductor package and packaging method thereof - Google Patents

Abstract

The present invention relates to an embedded semiconductor package and packaging method thereof. In the packaging method, a thermosetting dielectric layer is laminated on a carrier and multiple chips are mounted on the carrier by the thermosetting dielectric layer. After then, the thermosetting dielectric layer is solidified by heating step and then a molding compound is formed to encapsulate the chips. The carrier is removed to show a flat surface of the solidified thermosetting dielectric layer and a laser opening step and RDL forming step is continually executed on the flat surface. Therefore, an RDL is accurately and electrically connected to pads of the chips.

Description

Embedded semiconductor packaging structure and packaging method thereof

The invention relates to an embedded semiconductor packaging structure and its packaging method, in particular to an embedded wafer-level ball grid array or panel-level ball grid array semiconductor packaging structure and its packaging method.

The current embedded wafer-level ball grid array or panel-level ball grid array semiconductor packaging method can mass produce semiconductor packaging structures with smaller package sizes. Due to the improvement of the accuracy of the packaging process steps, the error of some process steps causes poor packaging yield.

Please refer to FIG. 3A to FIG. 3H, an embedded panel-level ball grid array semiconductor packaging method. As shown in FIG. 3A, a carrier 70 with a release layer 71 is prepared, and the release layer 71 is coated In this way, a thermoplastic adhesive material 72' is coated to form an adhesive layer 72, as shown in FIG. 3B. Then, as shown in FIG. 3C, a plurality of chips 80 are adhered to the adhesive layer 72, and then a compression molding process is performed. As shown in FIG. 3D, a sealant 81 is formed to cover the chips 80. As shown in FIG. 3E, another carrier board 73 is adhered to the top surface of the sealing compound 81, and the original carrier board 70 and its upper adhesive layer 72 are removed.

Since the chips 80 of FIG. 3C are pressed and adhered to the adhesive layer 72 with different strengths, and the adhesive layer 72 will be softened during the high-temperature molding process of FIG. 3D, causing the position of the chip 80 to shift, as shown in FIG. As shown in 3E, the wafers 80 are not flush; then, as shown in FIG. 3F, a dielectric insulating layer 90 is formed on the wafers 80. Since the wafers 80 are not flush, the dielectric insulation The upper surface 901 of the layer 90 cannot form a flat surface. As shown in FIG. 3G, a photoresist layer 91 is formed on the dielectric insulating layer 90, and the photoresist layer 91 is also uneven. Then, the dielectric insulating layer 90 is opened with holes 902 according to the exposure and development process, such as As shown in FIG. 3H, the size W1 and W2 of the opening 902 are not consistent with the shape, and the position of the opening 902 cannot be aligned with the corresponding contact 801 of each chip 80. As shown in FIG. 3I, only part of the contact 801 is exposed. For the subsequent rewiring process, there is a high probability that the rewiring cannot be electrically connected to the corresponding chip contacts smoothly.

Therefore, the current embedded wafer-level ball grid array or panel-level ball grid array semiconductor packaging method must be further improved to ensure good electrical connection between the chip contacts and the redistribution layer.

In view of the shortcomings of the above-mentioned embedded wafer-level ball grid array or panel-level ball grid array semiconductor package structure, the main purpose of the present invention is to provide a new embedded semiconductor package structure and its manufacturing method, whose rewiring layer can be accurately connected to the chip. Point alignment and good electrical connection.

The main technical means used to achieve the above purpose is to make the embedded semiconductor package structure include: A redistribution layer includes a first surface and a second surface; wherein the second surface is formed with a plurality of external connections; A thermosetting dielectric layer includes a flat surface and a plurality of openings, the flat surface is connected to the first surface of the redistribution layer, and each of the openings is formed with a metal pillar to correspond to the metal inside the redistribution layer Line connection A chip is arranged on the thermoset dielectric layer and includes a plurality of contacts, each of the contacts corresponds to and connects to the metal pillars of the openings of the thermoset dielectric layer; and The sealant layer is formed on the thermosetting dielectric layer and covers the chip therein.

It can be seen from the above description that the present invention mainly uses the thermosetting dielectric layer to provide a flat surface of the redistribution layer during the manufacturing process, that is, the surface connecting the thermosetting dielectric layer and the redistribution layer is a flat surface to ensure the rewiring layer. The bonding alignment between the wiring layer and the wafer contacts.

The main technical means used to achieve the above purpose is to make the embedded semiconductor packaging structure method include the following steps: (a) Provide a first carrier, and a release layer is formed on the upper surface of the first carrier; (b) Laminating a thermosetting dielectric layer on the release layer; wherein the thermosetting dielectric layer is in the B state and has adhesiveness; (c) pressing multiple chips on the thermosetting dielectric layer; (d) Heating the thermosetting dielectric layer to cure it from the B state to the C state; wherein the thermosetting dielectric layer in the C state is cured without stickiness; (e) forming a sealant layer on the thermosetting dielectric layer to cover the chips; (f) Place the sealing glue layer on a second carrier board, and remove the first carrier board and its upper release layer to expose the thermosetting dielectric layer; (g) Align the contacts of each chip and make holes on the thermosetting dielectric layer; (h) forming a rewiring layer on the thermosetting dielectric layer; (i) forming a plurality of external connections on the redistribution layer; and (j) Cut and separate out multiple embedded semiconductor packaging structures.

It can be seen from the above description that the packaging method of the present invention mainly uses the thermosetting dielectric layer for the chip to be temporarily bonded to the first carrier, and because the thermosetting dielectric layer has heat curing properties, it is heated and cured after the chip is bonded. Used as an insulating dielectric layer, it also ensures that the chip will not be displaced during the high-temperature process of the mold forming the encapsulant layer, and because the thermosetting dielectric layer has been cured and has a fixed thickness, it can provide a flat rewiring layer process. Surface to ensure the bonding alignment between the redistribution layer and the wafer contacts.

The present invention is aimed at improving the embedded wafer-level ball grid array or panel-level ball grid array semiconductor packaging structure and its packaging method. The technical content of the present invention will be described in detail with embodiments and drawings below.

First, please refer to FIG. 1, which is an embodiment of an embedded semiconductor packaging structure 1 of the present invention, which includes a rewiring layer 10, a thermosetting dielectric layer 20, a chip 30 and a sealant layer 40.

The redistribution layer 10 includes a first surface 101 and a second surface 102; wherein the second surface 102 is formed with a plurality of external connections 13, and the redistribution layer 10 is formed in an insulating dielectric body 11 A plurality of metal circuits 12; in this embodiment, the external connections 13 on the second surface 102 of the redistribution layer 10 are solder balls.

The thermosetting dielectric layer 20 includes a flat surface 201 and a plurality of openings 21, the flat surface 201 is connected to the first surface 101 of the redistribution layer 10, and each of the openings 21 is formed with a metal pillar 22 to connect with The inside of the redistribution layer 10 is connected to the corresponding metal line 12. In this embodiment, the thickness of the thermosetting dielectric layer 20 may be greater than 10 um, and the flatness of the thermosetting dielectric layer is less than or equal to 0.5 um, but it is not limited thereto.

The above-mentioned chip 30 has a plurality of contacts 31, and the chip 30 is disposed on the thermosetting dielectric layer 20, and each of the contacts 31 corresponds to and connects to the metal pillar 21 of the opening of the thermosetting dielectric layer 20, and further connects to the thermosetting dielectric layer 20. The metal lines 12 of the redistribution layer 10 are electrically connected.

The above-mentioned encapsulant layer 40 is formed on the thermosetting dielectric layer 20 and covers the chip 30 therein; in this embodiment, the flatness of the encapsulant body is less than or equal to 0.5 um, but it is not limited thereto.

The above-mentioned thermosetting dielectric layer 20 is used for temporary bonding of the chip 30 during the packaging process. Since the thermosetting dielectric layer 20 has heat curing properties, it is heated and cured after the chip 30 is bonded, and it is directly used as an insulating dielectric layer without being moved. , It also ensures that the wafer 30 will not be displaced during the high temperature process of forming the molding layer 40, and because the thermosetting dielectric layer 20 has been cured and has a fixed thickness, it can provide a flat surface 201 for the redistribution layer process. , To ensure the bonding and alignment between the redistribution layer 10 and the contact 31 of the wafer 30.

Please refer to FIGS. 2A to 2J again, which are the packaging method of the embedded semiconductor structure of the present invention, which includes the following steps (a) to (j).

In step (a), as shown in FIGS. 2A and 2B, a first carrier 50 is provided; wherein a release layer 51 is formed on the upper surface of the first carrier 50; in this embodiment, the release layer 51 can be formed by coating.

In step (b), as shown in FIG. 2B, a thermosetting dielectric layer 20' is laminated on the release layer 51; wherein the thermosetting dielectric layer 20' is not liquid and has a fixed thickness D (can be Greater than 10um); in this embodiment, the thermosetting dielectric layer 20' is in the B state and has viscosity.

In step (c), as shown in FIG. 2C, a plurality of chips 30 are pressed onto the thermosetting dielectric layer 20' to be adhered to the first carrier 50.

In step (d), the thermosetting dielectric layer 20 is heated to be cured to change from the B state to the C state; wherein the thermosetting dielectric layer 20 in the C state is cured without adhesion.

In step (e), as shown in FIG. 2D, a sealant layer 40 is formed on the thermosetting dielectric layer 20 to cover the chips 30; in this embodiment, the sealant body 40 is formed by molding .

In step (f), as shown in FIG. 2E, the encapsulant layer 40 is disposed on a second carrier 60, and the first carrier 50 and its upper release layer 51 are removed to make the thermosetting dielectric A flat surface 201 of the layer 20 is exposed, as shown in FIG. 2F.

In step (g), as shown in FIG. 2G, align the contacts 31 of each of the wafers 30, and make holes 21 on the thermosetting dielectric layer 20; in this embodiment, an excimer laser or UV laser is used A laser opening 21 is performed on the thermosetting dielectric layer 20 so that the contacts 31 of each chip 30 are exposed.

In step (h), as shown in FIG. 2H, a redistribution layer process is performed, that is, a redistribution layer 10 is formed on the thermosetting dielectric layer 20.

In step (i), as shown in FIG. 2I, a plurality of external connectors 13 are formed on the redistribution layer 10; in this embodiment, each of the external connectors 13 is a solder ball.

In step (j), as shown in FIG. 2J, a plurality of embedded semiconductor packaging structures 1 are cut and separated.

In summary, the embedded semiconductor encapsulation method of the present invention mainly uses the thermosetting dielectric layer 20', which is used for temporarily bonding the chip 30 during the packaging process. Because the thermosetting dielectric layer 20' has heat curing properties, After the chip 30 is bonded, it is heated and cured, and it is directly used as an insulating dielectric layer without removing it, so as to ensure that the chip 30 will not be displaced during the high-temperature molding process for forming the encapsulant layer 40, and because of the thermosetting dielectric The layer 20 has been cured and has a fixed thickness D. After the first carrier 50 is removed, a flat surface 201 for the next redistribution layer manufacturing process can be provided to ensure the contact 31 between the redistribution layer 10 and the chip 30 Join the counterpoint. In addition, with the laser opening, the position of the opening can be more accurately ensured and the opening diameter W is consistent.

The above are only the embodiments of the present invention and do not limit the present invention in any form. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field, Without departing from the scope of the technical solution of the present invention, when the technical content disclosed above can be used to make slight changes or modification into equivalent embodiments with equivalent changes, but any content that does not depart from the technical solution of the present invention is based on the technical essence of the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

1: Embedded semiconductor package structure 10: Redistribution layer 101: first surface 102: second surface 11: Insulating dielectric body 12: Metal circuit 13 external connectors 20: Thermoset dielectric layer 20’: Thermoset dielectric layer 201: Flat surface 21: Hole 22: Metal column 30: chip 31: Contact 40: Sealing layer 50: The first carrier board 51: Release layer 60: second carrier board 70: carrier board 71: release layer 72: Adhesive layer 72’: Thermoplastic glue 73: carrier board 80: chip 801: Contact 81: Sealing layer 90: Dielectric insulation layer 901: upper surface 902: hole 91: photoresist layer

FIG. 1 is a cross-sectional view of an embodiment of the embedded semiconductor package structure of the present invention. 2A to 2J: cross-sectional views of the structure corresponding to each step in the embedded semiconductor packaging method of the present invention. 3A to 3H: the structural cross-sectional views corresponding to each step in the existing embedded panel-level ball grid array semiconductor packaging method (excluding the rewiring layer).

1: Embedded semiconductor package structure

10: Redistribution layer

101: first surface

102: second surface

11: Insulating dielectric body

12: Metal circuit

13: External connector

20: Thermoset dielectric layer

201: Flat surface

21: Hole

22: Metal column

30: chip

31: Contact

40: Sealing layer

Claims (10)

An embedded semiconductor packaging structure, including: A redistribution layer includes a first surface and a second surface; wherein the second surface is formed with a plurality of external connections; A thermosetting dielectric layer includes a flat surface and a plurality of openings, the flat surface is connected to the first surface of the redistribution layer, and each of the openings is formed with a metal pillar to correspond to the metal inside the redistribution layer Line connection A chip is arranged on the thermoset dielectric layer and includes a plurality of contacts, each of the contacts corresponds to and connects to the metal pillars of the openings of the thermoset dielectric layer; and The sealant layer is formed on the thermosetting dielectric layer and covers the chip therein. The embedded semiconductor package structure according to claim 1, wherein the thickness of the thermosetting dielectric layer is greater than 10um. The embedded semiconductor package structure according to claim 1 or 2, wherein the flatness of the thermosetting dielectric layer is less than or equal to 0.5 um. The embedded semiconductor package structure according to claim 1 or 2, wherein the flatness of the molding compound is less than or equal to 0.5 um. The embedded semiconductor package structure according to claim 1 or 2, wherein each of the external connections is a solder ball. An embedded semiconductor packaging method includes: (a) Provide a first carrier, and a release layer is formed on the upper surface of the first carrier; (b) Laminating a thermosetting dielectric layer on the release layer; wherein the thermosetting dielectric layer is in the B state and has adhesiveness; (c) pressing multiple chips on the thermosetting dielectric layer; (d) Heating the thermosetting dielectric layer to cure it from the B state to the C state; wherein the thermosetting dielectric layer in the C state is cured without stickiness; (e) forming a sealant layer on the thermosetting dielectric layer to cover the chips; (f) Place the sealing glue layer on a second carrier board, and remove the first carrier board and its upper release layer to expose the thermosetting dielectric layer; (g) Align the contacts of each chip and make holes on the thermosetting dielectric layer; (h) forming a rewiring layer on the thermosetting dielectric layer; (i) forming a plurality of external connections on the redistribution layer; and (j) Cut and separate out multiple embedded semiconductor packaging structures. The embedded semiconductor packaging method according to claim 6, wherein the thickness of the thermosetting dielectric layer in the step (b) is greater than 10um. The embedded semiconductor packaging method according to claim 6 or 7, wherein the step (g) is to make a hole with a laser. The embedded semiconductor packaging method according to claim 8, wherein the step (g) uses an excimer laser or a UV laser. The embedded semiconductor packaging method according to claim 6, wherein each of the external connections is a solder ball.

Images