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TW202131472A - 半導體裝置以及其製造方法 - Google Patents

半導體裝置以及其製造方法 Download PDF

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Publication number
TW202131472A
TW202131472A TW109130239A TW109130239A TW202131472A TW 202131472 A TW202131472 A TW 202131472A TW 109130239 A TW109130239 A TW 109130239A TW 109130239 A TW109130239 A TW 109130239A TW 202131472 A TW202131472 A TW 202131472A
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TW
Taiwan
Prior art keywords
layer
hole
carrier substrate
pattern
insulating layer
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TW109130239A
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English (en)
Inventor
李昌普
孫瓘后
吳俊錫
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南韓商三星電子股份有限公司
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Publication of TW202131472A publication Critical patent/TW202131472A/zh

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Abstract

揭露半導體裝置以及其製造方法。所述方法包括：提供載體基板，所述載體基板包括導電層；將半導體晶粒放置於載體基板上；形成絕緣層，以覆蓋載體基板上的半導體晶粒；形成通孔孔洞，以在半導體晶粒的一側處穿透絕緣層並暴露出載體基板的導電層；執行鍍覆製程，在鍍覆製程中使用載體基板的導電層作為晶種來形成對通孔孔洞進行填充的通孔；在半導體晶粒的第一表面及絕緣層上形成第一重佈線層；移除載體基板；以及在半導體晶粒的第二表面及絕緣層上形成第二重佈線層，第一表面與第二表面被定位成彼此相對。

Description

半導體裝置以及其製造方法
本發明概念是有關於一種半導體裝置，且更具體而言是有關於晶圓級半導體封裝及面板級半導體封裝。
提供半導體封裝實施積體電路晶片，以使積體電路晶片有資格用於電子產品。在半導體封裝中，半導體晶片通常安裝於印刷電路板（printed circuit board，PCB）上，且使用接合配線或凸塊將半導體晶片電性連接至印刷電路板。隨著電子產業的近來發展，半導體封裝被以各種方式進行開發，以達成大小緊密、重量小及/或製作成本低的目標。另外，許多種類的半導體封裝隨著其應用領域的擴展而出現，例如高容量的大量儲存裝置（mass storage device）。
隨著半導體晶片的高度整合，半導體晶片的大小變得更小。然而，由於半導體晶片的大小小，因此難以對焊料球進行黏著、處理及測試。另外，在根據半導體晶片的大小獲取多樣化安裝板時可能會出現問題。提出扇出型晶圓級封裝（fan-out wafer level package，FO-WLP）及扇出型面板級封裝（fan-out panel level package，FO-PLP）來解決該些問題中的一些問題。
本發明概念的一些示例性實施例提供一種具有減少的缺陷的半導體裝置以及其製造方法。
本發明概念的標的並非僅限於上述內容，且根據以下說明，熟習此項技術者將清楚地理解以上未提及的其他標的。
根據本發明概念的一些示例性實施例，一種製造半導體裝置的方法可包括：提供載體基板，所述載體基板包括導電層；將半導體晶粒放置於所述載體基板上；形成絕緣層，以覆蓋所述載體基板上的所述半導體晶粒；形成通孔孔洞，以在所述半導體晶粒的一側處穿透所述絕緣層並暴露出所述載體基板的所述導電層；執行鍍覆製程，在所述鍍覆製程中使用所述載體基板的所述導電層作為晶種來形成對所述通孔孔洞進行填充的通孔；在所述半導體晶粒的第一表面及所述絕緣層上形成第一重佈線層；移除所述載體基板；以及在所述半導體晶粒的第二表面及所述絕緣層上形成第二重佈線層，所述第一表面與所述第二表面被定位成彼此相對。
根據本發明概念的一些示例性實施例，一種製造半導體裝置的方法可包括：提供載體基板；將半導體晶粒放置於所述載體基板上，以使所述半導體晶粒的主動表面面對所述載體基板；在所述載體基板上形成絕緣層，所述絕緣層環繞所述半導體晶粒；蝕刻所述絕緣層，以形成穿透所述絕緣層的通孔孔洞；形成晶種層，以覆蓋所述通孔孔洞的底表面及內側表面；形成填充所述通孔孔洞的通孔；在所述半導體晶粒及所述絕緣層上方形成第一重佈線層；移除所述載體基板，其中移除所述載體基板包括在移除所述載體基板時同時移除所述晶種層的一部分，所述晶種層的所述一部分位於所述通孔孔洞的所述底表面上；以及在所述半導體晶粒及所述絕緣層下方形成第二重佈線層。所述通孔孔洞的所述底表面可位於較所述半導體晶粒的所述主動表面的水平高度低且較所述絕緣層的底表面的水平高度低的水平高度處。
根據本發明概念的一些示例性實施例，一種半導體裝置可包括：下重佈線層；半導體晶粒，位於所述下重佈線層上；絕緣層，位於所述下重佈線層上，所述絕緣層環繞所述半導體晶粒；通孔，穿透所述絕緣層且耦合至所述下重佈線層的重佈線圖案；晶種層，位於所述通孔與所述絕緣層之間，所述晶種層環繞所述通孔的側表面；以及上重佈線層，位於所述絕緣層及所述半導體晶粒上，所述上重佈線層耦合至所述通孔。所述通孔的底表面相對於所述晶種層被暴露出。所述通孔可延伸至所述下重佈線層中。
現將結合附圖在以下闡述根據本發明概念的製造半導體裝置的方法。
圖1至圖22例示出顯示根據本發明概念一些示例性實施例的製造半導體裝置的方法的剖視圖。圖1至圖7、圖9至圖14、圖17至圖19、圖21及圖22例示出顯示根據本發明概念一些示例性實施例的製造半導體裝置的方法的剖視圖。圖8例示出顯示圖7所示區段A的放大圖。圖15及圖16例示出顯示圖14所示區段B的放大圖。圖20例示出顯示圖19所示區段C的放大圖。圖22例示出顯示根據本發明概念一些示例性實施例的半導體裝置的剖視圖。
參照圖1，可提供第一載體基板700。第一載體基板700可包括第一支撐基板710、導電層720及第一釋放層730。第一支撐基板710可為載體或設置於載體上的輔助工具。第一支撐基板710可由例如玻璃、塑料、金屬或任何其他合適的材料形成。導電層720可形成於第一支撐基板710上。可藉由對第一支撐基板710執行塗覆製程（coating process）或沈積製程（deposition process）來形成導電層720。導電層720可包含金屬，例如銅（Cu）。舉例而言，導電層720可為可拆離銅箔。第一釋放層730可形成於導電層720上。第一釋放層730可為雙面黏著膠帶（double-sided adhesive tape）或黏著層。當第一釋放層730是雙面黏著膠帶時，可採用真空疊層製程（vacuum lamination process）將第一釋放層730貼合至導電層720。當第一釋放層730是黏著層時，可塗覆黏著材料以形成第一釋放層730。
第一載體基板700可更包括設置於第一釋放層730上的壩件（dam）732。壩件732可具有自第一釋放層730向上突出的形狀。壩件732可界定在後續製程中在上面安裝半導體晶粒200的區。壩件732可包含與第一釋放層730的材料相同的材料。作為另外一種選擇，第一載體基板700可不包括壩件732。
根據圖2中所示的一些其他實施例，第一載體基板700’可包括導電基板715及第一釋放層730。導電基板715可足夠厚以用作第一支撐基板（參見圖1所示第一支撐基板710）及導電層（參見圖1所示導電層720）二者。導電基板715可包含選自鈦（Ti）及鉭（Ta）中的至少一者的材料。第一釋放層730可形成於導電基板715上。第一釋放層730可為雙面黏著膠帶或黏著層。以下內容將著重於圖1所示實施例。
參照圖3，可在第一載體基板700上設置半導體晶粒200。半導體晶粒200的主動表面可面對第一載體基板700。可在半導體晶粒200的主動表面上設置多個晶粒墊210。舉例而言，可將半導體晶粒200設置成使晶粒墊210接觸第一載體基板700的第一釋放層730。除非上下文另外指明，否則本文中使用的用語「接觸（contact）」是指直接連接（即，觸碰）。晶粒墊210可將半導體晶粒200的主動表面與第一釋放層730的頂表面隔開。晶粒墊210可設置於由壩件732界定的區中。舉例而言，可沿著半導體晶粒200的外邊緣對壩件732進行定位。
參照圖4，可在第一載體基板700上形成絕緣層300。可藉由在第一載體基板700上塗覆絕緣材料來形成絕緣層300。可在第一載體基板700上塗覆絕緣材料以覆蓋半導體晶粒200。絕緣層300可覆蓋半導體晶粒200的頂表面及側表面。壩件732可防止絕緣材料進入半導體晶粒200與第一載體基板700之間的空間。絕緣層300可具有與第一載體基板700面對的第一表面及與第一表面相對的第二表面。絕緣材料可包括絕緣聚合物，例如環氧模製化合物（epoxy molding compound，EMC）。
在一些其他實施例中，第一載體基板700可不包括壩件732。舉例而言，如圖5中所示，絕緣層300可填充第一載體基板700與半導體晶粒200之間的空間。絕緣材料可環繞晶粒墊210。以下內容將著重於圖4所示實施例。
根據本發明概念的一些示例性實施例，可將半導體晶粒200放置於第一載體基板700上，且接著可塗覆絕緣材料以形成絕緣層300。因此，可減少製程缺陷（例如在製造製程期間因絕緣層300的變形而對半導體晶粒200造成的損壞或者半導體晶粒200或絕緣層300自第一載體基板700的分層）。
參照圖6，可在絕緣層300中形成通孔孔洞VH。舉例而言，可在絕緣層300上形成罩幕圖案MP。當在平面中觀察時，罩幕圖案MP可具有在水平方向上與半導體晶粒200間隔開的圖案孔洞。可執行蝕刻製程，在蝕刻製程中使用罩幕圖案MP作為蝕刻罩幕，以在絕緣層300中形成通孔孔洞VH。通孔孔洞VH可被形成為具有隨著通孔孔洞VH接近第一載體基板700而逐漸減小的寬度。在蝕刻製程期間，可一同刻蝕第一載體基板700的第一釋放層730與絕緣層300。舉例而言，通孔孔洞VH可被形成為穿透絕緣層300且延伸至第一載體基板700中。通孔孔洞VH可穿透絕緣層300及第一釋放層730，進而暴露出導電層720。
參照圖7，可自圖6的所得結構移除罩幕圖案MP。
可在絕緣層300上形成晶種層SL。晶種層SL可共形地覆蓋絕緣層300。舉例而言，晶種層SL可被形成為覆蓋絕緣層300的頂表面。另外，可沿著通孔孔洞VH的底表面及內側表面形成晶種層SL。通孔孔洞VH的底表面可對應於導電層720的被暴露出的頂表面，且通孔孔洞VH的內側表面可對應於絕緣層300的內側壁及第一釋放層730的內側壁。舉例而言，如圖8中所示，在通孔孔洞VH中，晶種層SL的一部分SLa可接觸導電層720的頂表面。另外，在通孔孔洞VH中，晶種層SL可接觸絕緣層300的內側壁及第一釋放層730的內側壁。晶種層SL可包含金屬材料。舉例而言，晶種層SL可包含選自鈦（Ti）及鉭（Ta）中的至少一者的材料。晶種層SL與導電層720之間的邊界可能不可見，但本發明概念並非僅限於此。
在一些其他實施例中，第一載體基板700’可包括導電基板715及第一釋放層730。在此種情形中，如圖9中所示，在通孔孔洞VH中，晶種層SL可接觸導電基板715且亦可接觸絕緣層300的內側壁及第一釋放層730的內側壁。以下內容將著重於圖7所示實施例。
參照圖10，可在晶種層SL上形成抗蝕劑圖案RP。可在抗蝕劑圖案RP中形成溝槽T，以暴露出晶種層SL。溝槽T的至少一部分可與通孔孔洞VH交疊。舉例而言，溝槽T可在空間上連接至通孔孔洞VH。溝槽T可界定在後續製程中在其中形成第一上重佈線圖案516的區。
可在通孔孔洞VH及溝槽T中形成通孔410及第一上重佈線圖案516，進而覆蓋晶種層SL。可採用鍍覆製程來形成通孔410及第一上重佈線圖案516。舉例而言，可執行鍍覆製程，使得通孔孔洞VH及溝槽T被金屬材料填充，進而使得對通孔孔洞VH進行填充的金屬材料可構成通孔410，且對溝槽T進行填充的金屬材料可構成第一上重佈線圖案516。鍍覆製程可包括金屬無電鍍覆製程或金屬電鍍製程。鍍覆製程可使用晶種層SL作為電極。鍍覆製程的外部電力可連接至晶種層SL及導電層720。導電層720可厚於晶種層SL且可具有較晶種層SL的電阻小的電阻。因此，晶種層SL的位於通孔孔洞VH的底表面上的所述一部分SLa可自導電層720接收外部電力。
根據本發明概念，晶種層SL的位於通孔孔洞VH中的所述一部分SLa可自電阻低的導電層720接收電力，且因此可輕易地在通孔孔洞VH中執行鍍覆製程。因此，可避免缺陷（例如在鍍覆製程期間在通孔孔洞VH中的通孔410內產生空隙或者通孔孔洞VH中的導電材料填充失敗）。
第一上重佈線圖案516可填充溝槽T，但可不延伸至抗蝕劑圖案RP的頂表面上。因此，可不必單獨執行平坦化製程。基於通孔孔洞VH的形狀，通孔410可被形成為具有隨著通孔410接近第一載體基板700而逐漸減小的寬度。可選擇例如銅（Cu）等金屬作為在形成通孔410及第一上重佈線圖案516的鍍覆製程中使用的源材料。
根據本發明概念，在形成通孔410及第一上重佈線圖案516的製程中可不執行平坦化製程。因此，可防止平坦化製程對半導體晶粒200造成的損壞。
參照圖11，可移除抗蝕劑圖案RP，以暴露出晶種層SL的頂表面及第一上重佈線圖案516的上側壁。可移除晶種層SL的被暴露出的部分，以暴露出絕緣層300的頂表面。可執行蝕刻製程以移除晶種層SL。在蝕刻製程中，第一上重佈線圖案516可相對於晶種層SL具有蝕刻選擇性。因此，設置於第一上重佈線圖案516的底表面上的晶種層SL的未被暴露出的部分在蝕刻製程中可不被移除。設置於第一上重佈線圖案516的底表面上的晶種層SL的未被暴露出的部分可構成第一上晶種圖案514。晶種層SL的位於通孔孔洞VH中以及通孔410與絕緣層300之間的部分可構成通孔晶種層420。通孔晶種層420可插置於通孔410與絕緣層300之間，且在通孔410與導電層720之間可具有底部部分422。
參照圖12，可在絕緣層300上形成第一上介電層512。第一上介電層512可覆蓋第一上重佈線圖案516以及絕緣層300的頂表面。第一上重佈線圖案516的側表面可直接與第一上介電層512進行實體接觸。第一上介電層512可包含感光性聚合物。在本說明中，感光性聚合物可包括例如選自感光性聚醯亞胺（polyimide）、聚苯并噁唑（polybenzoxazole）、酚醛聚合物（phenolic polymer）及苯并環丁烯聚合物（benzocyclobutene polymer）中的至少一者。第一上介電層512、第一上晶種圖案514及第一上重佈線圖案516可構成第一上重佈線層510。
可在第一上重佈線層510上形成第二上重佈線層520。第二上重佈線層520的形成可類似於第一上重佈線層510的形成。舉例而言，可在第一上介電層512中形成孔洞。所述孔洞可暴露出第一上重佈線圖案516的頂表面。可在第一上介電層512上形成晶種層。晶種層可沿著孔洞的底表面及內側表面形成，同時覆蓋第一上介電層512的頂表面。可在晶種層上形成抗蝕劑圖案。抗蝕劑圖案可具有溝槽，所述溝槽界定在其中形成第二上重佈線圖案526的區。第二上重佈線圖案526可形成於孔洞及抗蝕劑圖案的溝槽中，進而覆蓋晶種層。之後，可移除抗蝕劑圖案，且可移除晶種層的被暴露出的部分，以形成第二上晶種圖案524。可在第一上介電層512上形成第二上介電層522，以覆蓋第二上重佈線圖案526。第二上介電層522可具有第一凹槽RS1，第一凹槽RS1暴露出第二上重佈線圖案526的頂表面。第二上介電層522、第二上晶種圖案524及第二上重佈線圖案526可構成第二上重佈線層520。第一上重佈線層510及第二上重佈線層520可構成上重佈線基板500且可具有與通孔410的電性連接。
如圖13中所示，可將圖12的所得結構定向成上下顛倒（即，「翻轉」）。舉例而言，在圖12的所得結構的此定向中，第一載體基板700位於絕緣層300上方，且半導體晶粒200的主動表面面朝上。另外，可在上重佈線基板500上設置第二載體基板800。第二載體基板800可包括第二支撐基板810及第二釋放層820。可使用第二釋放層820將第二支撐基板810貼合至第二上重佈線層520。第二支撐基板810可由例如玻璃、塑料、金屬或任何其他合適的材料形成。第二釋放層820可為雙面黏著膠帶或黏著層。
為易於說明，本文中可能使用例如「位於…上方（above）」、「上部的（upper）」、「位於…之下（beneath）」、「位於…下方（below）」、「下部的（lower）」等空間相對性用語來闡述圖中所例示的一個元件或特徵與另一（其他）元件或特徵的關係。應理解，所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。舉例而言，若圖中的裝置被顛倒，則被闡述為位於其他元件或特徵「下方」或位於其他元件或特徵「之下」的元件將被定向成位於所述其他元件或特徵「上方」。因此，用語「位於…下方」可囊括上方及下方兩種定向。裝置可具有其他定向（旋轉90度或處於其他定向），且本文中所使用的空間相對性描述語可相應地進行解釋。
可移除第一載體基板700的第一支撐基板710。可使用物理方法來移除第一支撐基板710。可移除第一支撐基板710以暴露出導電層720。
此後，可移除第一載體基板700的導電層720。當導電層720包括可拆離銅箔時，可以物理方式移除導電層720。作為另外一種選擇，可使用化學方法移除導電層720。移除導電層720可暴露出第一釋放層730。
如圖15中所示，通孔晶種層420可具有與導電層720接觸的底部部分422，且在移除導電層720時底部部分422可被同時移除。因此，通孔晶種層420可覆蓋通孔410的側表面且可不覆蓋通孔410的底表面410a。通孔晶種層420的端部可位於與通孔410的底表面410a的水平高度相同的水平高度處，且通孔410及通孔晶種層420可自絕緣層300的第一表面300a突出。
根據一些其他實施例，如圖16中所示，移除導電層720便可移除通孔晶種層420的一部分，所述一部分插置於通孔410與第一釋放層730之間。因此，通孔晶種層420可具有位於與絕緣層300的第一表面300a的水平高度相同的水平高度處的端部，且通孔410可自絕緣層300的第一表面300a突出。
參照圖17，可移除第一釋放層730。舉例而言，可使用物理方法或化學處理來移除第一釋放層730。在移除第一釋放層730時，可同時移除壩件732。移除第一釋放層730可暴露出絕緣層300的第一表面300a及半導體晶粒200的主動表面。
作為另外一種選擇，當使用圖5的實施例中所示的不包括壩件732的第一載體基板700製造半導體裝置時，可移除第一釋放層730以暴露出絕緣層300的第一表面300a及半導體晶粒200的晶粒墊210。
參照圖18，可形成第一下介電層112。第一下介電層112可覆蓋絕緣層300的第一表面300a及半導體晶粒200的主動表面。第一下介電層112可包含感光性聚合物。舉例而言，感光性聚合物可包括選自感光性聚醯亞胺、聚苯并噁唑、酚醛聚合物及苯并環丁烯聚合物中的至少一者。
可在第一下介電層112上形成第二凹槽RS2及第三凹槽RS3。舉例而言，可將第一下介電層112圖案化，以形成第二凹槽RS2及第三凹槽RS3。第二凹槽RS2可暴露出通孔410的底表面410a。第三凹槽RS3可暴露出半導體晶粒200的晶粒墊210。第二凹槽RS2可具有隨著接近絕緣層300而逐漸減小的寬度。第二凹槽RS2可具有寬度小於通孔410的底表面410a處的寬度的底表面。
參照圖19，可形成第一下晶種圖案114及第一下重佈線圖案116。舉例而言，可在第一下介電層112上形成晶種層。晶種層可沿著第二凹槽RS2及第三凹槽RS3的底表面及內側表面形成，同時覆蓋第一下介電層112。可在晶種層上形成抗蝕劑圖案。抗蝕劑圖案可具有溝槽，所述溝槽界定在其中形成第一下重佈線圖案116的區。第一下重佈線圖案116可形成於抗蝕劑圖案的溝槽中，進而覆蓋晶種層。之後，可移除抗蝕劑圖案，且可移除晶種層的被暴露出的部分，以形成第一下晶種圖案114。第一下介電層112、第一下晶種圖案114及第一下重佈線圖案116可構成第一下重佈線層110。
如圖20中所示，基於第二凹槽RS2的形狀，通孔410可在通孔410與第一下晶種圖案114之間的介面處具有較第一下晶種圖案114的寬度大的寬度。另外，通孔410的底表面410a處的寬度可大於第一下重佈線圖案116的底表面處的寬度。
參照圖21，可在第一下重佈線層110上形成第二下重佈線層120及第三下重佈線層130。第二下重佈線層120及第三下重佈線層130的形成可類似於第一下重佈線層110的形成。舉例而言，可在第一下介電層112上形成第二下介電層122，以覆蓋第一下重佈線圖案116及第一下晶種圖案114，且接著可形成第二下晶種圖案124及第二下重佈線圖案126以耦合至第一下重佈線圖案116。第二下介電層122、第二下晶種圖案124及第二下重佈線圖案126可構成第二下重佈線層120。可在第二下介電層122上形成第三下介電層132，以覆蓋第二下重佈線圖案126及第二下晶種圖案124，且接著可形成第三下晶種圖案134及第三下重佈線圖案136以耦合至第二下重佈線圖案126。第三下介電層132、第三下晶種圖案134及第三下重佈線圖案136可構成第三下重佈線層130。第一下重佈線層110、第二下重佈線層120及第三下重佈線層130可構成下重佈線基板100。應理解，當稱一元件「連接」至或「耦合」至另一元件或位於另一元件「上」時，所述元件可直接連接至或直接耦合至所述另一元件或者直接位於所述另一元件上，或者可存在中間元件。反之，當稱一元件「直接連接」至或「直接耦合」至另一元件時，不存在中間元件。
如圖22中所示，可將圖21的所得結構定向成上下顛倒。舉例而言，在圖22的所得結構的此定向中，下重佈線基板100位於絕緣層300下方，且半導體晶粒200的主動表面面朝下。可在下重佈線基板100上形成保護層142。保護層142可保護下重佈線基板100。保護層142可包含聚醯胺系聚合物材料或無機材料（例如氧化矽（SiOx）、氮化矽（SiNx）及氮氧化矽（SiON）），但本發明概念並非僅限於此。
可在保護層142上形成端子墊144。端子墊144可穿透保護層142以耦合至第三下重佈線圖案136。端子墊144可包含導電材料，例如金屬。
可在保護層142上設置外部端子150。舉例而言，外部端子150可放置於端子墊144上。可將外部端子150設置成使安裝於下重佈線基板100上的半導體晶粒200擱置於不同的基板上。外部端子150可包括焊料球或焊料凸塊。
此後，可移除第二載體基板800。舉例而言，可移除第二釋放層820以將第二支撐基板810自上重佈線基板500拆離。可藉由物理方法或化學處理移除第二釋放層820。
上述製程可製造根據本發明概念一些示例性實施例的半導體裝置。
圖22及圖23例示出顯示根據本發明概念一些示例性實施例的半導體裝置的剖視圖。
參照圖22，半導體裝置可包括下重佈線基板100、半導體晶粒200、絕緣層300、通孔410及上重佈線基板500。
下重佈線基板100可包括自頂部至底部依序設置的第一下重佈線層110、第二下重佈線層120及第三下重佈線層130。第一下重佈線層110、第二下重佈線層120及第三下重佈線層130可分別包括第一下介電層112、第二下介電層122及第三下介電層132，且亦可分別包括分別設置於第一下介電層112、第二下介電層122及第三下介電層132中的第一下重佈線圖案116、第二下重佈線圖案126及第三下重佈線圖案136。第一下重佈線圖案116、第二下重佈線圖案126及第三下重佈線圖案136可設置於第一下介電層112、第二下介電層122及第三下介電層132中，在第一下重佈線圖案116、第二下重佈線圖案126及第三下重佈線圖案136與第一下介電層112、第二下介電層122及第三下介電層132之間具有第一下晶種圖案114、第二下晶種圖案124及第三下晶種圖案134。下重佈線基板100可使用第一下重佈線層110、第二下重佈線層120及第三下重佈線層130來對發送至半導體晶粒200及自半導體晶粒200發送的訊號進行重佈線。
在下重佈線基板100下方可設置有保護層142。保護層142可覆蓋下重佈線基板100的第三下重佈線層130。在保護層142上可設置有端子墊144。端子墊144可穿透保護層142以耦合至第三下重佈線層130的第三下重佈線圖案136。
在保護層142上可設置有外部端子150。舉例而言，外部端子150可放置於端子墊144上。外部端子150可包括焊料球或焊料凸塊。
在下重佈線基板100上可安裝有半導體晶粒200。半導體晶粒200可被設置成使半導體晶粒200的主動表面面對下重佈線基板100的第一下重佈線層110。
半導體晶粒200可藉由晶粒墊210耦合至第一下重佈線層110的第一下晶種圖案114及第一下重佈線圖案116。
第一下重佈線層110的第一下介電層112可具有在半導體晶粒200下方向上突出且與半導體晶粒200的主動表面接觸的一部分。第一下介電層112可環繞晶粒墊210。
在下重佈線基板100上可設置有絕緣層300。絕緣層300可覆蓋下重佈線基板100的頂表面且可環繞半導體晶粒200。絕緣層300可覆蓋半導體晶粒200的側表面及頂表面。
根據一些其他實施例，如圖23中所示，半導體晶粒200可與下重佈線基板100的第一下介電層112間隔開。半導體晶粒200可藉由設置於第一下介電層112與半導體晶粒200之間的晶粒墊210耦合至第一下重佈線圖案116。絕緣層300可在半導體晶粒200與第一下介電層112之間延伸，以填充半導體晶粒200與第一下介電層112之間的空間。在半導體晶粒200與第一下介電層112之間，絕緣層300可環繞晶粒墊210。以下內容將著重於圖22所示實施例。
在絕緣層300中可設置有通孔410。通孔410可在半導體晶粒200的一側處垂直地穿透絕緣層300。通孔410可具有隨著通孔410接近下重佈線基板100而逐漸減小的寬度。通孔410可穿透絕緣層300且可突出至絕緣層300的底表面上。通孔410可延伸至下重佈線基板100的第一下介電層112中，進而耦合至第一下重佈線圖案116。第一下晶種圖案114可插置於通孔410與第一下重佈線圖案116之間。舉例而言，通孔410可具有與第一下晶種圖案114接觸的底表面。如圖20中所示，在通孔410與第一下晶種圖案114之間的介面處，通孔410可具有較第一下晶種圖案114的寬度大的寬度。另外，通孔410的底表面處的寬度可大於第一下重佈線圖案116的頂表面處的寬度。
在絕緣層300與通孔410之間可插置有通孔晶種層420。舉例而言，通孔晶種層420可環繞通孔410的側表面。通孔410的底表面可不被通孔晶種層420覆蓋，且可相對於通孔晶種層420被暴露出。為此，通孔410可直接接觸第一下晶種圖案114。
在絕緣層300上可設置有上重佈線基板500。上重佈線基板500可包括設置於絕緣層300上的第一上重佈線層510及第二上重佈線層520。第一上重佈線層510及第二上重佈線層520可分別包括第一上介電層512及第二上介電層522，且亦可分別包括分別設置於第一上介電層512及第二上介電層522中的第一上重佈線圖案516及第二上重佈線圖案526。第一上重佈線圖案516及第二上重佈線圖案526可設置於第一上介電層512及第二上介電層522中，在第一上重佈線圖案516及第二上重佈線圖案526與第一上介電層512及第二上介電層522之間具有第一上晶種圖案514及第二上晶種圖案524。第一上重佈線層510的第一上重佈線圖案516可耦合至通孔410。第二上重佈線層520的第二上介電層522可覆蓋第二上重佈線圖案526。第二上介電層522可具有第一凹槽RS1，第一凹槽RS1暴露出第二上重佈線圖案526的一部分。
可如上所述提供及配置半導體裝置。
作為另外一種選擇，當使用圖5的實施例中所示的不包括壩件732的第一載體基板700製造半導體裝置時，半導體晶粒200的主動表面可不接觸下重佈線基板100。如圖23中所示，絕緣層300可填充下重佈線基板100與半導體晶粒200的主動表面之間的空間，且半導體晶粒200可藉由晶粒墊210耦合至下重佈線基板100。舉例而言，在下重佈線基板100上，絕緣層300可覆蓋半導體晶粒200且可在半導體晶粒200與下重佈線基板100之間延伸。
圖24例示出顯示根據本發明概念一些示例性實施例的半導體裝置的剖視圖。
參照圖24，半導體裝置可包括下封裝10及上封裝20。下封裝10可由以上參照圖22論述的下重佈線基板100、半導體晶粒200、絕緣層300、通孔410及上重佈線基板500構成。
上封裝20可設置於下封裝10上。上封裝20可包括上封裝基板610、安裝於上封裝基板610上的上半導體晶粒620以及覆蓋位於上封裝基板610上的上半導體晶粒620的上模製層630。上封裝基板610可包括印刷電路板（PCB）或重佈線基板。上半導體晶粒620可以覆晶方式安裝於上封裝基板610上。舉例而言，上半導體晶粒620可藉由上晶粒凸塊622連接至上封裝基板610。另舉例而言，上半導體晶粒620可以配線接合方式安裝於上封裝基板610上。上模製層630可包含環氧模製化合物（EMC）。
上封裝20可包括設置於上封裝基板610下方的連接端子614。連接端子614可耦合至上封裝基板610的基板墊，且可耦合至下封裝10中所包括的上重佈線基板500的第二上重佈線圖案526，所述第二上重佈線圖案526被暴露至第一凹槽RS1。舉例而言，上封裝20可藉由連接端子614耦合至上重佈線基板500，且上重佈線基板500可對上封裝20進行重佈線以具有與通孔410的電性連接。
根據本發明概念一些示例性實施例的製造半導體裝置的方法可包括：將半導體晶粒放置於載體基板上，且接著塗覆絕緣材料以形成絕緣層。因此，可減少製程缺陷（例如在製造製程期間因絕緣層的變形而對半導體晶粒造成的損壞或者半導體晶粒或絕緣層自載體基板的分層）。
根據本發明概念，晶種層可具有位於通孔中的一部分，且晶種層的所述一部分可自電阻低的導電層接收電力，因此可輕易地在通孔孔洞中執行鍍覆製程。因此，可避免缺陷（例如在鍍覆製程期間在通孔孔洞中的通孔內產生空隙或者通孔孔洞中的導電材料填充失敗）。
根據本發明概念，在形成通孔及上重佈線圖案的製程中可不執行平坦化製程。因此，可防止平坦化製程對半導體晶粒造成的損壞。
儘管已結合附圖中所例示的本發明概念的示例性實施例闡述了本發明概念，然而此項技術中具有通常知識者應理解，在不背離本發明概念的精神及本質特徵的條件下，可對其進行形式及細節上的變化。因此，以上揭露的實施例應被視為例示性的，而非限制性的。
10:下封裝 20:上封裝 100:下重佈線基板 110:第一下重佈線層 112:第一下介電層 114:第一下晶種圖案 116:第一下重佈線圖案 116a:底表面 120:第二下重佈線層 122:第二下介電層 124:第二下晶種圖案 126:第二下重佈線圖案 130:第三下重佈線層 132:第三下介電層 134:第三下晶種圖案 136:第三下重佈線圖案 142:保護層 144:端子墊 150:外部端子 200:半導體晶粒 210:晶粒墊 300:絕緣層 300a:第一表面 300b:第二表面 410:通孔 410a:底表面 420:通孔晶種層 422:底部部分 500:上重佈線基板 510:第一上重佈線層 512:第一上介電層 514:第一上晶種圖案 516:第一上重佈線圖案 520:第二上重佈線層 522:第二上介電層 524:第二上晶種圖案 526:第二上重佈線圖案 610:上封裝基板 614:連接端子 620:上半導體晶粒 622:上晶粒凸塊 630:上模製層 700、700’:第一載體基板 710:第一支撐基板 715:導電基板 720:導電層 730:第一釋放層 732:壩件 800:第二載體基板 810:第二支撐基板 820:第二釋放層 A、B、C:區段 MP:罩幕圖案 RP:抗蝕劑圖案 RS1:第一凹槽 RS2:第二凹槽 RS3:第三凹槽 SL:晶種層 SLa:一部分 T:溝槽 VH:通孔孔洞
圖1至圖22例示出顯示根據本發明概念一些示例性實施例的製造半導體裝置的方法的剖視圖。
圖22及圖23例示出顯示根據本發明概念一些示例性實施例的半導體裝置的剖視圖。
圖24例示出顯示根據本發明概念一些示例性實施例的半導體裝置的剖視圖。
100:下重佈線基板
110:第一下重佈線層
112:第一下介電層
114:第一下晶種圖案
116:第一下重佈線圖案
120:第二下重佈線層
122:第二下介電層
124:第二下晶種圖案
126:第二下重佈線圖案
130:第三下重佈線層
132:第三下介電層
134:第三下晶種圖案
136:第三下重佈線圖案
142:保護層
144:端子墊
150:外部端子
200:半導體晶粒
210:晶粒墊
300:絕緣層
410:通孔
420:通孔晶種層
500:上重佈線基板
510:第一上重佈線層
512:第一上介電層
514:第一上晶種圖案
516:第一上重佈線圖案
520:第二上重佈線層
522:第二上介電層
524:第二上晶種圖案
526:第二上重佈線圖案
RS1:第一凹槽

Claims (20)

  1. 一種製造半導體裝置的方法，所述方法包括： 提供載體基板，所述載體基板包括導電層； 將半導體晶粒放置於所述載體基板上； 形成絕緣層，以覆蓋所述載體基板上的所述半導體晶粒； 形成通孔孔洞，以在所述半導體晶粒的一側處穿透所述絕緣層並暴露出所述載體基板的所述導電層； 執行鍍覆製程，在所述鍍覆製程中使用所述載體基板的所述導電層作為晶種來形成對所述通孔孔洞進行填充的通孔； 在所述半導體晶粒的第一表面及所述絕緣層上形成第一重佈線層； 移除所述載體基板；以及 在所述半導體晶粒的第二表面及所述絕緣層上形成第二重佈線層，所述第一表面與所述第二表面被定位成彼此相對。
  2. 如請求項1所述的方法，更包括： 在執行所述鍍覆製程之前，形成覆蓋所述通孔孔洞的底表面及內側表面的晶種層。
  3. 如請求項2所述的方法，其中所述晶種層包括位於所述通孔孔洞的所述底表面上的第一部分及位於所述通孔孔洞的所述內側表面上的第二部分， 其中在移除所述載體基板時所述晶種層的所述第一部分被同時移除。
  4. 如請求項1所述的方法，其中所述鍍覆製程利用被施加至所述載體基板的所述導電層的電力。
  5. 如請求項1所述的方法，其中在移除所述載體基板之後所述通孔的底表面被暴露出。
  6. 如請求項1所述的方法，其中所述通孔孔洞延伸至所述載體基板中。
  7. 如請求項6所述的方法，其中所述通孔的底表面突出超過所述絕緣層的所述第二表面。
  8. 如請求項1所述的方法，其中形成所述第二重佈線層包括： 在所述半導體晶粒的所述第二表面及所述絕緣層上形成介電層； 形成圖案孔洞，以穿透所述介電層並暴露出所述通孔的底表面； 在所述通孔孔洞中形成晶種圖案，以接觸所述通孔的所述底表面；以及 在所述晶種圖案上形成重佈線圖案。
  9. 如請求項8所述的方法，其中，在所述通孔與所述晶種圖案之間的介面處，所述通孔的寬度大於所述晶種圖案的寬度。
  10. 如請求項1所述的方法，其中 所述半導體晶粒的所述第二表面是主動表面，且 所述半導體晶粒的多個晶粒墊電性連接至所述第二重佈線層。
  11. 如請求項10所述的方法，其中 所述載體基板包括位於所述載體基板的頂表面上的壩件， 在移除所述載體基板之前，所述載體基板環繞位於所述半導體晶粒下方的所述晶粒墊， 所述晶粒墊的底表面位於與所述絕緣層的底表面的水平高度相同的水平高度處，且 在形成所述第二重佈線層期間，所述第二重佈線層的介電層填充所述絕緣層與所述晶粒墊之間的空間。
  12. 一種製造半導體裝置的方法，所述方法包括： 提供載體基板； 將半導體晶粒放置於所述載體基板上，以使所述半導體晶粒的主動表面面對所述載體基板； 在所述載體基板上形成絕緣層，所述絕緣層環繞所述半導體晶粒； 蝕刻所述絕緣層，以形成穿透所述絕緣層的通孔孔洞； 形成晶種層，以覆蓋所述通孔孔洞的底表面及內側表面； 形成填充所述通孔孔洞的通孔； 在所述半導體晶粒及所述絕緣層上方形成第一重佈線層； 移除所述載體基板，其中移除所述載體基板包括在移除所述載體基板時同時移除所述晶種層的一部分，所述晶種層的所述一部分位於所述通孔孔洞的所述底表面上；以及 在所述半導體晶粒及所述絕緣層下方形成第二重佈線層， 其中所述通孔孔洞的所述底表面位於較所述半導體晶粒的所述主動表面的水平高度低且較所述絕緣層的底表面的水平高度低的水平高度處。
  13. 如請求項12所述的方法，其中 所述載體基板包括導電層，且 所述通孔孔洞被形成為穿透所述絕緣層且暴露出所述載體基板的所述導電層。
  14. 如請求項13所述的方法，其中 所述晶種層接觸所述載體基板的所述導電層，且 形成所述通孔包括執行鍍覆製程，在所述鍍覆製程中使用所述導電層及所述晶種層作為晶種。
  15. 如請求項12所述的方法，其中在移除所述載體基板之後所述通孔的底表面被暴露出，且 其中所述通孔的所述底表面接觸所述第二重佈線層的重佈線圖案。
  16. 如請求項12所述的方法，其中所述通孔突出超過所述絕緣層的所述底表面。
  17. 如請求項12所述的方法，其中形成所述第二重佈線層包括： 形成介電層，以覆蓋所述半導體晶粒的所述主動表面及所述絕緣層的所述底表面； 蝕刻所述介電層，以形成暴露出所述通孔的圖案孔洞； 在所述圖案孔洞中形成晶種圖案，以接觸所述通孔；以及 在所述晶種圖案上形成重佈線圖案。
  18. 一種半導體裝置，包括： 下重佈線層； 半導體晶粒，位於所述下重佈線層上； 絕緣層，位於所述下重佈線層上，所述絕緣層環繞所述半導體晶粒； 通孔，穿透所述絕緣層且耦合至所述下重佈線層的重佈線圖案； 晶種層，位於所述通孔與所述絕緣層之間，所述晶種層環繞所述通孔的側表面；以及 上重佈線層，位於所述絕緣層及所述半導體晶粒上，所述上重佈線層耦合至所述通孔， 其中所述晶種層的底表面相對於所述晶種層被暴露出，且 其中所述通孔延伸至所述下重佈線層中。
  19. 如請求項18所述的半導體裝置，其中所述通孔的所述底表面位於較所述絕緣層的底表面的水平高度低且較所述半導體晶粒的底表面的水平高度低的水平高度處。
  20. 如請求項18所述的半導體裝置，其中所述上重佈線層包括： 介電層，覆蓋所述絕緣層的底表面及所述半導體晶粒的底表面； 所述重佈線圖案，穿透所述介電層且耦合至所述通孔；以及 晶種圖案，位於所述重佈線圖案與所述通孔的所述底表面之間，所述晶種圖案接觸所述通孔的所述底表面。
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