TW202137712A - Two-capacitor digital-to-analog converter - Google Patents

Abstract

A two-capacitor digital-to-analog converter circuit having circuitry to compensate for an unwanted capacitance is disclosed. The converter is configured to generate an average voltage on two capacitors for a sequence of bits in a digital word so that when the final bit is reached, the average voltage corresponds to an analog level of the digital word. The converter is configured to input and average the voltage on the two capacitors using different modes to minimize the effects of capacitor mismatch and switching capacitance on the accuracy of the conversion. The converter includes a buffer amp that has an input capacitance that can affect the conversion. Accordingly, the converter further includes capacitance compensation circuitry configured to provide a replica input capacitance that can be charged and discharged according to the bits of the digital word and coupled to the input capacitor to prevent the input capacitance from affecting the conversion.

Description

Dual-capacitor digital-to-analog converter

This disclosure is about integrating analog and digital circuits, and more specifically about circuits and methods for digital-to-analog conversion.

Electronic systems may require digital-to-analog converters (DAC) to convert digital signals into corresponding analog signals. For example, the DAC may allow a set of digits to be used to set the output voltage level. Specifically, the DAC can be configured to receive each binary bit (b ₀ , b ₁ , …b _N-1 ) and the reference voltage (V _REF ) of the N-bit binary word group, and output the output voltage ( V _O ). In other words, the DAC can be configured to divide the range defined by the reference voltage into a plurality of levels, each corresponding to possible digit words in the range of possible digit words for a given resolution. To achieve this, the DAC may include a network of resistors or capacitors coupled by switches. The switch can be turned on/off controlled by the bits of the binary word group to output voltages of various levels. The capacitor network can be better than the resistor network due to its lower loss, but it can be limited due to its large size and poor accuracy at high resolution (N ≥ 10). Therefore, it is necessary to use a DAC with a capacitor network with improved size and accuracy. This is the background of the implementation of this disclosure.

In at least one aspect, the present disclosure generally describes a dual-capacitor digital-to-analog converter circuit (ie, 2C-DAC). The 2C-DAC circuit includes a stage and mode controller configured to set an action bit in a digital word group, select a mode condition of the action bit, and based on the action bit A value of the element and the selected mode status are switched according to a first mode or a second mode configuration of a conversion process. The 2C-DAC circuit further includes a redistribution switch configured to couple the first capacitor and the second capacitor together to generate an average voltage during an averaging phase of the conversion process. The 2C-DAC circuit further includes a buffer amplifier having an input capacitance at an input. The buffer amplifier is configured to generate an output voltage based on the average voltage. The 2C-DAC further includes a capacitance compensation circuit, and the capacitance compensation circuit includes a duplicate input capacitance. The capacitance compensation circuit is configured to couple a reference voltage or a ground to the duplicate input capacitor based on the value of the action bit during an input phase of the conversion process. The capacitance compensation circuit is further configured to couple the duplicate input capacitance to the input capacitance during the averaging phase of the conversion procedure to adjust the average voltage.

In another aspect, the present disclosure generally describes a method for digital-to-analog conversion. The method includes receiving a digit word group, setting an action bit of the digit word group, selecting a mode status of the action bit, and determining for the action based on a value of the action bit and the selected mode status A first mode or a second mode of bits. The method further includes performing an input phase including a first mode and a second mode. In a first mode of the input stage, a first capacitor and a duplicate input capacitor are charged or discharged according to the value of the action bit. In a second mode of the input stage, a second capacitor and a duplicate input capacitor are charged or discharged according to the value of the action bit. The method further includes performing an averaging phase including coupling the first capacitor and the second capacitor together to generate an average voltage for the active bit. The averaging stage further includes coupling the average voltage to a buffer amplifier having an input capacitance, and coupling the duplicate input capacitance and an input capacitance together to generate a bit for the action at an input of the buffer amplifier Yuan's adjusted average voltage.

In another aspect, the present disclosure generally describes a system for digital-to-analog conversion. The system includes a stage and mode controller that is configured to receive a bit of a digital block and according to an input stage, an average stage, or an output stage of a conversion process and according to the A first mode or a second mode output switching signal determined by each bit in the digit word group received at an input to the system. The system further includes an averaging circuit including a first capacitor and a second capacitor. The averaging circuit is configured to charge or discharge the first capacitor or the second capacitor during an input phase, and is configured to couple the first capacitor and the second capacitor together during an averaging phase To generate an average voltage. The system further includes an output circuit including an input capacitor. The output circuit is configured to generate an output voltage based on the average voltage received from the averaging circuit, and is configured to couple the output voltage to an output of the system during the output phase. The system further includes a capacitance compensation circuit including a duplicate input capacitance substantially equal to the input capacitance. The capacitance compensation circuit is configured to couple the duplicate input capacitance and the input capacitance together during an averaging phase to adjust the average voltage to compensate the input capacitance.

The foregoing illustrative invention content, other exemplary purposes and/or advantages of the present disclosure, and ways to achieve them are further explained in the following embodiments and accompanying drawings.

[Cross-reference of related applications]

This application claims the priority of U.S. Provisional Patent Application No. 62/979,472 filed on February 21, 2020 and U.S. Provisional Patent Application No. 62/979,474 filed on February 21, 2020.

This disclosure describes a double-capacitor DAC, which can provide high-resolution conversion of low-frequency and wide-band signals with high accuracy. Compared with other DACs based on capacitor networks, such as binary weighted capacitor network DAC or ladder capacitor network (ie, C-2C network) DAC, the disclosed DAC can be used in a smaller area integrated circuit It is manufactured and does not need to be calibrated for accurate performance at high resolution. Additionally, the disclosed DAC provides alternate operation modes and circuitry to compensate for the inaccuracy caused by the actual implementation.

The binary weighted capacitor network DAC includes a capacitor bank (each bank has a specific capacitance), and the capacitor bank can turn on/off the coupling to the reference voltage according to the binary input to generate a specific output voltage. One problem with this method is the number of capacitors required for high-resolution (N ≥ 10) applications. A large number of capacitors can produce a network that is too complex or too large for the actual implementation. In addition, problems that scale with the number of capacitors in the network (such as leakage, mismatch, etc.) can also limit the resolution of binary weighted capacitors that can be implemented in practice. The disclosed DAC uses only two capacitors, and therefore can be physically smaller than the corresponding binary weighted capacitor DAC. Additionally, two capacitors can be nominally the same capacitance (for example, 1:1 ratio); therefore, the range between the largest capacitor in the network and the smallest capacitor in the network (ie, the capacitor distribution ratio) can be smaller. Furthermore, because of the redistribution of charge between the two capacitors in the disclosed DAC network, the capacitor mismatch can be effectively eliminated. Therefore, the disclosed DAC can also have a smaller capacitor mismatch than a binary weighted capacitor network, and therefore can be more accurate (eg, linear, monotonic).

The C-2C network DAC can be simpler and smaller than the binary weighted capacitor network DAC, but can still be complex and large in order to provide linear performance at high resolution. The linearity of the C-2C network DAC can be affected by the parasitic capacitance at the nodes in the ladder network. To compensate for parasitic capacitance, the C-2C DAC may require memory (for example, RAM) for storage and recall of digital correction items (for example, obtained through calibration) and/or may need to self-calibrate and trim the capacitor array. In either case, the circuitry used to compensate for parasitic effects can make the C-2C DAC more complex and larger. The disclosed DAC uses only two capacitors, and therefore can be physically smaller than the corresponding C-2C network DAC. Furthermore, because of the redistribution of charge between the two capacitors in the disclosed DAC network, the nonlinearity caused by the parasitic capacitance can be effectively eliminated. Therefore, the disclosed DAC may not require calibration or trimming capacitor arrays for linear performance at high resolution.

The advantages of the disclosed DAC capacitor network may come at the price of its speed. For binary weighted capacitor DAC or C-2C DAC, the bits of the digit block can be applied to the capacitor network in parallel to obtain the corresponding output signal. However, in the disclosed DAC capacitor network, the bits of the digit block are applied in sequence (serial), and the least significant bit (LSB) must be processed before the corresponding output signal can be obtained. All bits up to the most significant bit (MSB).

The trade-off between performance and speed may be acceptable for applications that do not require high-speed conversion. For example, some biomedical applications (eg, glucose monitoring and sensing) may require a DAC as part of a programmable bias circuit. These applications may require accurate and low power consumption DACs, but may not require DACs with high speeds. The disclosed DAC is very suitable for these applications because it can operate with high resolution (for example, ≥ 10 bits), has low power consumption, has a simple (that is, small) layout, and is highly linear (for example, for integral Non-linearity or differential non-linearity ≤ ±1 LSB), and can provide rail-to-rail output.

To explain its ideal operation, a simplified two-capacitor DAC is shown in Figure 1A. The capacitors (C ₁ , C ₂ ) may have substantially the same capacitance, so that the ratio of capacitance may be approximately 1:1. For conversion, the double-capacitor DAC is configured to receive each bit (b _i ) of the digit block (B) in a sequence from LSB to MSB. The average voltage (V _AVG ) can be generated for each bit in the sequence, so that the final average voltage of the sequence corresponds to the output voltage (V _O ) of the analog level of the digit block (B). The average voltage is the voltage generated by redistributing the charge difference between capacitors charged to different voltages. When the redistribution is equal, the voltage on the capacitors after the redistribution is approximately the average of the voltages on the capacitors before the redistribution. This is the term "average" used in this article, but this disclosure recognizes the background that variation may exist (for example, if the redistributions are not equal). Therefore, the average voltage generated for each cell (ie, redistributed voltage) can generally refer to the voltage between the voltages on the capacitors before redistribution (for example, the number of midranges, the number of offset midranges, the weighted average, etc.) , Not a specific mathematical relationship. Each average voltage of the sequence is calculated using two stages: the input stage and the average stage (that is, the redistribution stage). The output phase occurs after the final average voltage calculation of the sequence. The table of the switch status of each stage is shown in Table 1 below.

surface 1 : Simple double capacitor DAC Example of the switch state stage S ₀ S ₁ S _AVG S _OUT enter (b _i = 0) Conduction Turn off Turn off Turn off enter (b _i = 1) Turn off Conduction Turn off Turn off Averaging Turn off Turn off Conduction Turn off Output Turn off Turn off Turn off Conduction

When the input bit (b _i ) is logic 1, the upper bit input switch (ie, a switch (S ₁ )) can be configured to couple the first capacitor (C ₁ ) to the reference voltage (V _REF ), and when the input bit (b _i ) is logic 0, the lower bit input switch (ie, zero switch (S ₀ )) can be configured to couple the first capacitor (C ₁ ) to the ground voltage (For example, 0V). A switch (S ₁ ) and a zero switch (S ₀ ) are switched in a complementary manner, so that when a switch (S ₁ ) is closed, the zero switch (S ₀ ) is opened, and vice versa. Based on the state of the switch, the first capacitor (C ₁ ) is charged or discharged during the input phase of the DAC conversion procedure. In the averaging phase of the DAC conversion procedure, the averaging switch (S _AVG ) (for example, the redistribution switch) is configured to couple the first capacitor (C ₁ ) and the second capacitor (C ₂ ) together so that the capacitor The total stored charge is equally redistributed. Before the output phase, the input phase and the averaging phase are repeated for each bit of the digit block. In the output stage of the DAC conversion procedure, the output switch (S _OUT ) is configured to couple the second buffer amplifier 110 to the output of the DAC. The redistributed charge (ie, the average voltage) on the second capacitor (C ₂ ) produces an input voltage at the input to the buffer amplifier 110, which is configured to be at the output (ie, the double-capacitor DAC output) Generate output voltage (V _O ). The buffer amplifier can be a single gain amplifier, so that the average voltage (V _{AVG ) becomes the output voltage (V O} ) of the double-capacitor DAC in the output stage.

FIG. 1B shows the display of the binary block 101 (that is, 5) in the range of the binary block from 000 (that is, 0) to 111 (that is, 7), which is shown in FIG. 1A A graph of the output voltage (V _AVG ) of the double-capacitor DAC. For LSB (ie, b ₀ ), the first capacitor is charged to the reference voltage (V _REF ) during the input phase. Second, the charge is then divided equally between the capacitors in the averaging phase, so that the average voltage (V _AVG ) of _{b 0 is V REF} /2 (ie, 4/8V _REF ). For the next effective bit (b ₁ ), the first capacitor (C ₁ ) is discharged to ground during the input phase. Second, the remaining charge is equally divided between the capacitors in the averaging phase, so that the average voltage (V _AVG ) is discharged to _{a voltage halfway between V REF} /2 and ground (ie, 2/8 V _REF ). For the most significant bit (b ₂ ), the first capacitor (C ₁ ) is charged to V _REF . Second, the charge is equally divided between the capacitors in the averaging phase, so that the average voltage (V _AVG ) is charged to a voltage _{halfway between the previous output voltage and V REF} (ie, 5/8V _REF ). Therefore, the average voltage develops through the bits from LSB to MSB and ends _{at the output voltage (V O) corresponding to the digital value.} Therefore, the entire group of digits can be processed sequentially to reach the appropriate converted analog value.

The performance (for example, accuracy) of the double-capacitor DAC can be characterized by its integral nonlinearity and its differential nonlinearity. The difference between the actual DAC output and the ideal DAC output of the integral nonlinearity (INL) coefficient bit input. The differential non-linearity (DNL) coefficient bit is the difference between the actual step size and the ideal step size of the step size between inputs (for example, the step size between 000 and 001). In some applications, INL and DNL are less than ±1LSB as desired. When these conditions are met, the DAC can be said to be monotonic. In addition to the capacitor mismatch, the actual implementation of the two-capacitor DAC shown in FIG. 1A may have additional (ie, undesired) capacitance that can cause performance degradation. Further, the extra capacitance can limit the rail-to-rail operation of the dual-capacitor DAC. The disclosed dual-capacitor DAC utilizes methods and circuit systems to reduce or eliminate additional capacitance to improve performance, so that the dual-capacitor DAC is monotonic and can operate rail-to-rail.

One source of extra capacitance is caused by the actual implementation of the switches (for example, S ₀ , S _{1) used in the input stage. For example, the first switch (S 1} ) of the double-capacitor DAC shown in FIG. 1A can be implemented as a transistor (eg, MOSFET) that includes a small capacitance (eg, gate capacitance, C _{GS) that is charged during operation.} The charge stored in this small capacitor can change (for example, reduce) the charge stored in the capacitor (C ₁ ) during the input phase. For short binary blocks (for example, N<10), the change in charge can be relatively small, so that at the end of the sequence of binary bits, the final output voltage does not change significantly from its ideal level. In other words, the performance has not deteriorated significantly. However, for long binary blocks (that is, high resolution), the cumulative effect of the charge change caused by the switched capacitor can degrade the performance of the double-capacitor DAC. The disclosed double-capacitor DAC uses method and circuit system to reduce the effect of switching capacitors to improve performance.

Another source of the extra capacitance in the actual implementation is the buffer amplifier 110. The buffer amplifier 110 may be implemented as an operational amplifier (ie, opamp) having an input capacitance. For example, the input stage of a buffer amplifier (eg, operational amplifier) may include a transistor (eg, MOSFET) _{with a capacitance (eg, gate capacitance, C GS) associated with its operation.} The input capacitance can change (for example, lower) the level of charge output from the two capacitors. _{Therefore, the output voltage (V O} ) at the output of the double-capacitor DAC may be less accurate to a level corresponding to the determined ratio of the input capacitance of the buffer amplifier to the first capacitor C ₁ and the second capacitor C _2. Because the input capacitance can vary according to the voltage at the input of the buffer amplifier 110, the accuracy of the double-capacitor DAC can vary according to the binary block input. The disclosed double-capacitor DAC utilization method and circuit system can reduce the effect of buffer amplifier input capacitance and its variation to improve performance.

FIG. 2 is a schematic diagram of a double-capacitor DAC (ie, 2C-DAC) circuit according to a first possible implementation of the present disclosure. The 2C-DAC circuit 200 (ie, the circuit) includes a plurality of switches that configure the circuit for a digital conversion program. As mentioned earlier, the digital conversion of binary (ie, digital) blocks is performed by calculating the average voltage (V _AVG ) of each bit. For example, the first average voltage can be calculated based on the least significant bit of the binary block, and then continuously updated until all the bits of the digital block have been processed (ie, to the MSB). The final average voltage is at the level corresponding to the digit block and is coupled to the output of the DAC as the output voltage (V _O ). The average voltage obtained for each element is calculated using the input phase and the average phase. The 2C-DAC circuit is configured for each stage of the conversion process by controlling a plurality of switches. The switch may be implemented as a transistor device (eg, NMOS transistor and/or PMOS transistor).

The 2C-DAC includes a first set of input switches (S _{1_C1} , S _{0_C1} ), which can be configured to charge/discharge the _{first capacitor (C 1) during the input phase.} The configuration of the switch is based on the bits of the binary word group. For example, if the bit of the _{digit string} is 1, the switch S 1_C1 is turned on (that is, conductive) and the switch S _{0_C1 is} turned off (that is, not conductive), and vice versa when the current bit is zero. The 2C-DAC further includes a second set of input switches (S _{1_C2} , S _{0_C2} ), which can be configured to charge/discharge the second capacitor during the input phase. The configuration of the second group of switches can also be based on the bits of the binary word group. For example, if the bit is 1, the switch S _{1_C2} is on and the switch S _{0_C1 is} off, and when the bit is zero, the opposite is true.

During the input phase, only one set of input switches is valid for each bit of the digit block. For example, some bits of the digital word group can be input using the first group of input switches (S _{1_C1} , S _{0_C1} ), and other bits of the digital word group can be input using the second group of input switches (S _{1_C2} , S _{0_C2} ). The choice of using the first group or the second group for the input stage is determined by the mode of the 2C-DAC circuit.

The 2C-DAC circuit can operate in one of two modes. In the first mode (ie, Mode1), the first set of input switches (S _{1_C1} , S _{0_C1} ) is used, and in the second mode (ie, Mode2), the second set of input switches (S _{1_C2} , S _{0_C2} ). The 2C-DAC further includes a set of coupling switches (S _{C_C1} , S _{C_C2} ), which are configurable in the input phase to connect the first capacitor (C ₁ ) or the second capacitor (C ₂ ) One is coupled to the buffer amplifier 210. _{The selection of the} first capacitor coupling switch (S C_C1) or the second capacitor coupling switch (S _{C_C2} ) can be determined by the mode of the conversion program. For example, in the first mode (ie, Mode1), the first capacitor (C ₁ ) may be charged in the input phase, and the second capacitor (C ₂ ) may be coupled to the buffer amplifier 210 in the input phase. In the second mode (ie, Mode ₂ ), the second capacitor (C 2) can be charged in the input phase, and the first capacitor (C ₁ ) can be coupled to the buffer amplifier 210 in the input phase. Switching in this manner alternates between charging/discharging during the input phase and the capacitor coupled to the buffer amplifier 210 during the input phase. By alternately coupling in this way, the effect of capacitor mismatch can be reduced, and the efficiency of DAC conversion can be increased (for example, accuracy, linearity). Table 2 illustrates an example switch state of the input stage according to a possible implementation of the present disclosure. Other switches not mentioned in Table 2 can be turned off during the input phase.

surface 2 : Instance switch state of the input stage To bi=1, MODE 1 bi=0, MODE1 bi=1, MODE2 bi=0, MODE2 S _{1_C1} Conduction Turn off Turn off Turn off S _{0_C1} Turn off Conduction Turn off Turn off S _{1_C2} Turn off Turn off Conduction Turn off S _{0_C2} Turn off Turn off Turn off Conduction S _{C_C1} Turn off Turn off Conduction Conduction S _{C_C2} Conduction Conduction Turn off Turn off

The 2C-DAC further includes an averaging switch (ie, a redistribution switch). After one of the first capacitor (C ₁ ) or the second capacitor (C ₂ ) is charged/discharged during the input phase, the averaging phase can start. In the averaging phase, the averaging switch S _AVG can be turned on, and the input switch can be turned off. The averaging switch can be used in the averaging phase regardless of the mode. When the average switch S _{AVG is} turned on _, the charges in the first capacitor (C ₁ ) and the second capacitor (C ₂ ) can be equalized to an average value. Therefore, the voltage on each capacitor can be substantially the same (for example, equal) at the end of the averaging phase.

The set of coupling switches (S _{C_C1} , S _{C_C2} ) can be configured in the averaging phase to couple both the first capacitor (C ₁ ) and the second capacitor (C ₂ ) to the buffer amplifier. For example, in the first mode (ie, Mode1), the first capacitor (C ₁ ) can be charged in the input phase, and the first capacitor (C ₁ ) and the second capacitor (C ₂ ) can be coupled in the average phase Connected together and coupled to the buffer amplifier. In the second mode (ie Mode2), the second capacitor (C ₂ ) can be charged in the input phase, and the first capacitor (C ₁ ) and the second capacitor (C ₂ ) can be coupled in the averaging phase Together and coupled to the buffer amplifier. Switching in this way alternates the capacitors charged/discharged during the input phase and couples the two capacitors to the buffer amplifier during the averaging phase. By switching in this way, the effect of capacitor mismatch can be reduced, and the efficiency of DAC conversion can be increased (for example, accuracy, linearity). Table 3 illustrates an example switch state of the average phase according to a possible implementation of the present disclosure. Other switches not mentioned in Table 3 can be turned off during the average phase.

surface 3 : Instance switch state of the average phase To MODE 1 MODE2 S _AVG Conduction Conduction S _{C_C1} Conduction Conduction S _{C_C2} Conduction Conduction

The 2C-DAC may further include a buffer amplifier 110 implemented as an operational amplifier 210 (ie, opamp). The operational amplifier 210 may be configured for a single gain, so that in the output phase, the output voltage (V _O ) may be approximately equal to the average voltage after the charge has been redistributed between the first capacitor and the second capacitor. The output voltage (V _O ) of the operational amplifier can be a voltage in the range determined by the upper rail voltage and the lower rail voltage supplied to the operational amplifier. In one possible implementation, the operational amplifier can be configured for rail-to-rail operation so that the output voltage (V _O ) can be in the range from the ground voltage to the reference voltage (V _REF ).

By alternating the pattern during the conversion, the capacitor charged/discharged during the input phase can be changed. This change can minimize the effects of capacitor mismatch and undesired capacitance (for example, switching capacitance) that _{negatively affect the accuracy of the V O of a given location element.} Therefore, the disclosed 2C-DAC may have improved accuracy. This improved accuracy is especially important for high-resolution (high-bit depth) applications where the output voltage range is sub-divided into sub-ranges to represent each possible bit combination in the digit block. For example, the rail-to-rail output voltage range of 0 to 5V must be divided into 32 sub-ranges to represent 5-bit digit blocks, which only provides a sub-range of approximately 156 mV for each possible bit. As the number of bits in a digit block increases, higher accuracy is required. The disclosed 2C-DAC can provide high-resolution processing (N-byte characters, N ≥ 10) accuracy.

(1)

(2)The mode selection can be based on the mode status of each bit of the digit word group. For example, the mode condition can be one of the two possible mode conditions for each bit in the bit block. The mode status is a rule, such as the rule expressed in the following equation.

(1)

(2)

The mode status can be based on the bit position in the digit word group. For example, LSB (i=0) may have the first mode status, the next higher significant bit (i.e., i=1) may have the second mode status, and the next higher significant bit (i.e., i= 2) It can have the first mode status, and so on until the MSB. Therefore, as the bits are sequentially timed into the DAC, the mode condition may change (for example, alternate) between the first mode condition (ie, mode-condition_1) and the second mode condition (ie, mode_condition_2) .

FIG. 3 is a table of possible mode conditions and modes for each possible bit combination of a 5-bit binary block (ie, a digital block) according to an example implementation of the present disclosure. Each possible digit word group has a unique pattern combination based on (i) the mode status of each bit position and (ii) the bit value of each bit position. For the digit word group 00000, the bit positions are alternated due to the mode status, but the bit values of the bit positions are not alternated, which is used to alternate the mode of each bit from LSB to MSB. Similarly, for the digit word group 11111, the bit positions of the bit positions are alternated due to the mode status, but the bit values of the bit positions are not alternated, which is used for the mode of the bit positions from LSB to MSB. The modes used for the digit groups 00000 and 11111 are complementary. For the digit word group 01010, because the mode status alternates with bit positions and bit values also alternate with bit positions, the mode used for each bit from LSB to MSB is the same (that is, Mode1). Similarly, for the digit block 10101, because the mode status alternates for each bit position and the bit value also alternates for each position, the mode used for each bit from LSB to MSB is the same (ie, Mode2). As long as the mode status alternates with the bit position (that is, in the horizontal direction of the table), the selection of which mode status is used for the LSB of the 00000 word group can be one of the first mode status or the second mode status.

2C-DAC includes bits that are configured to sequentially feed digital blocks (for example, feed bits according to the clock) into 2C-DAC, based on the validity of the bits (that is, their Bit position) to select the mode status, and to select the mode (ie, Mode1, Mode2) based on the value of the bit applied to the selected mode status (not shown). For example, the 2C-DAC may include a logic circuit system that activates the first mode (Mode1) or the second mode (Mode2) based on the table shown in FIG. 3. Alternatively, when greater than or less than 5 bits in the digit block, the 2C-DAC may include logic to activate the first mode (Mode1) or the second mode (Mode2) based on a table similar to the table shown in FIG. 3 electrical system.

The mode status can be implemented using a bit selection signal (ie, Bit_Select). The bit selection signal can be alternated based on the validity of the bit. For example, the bit selection signal can be zero for the LSB bit (Data[0]), one for the next significant bit (Data[1]), and one for the next significant bit (Data[2]). Zero, and so on until the MSB. The mode can be selected by comparing the value of the bit (ie, Bit_Vale) with the bit selection signal. For example, when the bit selection signal is 0 and the value of the bit is 0, Mode 1 can be selected, and when the bit selection signal is 0 and the value of the bit is 1, Mode 2 can be selected. Similarly, when the bit selection signal is 1 and the value of the bit is 0, Mode 2 can be selected, and when the bit selection signal is 1 and the value of the bit is 1, Mode 1 can be selected.

FIG. 4 graphically illustrates the process of mode condition selection and mode determination based on the table of possible mode conditions shown in FIG. 3. The program is based on the example 5-bit number block, 01100. The program starts with the LSB of the 5-bit digit block, 01100. From the table shown in FIG. 3, the mode status for LSB (Data[0]) is the first mode status (Bit_Select = 0). Therefore, when the bit value of the LSB (b ₀ = 0) is applied to the mode condition, Mode1 is selected. In other words, the bit selection signal of the bit (that is, 0) matches the bit value (that is, 0), so Mode1 is selected. As a result, the 2C-DAC shown in Figure 2 can use the switch assigned to Mode1 to continue through the input, average, and output stages.

The program continues with the next significant bit of the 5-bit digit block, 01100. From the table shown in FIG. 3, the mode status for the next valid bit (Data[1]) is the second mode status (Bit_Select = 1). Therefore, when the bit value (b ₁ = 0) of the next valid bit is applied to the mode condition, Mode2 is selected. In other words, the bit selection signal of the bit (that is, 1) does not match the bit value (that is, 0), so Mode2 is selected. As a result, the 2C-DAC shown in Figure 2 can continue through the input, averaging, and output stages using the switch assigned to Mode2.

The program continues with the next significant bit of the 5-bit digit block, 01100. From the table shown in FIG. 3, the mode status for the next valid bit (Data[2]) is the first mode status (Bit_Select = 0)). Therefore, when the bit value (b ₂ = 1) of the next significant bit is applied to the mode condition, Mode2 is selected. In other words, the bit selection signal (that is, 0) does not match the bit value (that is, 1), so Mode2 is selected. As a result, the 2C-DAC shown in Figure 2 can continue through the input, averaging, and output stages using the switch assigned to Mode2.

The program continues with the next significant bit of the 5-bit digit block, 01100. From the table shown in FIG. 3, the mode status for the next valid bit (Data[3]) is the second mode status (Bit_Select = 1). Therefore, when the bit value of the next significant bit (b ₃ = 1) is applied to the mode condition, Mode1 is selected. In other words, the bit selection signal (ie, 1) matches the bit value (ie, 1), so Mode1 is selected. As a result, the 2C-DAC shown in Figure 2 can use the switch assigned to Mode1 to continue through the input, average, and output stages.

The program ends with the MSB of the 5-bit digit block, 01100. From the table shown in FIG. 3, the mode status for the next valid bit (Data[4]) is the first mode status (Bit_Select = 0). Therefore, when the bit value of the MSB (b ₄ = 0) is applied to the mode condition, Mode1 is selected. In other words, the bit selection signal (ie, 0) matches the bit value (ie, 0), so Mode 1 is selected. As a result, the 2C-DAC shown in Figure 2 can use the switch assigned to Mode1 to continue through the input, average, and output stages.

As can be observed, the program changes mode when the sequential bit value does not change. This prevents repeated charging of the same capacitor in the sequence or repeated discharge of the same capacitor in the sequence. Preventing repeated charging/discharging of the same capacitor in the bit sequence can prevent repeated use of the same switch, which can prevent charging/discharging errors caused by the capacitance of the switch. On the other hand, at least due to the use of different switches to charge and discharge the capacitor, when the sequential bit value changes, the program does not change the mode. By preventing repeated charging/discharging of the same capacitor (that is, repeated use of the same switch), the efficiency of DAC conversion (for example, accuracy, linearity) can be increased.

At the end of the procedure, the output voltage (V _O ) at the output of the buffer shown in FIG. 2 can be at a voltage corresponding to the number of digits 01100 (ie, 12). For a 2C-DAC output voltage range of 0 V to 1 V. _{The output voltage (V O} ) at the end of the described procedure can be 12/31 V. The program shown in Figure 4 operates on binary blocks and can be repeated for additional binary blocks. For example, binary blocks can be sequentially input to the 2C-DAC to generate a time-varying output voltage. The rate at which the output voltage can change may depend on the speed at which the program (such as shown in Figure 4) can be executed. Therefore, a higher resolution (ie, a longer digit block) may result in a slower conversion than a lower resolution (ie, a shorter digit block).

FIG. 5 is a schematic diagram of a two-capacitor DAC (ie, 2C-DAC) circuit including a reset and output circuit system according to a possible implementation of the present disclosure. The 2C-DAC circuit 500 is similar to the embodiment of FIG. 2, in which a sample and hold circuit 510 is added at the output of the operational amplifier 210. The sample and hold circuit 510 includes a sample and hold capacitor (C _{SH ) coupled to the output switch (S OUT} ). When the output switch is turned on, the sample and hold capacitor (C _SH ) is configured to charge to the output voltage (V _O ) of the operational amplifier 210. The sample and hold capacitor (C _SH ) is coupled to the output of the DAC (ie, OUT _DAC ), so that even when the output switch (S _OUT ) is turned off, the sample and hold capacitor (C _SH ) can be used to maintain the DAC The output voltage at the output (that is, OUT _{DAC ).}

The 2C-DAC circuit 500 further includes a reset switch coupled to each capacitor of the circuit. The first reset switch (S _{RES_C1} ) is coupled in parallel between the positive terminal of the first capacitor (C ₁ ) and the ground. The first reset switch is configurable in the on-state to discharge the _{first capacitor (C 1 ).} The second reset switch (S _{RES_C2} ) is coupled in parallel between the positive terminal of the second capacitor (C ₂ ) and the ground. The second reset switch is configurable in the on-state to discharge the _{second capacitor (C 2 ).} The sample and hold reset switch (S _{RES_CSH} ) is coupled in parallel between the positive terminal of the sample and hold capacitor (C _{SH) and ground.} The sample and hold reset switch (S _{RES_CSH} ) is configurable in the on-state to discharge the sample and hold capacitor (C _SH ). The reset switches can be controlled together or independently. For example, the reset switch can be turned on at the end of the digit block, so no residual charge will change the calculation of the next digit block.

_{The operational amplifier 210 of the 2C-DAC circuit 500 may have an input capacitance (C IN} ) that can affect (for example, reduce) the accuracy of the digital-to-analog conversion. For example, the input stage of an operational amplifier may include a differential pair of transistors. One or more transistors in the differential pair may have a capacitance associated with the control terminal (eg, gate terminal). In this example, the input capacitance (C _IN ) of the operational amplifier may be the capacitance associated with the gate terminal (ie, C _GS ). If the input capacitance of the operational amplifier is charged using a portion of the charge _{coupled from the capacitors (C 1} , C _{2 ), V O} may have an error associated with this portion of the charge used to charge the input capacitance of the operational amplifier. Because the input capacitance may change, calibration of this part may be difficult or impossible.

Figure 6 is a graph of the input capacitance of an operational amplifier configured as a buffer amplifier. The diagram includes an illustration 610 showing a buffer amplifier including an operational amplifier 210 having an input capacitance C _IN. As shown in the chart, the input capacitance can change the average input voltage (V _AVG ) in complex ways (for example, non-linear, non-monotonic, etc.). As mentioned earlier, during the conversion, the average voltage can change (see Figure 1B, for example). Therefore, the conversion error caused by the input capacitance can be changed for each possible bit combination. This can lead to conversion of binary blocks with unpredictable errors. The disclosed double-capacitor DAC utilization method and circuit system reduce the effect of buffer amplifier input capacitance and its variation to improve performance (for example, linearity, single scheduling, accuracy).

FIG. 7 is a schematic diagram of a double-capacitor DAC (ie, 2C-DAC) circuit including a capacitance compensation circuit according to a possible implementation of the present disclosure. The 2C-DAC circuit 700 is similar to the 2C-DAC implementation of FIG. 5, in which a capacitance compensation circuit 710 is added. The capacitance compensation circuit 710 includes a _{duplicate input capacitor (C IN_REP} ) (ie, duplicate input capacitance) having a capacitance (for example, equivalent capacitance) similar to _{the input capacitor (C IN) of the operational amplifier 720.} For example, the input capacitor (C _IN ) and the duplicate input capacitor (C _{IN_REP} ) may have the same variation as the average voltage (for example, see Figure 6).

The capacitance compensation circuit 710 may further include a pair of compensation input switches (S ₁ , S ₀ ). The compensation input switch can be configured to operate according to the data for controlling the first group of input switches (S _{1_C1} , S _{0_C1} ) or the second group of input switches (S _{1_C2} , S _{0_C2} ). For example, when one of S _{1_C1} or S _{1_C2} is turned on, the first compensation input switch (S _{1_CINREP} ) can be turned on, and when one of S _{0_C1} or S _{0_C2} is turned on, the second compensation input switch ( S _{0_CINREP} ) is turned on. When the first compensation input switch (S _{1_CINREP} ) is turned on, the second compensation input switch (S _{0_CINREP} ) can be turned off, and vice versa. In other words, in the input phase of either Mode1 or Mode2, when the bit value is 1, the first compensation input switch (S _{1_CINREP} ) is turned on, or when the bit value is zero, the second compensation input switch is turned on (S _{2_CINREP} ) is turned on. In this way, the duplicate input capacitor (C _{IN_REP} ) can be charged or discharged during the input phase.

The capacitance compensation circuit 710 may further include a first compensation switch (S _{COMP_C1} ) and a second compensation switch (S _{COMP_C2} ) configured to operate during the averaging phase and according to the mode. Therefore, while the average switch (S _AVG ) and S _{C_C1} or S _{C_C2 are} turned on, one of S _{COMP_1} or S _{COMP_2} can be turned on. For example, in the averaging phase of the conversion process in Mode1, the first compensation switch (S _{COMP_1} ) can be turned on to couple _{the charge stored in C IN_REP to NODE1} of the 2C-DAC circuit 700. In the average phase of the conversion procedure in Mode2, the second compensation switch (S _{COMP_2} ) can be turned on to couple _{the charge stored in C IN_REP} to NODE2 of the 2C-DAC circuit 700. The average phase of the conversion process therefore has two aspects. The first aspect (ie, conversion average) includes _{redistribution of charges between C 1} and C ₂ , and the second aspect (ie, replication average) includes redistribution of charges between _{C IN_REP} and C _IN.

In the averaging phase of the conversion process (ie, copy averaging), the charge on _{C IN_REP can be redistributed to C 1} (C ₂ ) and C ₂ (C ₁ ) in the same way as the input capacitance C _IN Redistribution. Therefore, a part of the charge is added to compensate for the charge consumed by the input capacitor. The duplicate input capacitor (C _{IN_REP} ) and the input capacitor (C _IN ) have the same average voltage and the same average capacitance. In one possible implementation, the copy input capacitor is a copy of a part of the operational amplifier 720 (not shown). For example, the capacitance compensation circuit 710 may include a transistor configured to substantially match the transistor of the operational amplifier 720 coupled to the output of the 2C-DAC. Table 4 illustrates an example switch state of the average phase according to a possible implementation of the present disclosure. Other switches not mentioned in Table 4 can be turned off during the average phase.

surface 4 : Instance switch state of the average phase To MODE 1 MODE2 S _AVG Conduction Conduction S _{C_C1} Conduction Conduction S _{C_C2} Conduction Conduction S _{COMP_1} Conduction Turn off S _{COMP_2} Turn off Conduction

FIG. 8 is a flowchart of a method for digital to analog conversion according to a possible implementation of the present disclosure. The method 800 includes receiving 810 a binary word group (B) (that is, a digit word group) including binary bits (ie, digit bit, bit). For example, receiving a binary word group may include sequentially receiving bits from the least significant bit (LSB) to the most significant bit (MSB). Therefore, the method includes setting 820 the LSB to the action bit in the binary block. The method further includes selecting 830 mode status based on the action bit in the binary word group (for example, 0=Mode1, 1=Mode2). The method then includes determining the 835 mode based on the value of the action bit (eg, 0, 1) and the selected mode status. The method then enters the input phase of the conversion program.

The converter may include stage and mode controllers to load data into the converter, determine the mode for each bit, and output switching signals to switches in the 2C-DAC circuit. For example, the stage and mode controller may include a shift register to sequentially feed bits into the 2C-DAC circuit. The stage and mode controller may further include logic configured to determine the status of the mode and the mode of each bit. The logic can be further configured to output a switching signal based on the mode status and the mode of each bit.

In the input phase of the conversion procedure, the method includes controlling a set of input switches to charge or discharge the capacitor. In Mode1, the method includes controlling 841 the first set of input switches (S _{0_C1} , S _{1_C1} ) to charge/discharge the first capacitor (C ₁ ) (and turn on S _{C_C2} ). In Mode2, the method includes controlling 842 the second set of input switches (S _{0_C2} , S _{1_C2} ) to charge/discharge the second capacitor (C ₂ ) (and turn on S _{C_C1} ). Furthermore, in the input phase, the method includes controlling 840 a set of compensation input switches (S _{1_CINREP} , S _{0_CINREP} ) to charge/discharge the copy input capacitor (C _{IN_REP ).} The control of the compensation input switch can be independent of this mode. For example, when bi=1, S _{1_CINREP} can be turned on to _{charge C IN_REP} , and when bi=0, S _{0_CINREP} can be turned on to _{discharge C IN_REP} , regardless of the determined mode. After the input phase, the method enters the averaging phase of the conversion process.

In the averaging phase of the conversion procedure, the method includes controlling the 850 averaging switch (S _AVG ) to couple C ₁ to C ₂ to redistribute (ie, average) the charge between the capacitors (and turn on _{SC_C1} and _{SC_C2} ) . The method further includes controlling the switch to _{redistribute charge between the replicated input capacitance (C IN_REP} ) and the input capacitance of the buffer amplifier (C _IN ) to generate an adjusted average voltage. In Mode1, the method includes controlling 851 coupling switch ( _{SC_C1} ), coupling switch ( _{SC_C2} ) and compensation switch (S _{COMP_1} ) to couple C _{IN_REP} to C _IN . In Mode2, the method includes controlling 852 the coupling switch (S _{C_C1} ), the coupling switch (S _{C_C2} ), and the compensation switch (S _{COMP_2} ) to couple C _{IN_REP} to C _IN .

After the average phase, the method can repeat the input phase and the average phase, or enter the output phase based on the bit position of the action bit. Therefore, the method includes checking whether the 860 action bit is the final bit of the coefficient bit block (eg, MSB). If the action bit is not the last bit of the digital word group, the next most significant bit is set to 870 as the action bit, and the program conversion process is repeated for the new action bit. If the last bit of the bit-coefficient bit group is actuated, the method enters the output stage.

In the output stage of the conversion procedure, the method includes controlling the 880 output switch (S _OUT ) to couple the output of the buffer amplifier to the output of the DAC (ie, OUT _DAC ). The output voltage (V _O ) of the buffer amplifier is a buffered version _{of the average voltage (V AVG) at the input of the buffer amplifier.} After the output of the digit word group is generated, the first capacitor, the second capacitor, and the duplicate input capacitor can be discharged, and a new digit word group can be received. After receiving the new digit word group, the above procedure can be repeated to obtain the output voltage of the new digit word group.

FIG. 9 is a block diagram of a system for digital-to-analog conversion according to an embodiment of the present disclosure. The system includes a 2C-DAC 910 that can be configured with a mode1 or mode2 version of an input phase, an averaging phase, and an output phase through the phase and mode controller 901. For example, the stage and mode controller 901 may include a digital bit shift register to read (ie, clock input) the bit value of the digital block from the least significant bit to the most significant bit. The stage and mode controller 901 may further include logic configured to determine mode conditions and modes (ie, mode1, mode2) based on the position of the bit and the value of the bit (see, for example, FIG. 3). The stage and mode controller 901 can output the switching signal coupled to the switch in the 2C-DAC. The switch can be configured according to the mode (ie, mode1, mode2) and the stage of conversion (ie, input, average, output).

The 2C-DAC may also include an averaging circuit 940. The averaging circuit 940 may include a first capacitor (C ₁ ) and a second capacitor (C ₂ ). The averaging circuit 940 can be configured by switching signals to charge or discharge the first capacitor or the second capacitor during the input phase. The averaging circuit 940 may be further configured by switching signals to couple the first capacitor and the second capacitor together during the averaging phase to average (ie, redistribute) the added or remaining charge during the averaging phase. The averaging circuit 940 may be further configured to couple one of the first capacitor (C ₁ ) (for example, for mode 2) or the second capacitor (C ₂ ) (for example, for mode 1) to Output circuit 950.

The 2C-DAC further includes an output circuit 950 coupled to the output of the 2C-DAC 910 during the output phase. The output circuit 950 may include a buffer amplifier to buffer the average voltage received from the averaging circuit 940 to generate the output voltage (V _O ) of the 2C-DAC. _{The output circuit may have an input capacitance (C IN} ) that prevents a portion of the charge (ie, voltage) from reaching the output, where this portion is based on the average voltage at the input.

To compensate _{for the effect of C IN} on the output voltage (V _O ), the 2C-DAC 910 includes a capacitance compensation circuit 930. The capacitance compensation circuit includes a duplicate input capacitance (C _{IN_REP} ). The duplicate input capacitance may be a duplicate (ie, a copy) _{of the input capacitance (C IN} ) of the buffer amplifier with the same variation as the input voltage. The capacitance compensation circuit 930 can be configured by switching signals to charge or discharge the duplicate input capacitance during the input phase. The capacitance compensation circuit can be further configured to couple the replicated input capacitor to the input capacitor during the averaging phase to average the added or remaining charge during the averaging phase, so that the effect of the input capacitor on the output voltage (V _O ) is obtained compensate.

The disclosed 2C-DAC circuit can provide advantages over digital-to-analog conversion circuits. For example, because it only needs two capacitors for the conversion process, it can be low power. At least because it compensates for switching capacitance, capacitor mismatch, and input capacitance that would otherwise affect the accuracy of the conversion process, it can be highly precise. It can occupy a small area in a silicon integrated circuit. For example, a 2C-DAC circuit using 4 picofarad (pF) or 8 pF capacitors and switches may require an area of 50 microns (µm) by 70 µm. Since the required customized layout is only for the two capacitors, switch, buffer amplifier, and output capacitor, it is expected to minimize the design time. The rest of the design is in the digital domain. Although the conversion process has a delay associated with serially processing each bit, this delay may be suitable for applications that do not require speed and may require high-precision rail-to-rail conversion. For example, biomedical applications may have slowly changing conditions, which can be handled by the disclosed 2C-DAC.

In the description and/or the drawings, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term "and/or" includes any or all combinations of one or more of the associated listed items. The drawings are schematic representations and are therefore not necessarily drawn to scale. Unless otherwise stated, specific terms have been used in a general and descriptive sense, rather than for the purpose of limitation.

Unless otherwise defined, all technical and scientific terms used in this article have the same meanings commonly understood by those with ordinary knowledge in the technical field. Methods and materials similar or equivalent to those described herein can be used in the implementation or testing of the present disclosure. As in this specification and in the scope of the appended application, unless the content clearly indicates otherwise, the singular form "一 (a/an)" and "the (the)" include plural referents. The term "comprising" and its variants used herein are used synonymously with the term "including" and its variants, and are non-limiting open terms. As used herein, the term "optional" or "optionally" means that the feature, situation, or situation described later may or may not occur, and that the description includes the occurrence and non-occurrence of the Cases of characteristics, circumstances, or circumstances. Ranges can be expressed herein as from "about" one specific value and/or to "about" another specific value. When expressing this range, one aspect includes from the one specific value and/or to the other specific value. Similarly, when the aforementioned "about" is used to express a value as an approximation, it should be understood that the specific value will form another aspect. It should be further understood that the endpoint of each of these ranges is significantly relative to the other endpoint, and is significantly independent of the other endpoint.

Some implementations can be implemented using various semiconductor processing and/or packaging techniques. Some embodiments can be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC) , Silicon on Insulator (SOI), Completely Depleted SOI (FDSOI), and/or etc.

Although certain features of the described embodiments have been illustrated as described herein, those with ordinary knowledge in the art will now think of many modifications, substitutions, changes, and equivalents. Therefore, it should be understood that the scope of the attached patent application is intended to cover all such modifications and changes that fall within the scope of the embodiments. It should be understood that these are presented by way of example (non-limiting) only, and various forms and details can be changed. Any part of the devices and/or methods described herein can be combined in any combination, except for mutually exclusive combinations. The implementations described herein may include various combinations and/or sub-combinations of the functions, components, and/or features of the different implementations described.

It should be understood that in the foregoing description, when an element is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, it It may be directly on, connected or coupled to another element, or one or more intervening elements may be present. Conversely, when an element is referred to as being directly on another element, directly connected to another element, or directly coupled to another element, no intervening elements exist. Although the term directly on (directly on), directly connected to (directly connected to), or directly coupled to (directly coupled to) may not be used throughout the embodiment, it can be called directly on, directly Components connected to or directly coupled to. The scope of patent application (if any) of this application can be modified to describe the illustrative relationships described in this specification or shown in the drawings.

When used in this specification, the singular form may include the plural form, unless a specific situation is clearly indicated in the context. In addition to the orientation depicted in the schema, relative terms of space (for example, over, above, upper, under, below, below, below, etc.) lower) etc.) are intended to cover the different orientations of the device in use or operation. In some embodiments, the relative terms above and below include vertically above and vertically below, respectively. In some embodiments, the term adjacent may include laterally adjacent or horizontally adjacent.

110: Buffer amplifier 200: 2C-DAC circuit 210: Buffer amplifier/operational amplifier 500: 2C-DAC circuit 510: Sample and hold circuit 610: Illustration 700: 2C-DAC circuit 710: Capacitance compensation circuit 720: Operational amplifier 800: Method 810: Receive 820: Setting 830: Selection 835: Judgment 840: Control 841: Control 842: Control 850: Control 851: Control 852: Control 860: Check 870: Setting 880: Control 901: Phase and Mode Controller 910: 2C- DAC 930: Capacitance compensation circuit 940: Averaging circuit 950: Output circuit B: Digit block b ₀ : LSB b ₁ : Second effective bit b ₂ : Most significant bit b _i : Bit C ₁ : Capacitor/first Capacitor C ₂ : Capacitor/Second Capacitor C _IN : Input Capacitance C _{IN_REP} : Copy Input Capacitor C _SH : Sample and Hold Capacitor Mode1: First Mode Mode2: Second Mode OUT _DAC : Output S ₀ : Zero Switching/Compensation Input Switch S _{0_C1} : input switch S _{0_C2} : input switch S _{0_CINREP} : second compensation input switch S ₁ : one switch/compensation input switch S _{1_C1} : input switch S _{1_C2} : input switch S _{1_CINREP} : first compensation input switch S _AVG : average switch S _{C_C1} : first capacitor coupling switch/coupling switch S _{C_C2} : second capacitor coupling switch/coupling switch S _{COMP_1} : first compensation switch S _{COMP_C1} : first compensation switch S _{COMP_2} : second compensation switch S _{COMP_C2} : Second compensation switch S _OUT : output switch S _{RES_C1} : first reset switch S _{RES_C2} : second reset switch S _{RES_CSH} : sample and hold reset switch V _AVG : average voltage V _O : output voltage V _REF : reference voltage

[Fig. 1A] is a schematic diagram of an example double-capacitor DAC according to a possible implementation of the present disclosure. [Figure 1B] is a graph of the output voltage of the double-capacitor DAC in Figure 1A for possible digital blocks. [Fig. 2] is a schematic diagram of a double-capacitor DAC (ie, 2C-DAC) according to a first possible implementation of the present disclosure. [FIG. 3] is a table of possible mode conditions for each possible bit combination of a 5-bit binary block (ie, a digit block) according to an example implementation of the present disclosure. [Fig. 4] Graphically shows the procedure of mode condition selection and mode determination based on the table of possible mode conditions shown in Fig. 3. [FIG. 5] is a schematic diagram of a double-capacitor DAC (ie, 2C-DAC) including a reset and output circuit system according to a possible implementation of the present disclosure. [Figure 6] is a graph of the input capacitance versus average voltage of the buffer amplifier according to a possible implementation of the present disclosure. [FIG. 7] is a schematic diagram of a two-capacitor DAC (ie, 2C-DAC) including input capacitance compensation according to a possible implementation of the present disclosure. [Figure 8] is a flow chart of a method for digital to analog conversion according to a possible implementation of the present disclosure. [Figure 9] is a block diagram of a system for digital to analog conversion according to an embodiment of the present disclosure.

The components in the drawing are not necessarily drawn to scale relative to each other. Similar component symbols indicate corresponding parts in several views.

700: 2C-DAC circuit

710: Capacitance compensation circuit

720: Operational amplifier

C ₁ : capacitor / first capacitor

C ₂ : Capacitor/Second capacitor

C _IN : Input capacitance

C _{IN_REP} : Copy input capacitor

C _SH : Sample and hold capacitor

OUT _DAC : output

S _{0_C1} : Input switch

S _{0_C2} : Input switch

S _{0_CINREP} : The second compensation input switch

S _{1_C1} : Input switch

S _{1_C2} : Input switch

S _{1_CINREP} : The first compensation input switch

S _AVG : Average switch

S _{C_C1} : first capacitor coupling switch/coupling switch

S _{C_C2} : second capacitor coupling switch/coupling switch

S _{COMP_1} : The first compensation switch

S _{COMP_2} : The second compensation switch

S _OUT : output switch

S _{RES_C1} : The first reset switch

S _{RES_C2} : The second reset switch

S _{RES_CSH} : Sample and hold reset switch

V _REF : Reference voltage

Claims (13)

A double-capacitor digital-to-analog converter circuit, which includes: A stage and mode controller, which is configured to set an action bit in a digital word group, select a mode condition of the action bit, and a value based on the action bit and the selected mode condition according to A first mode or a second mode of the conversion program to configure the switch; A redistribution switch configured to couple a first capacitor and a second capacitor together during a redistribution phase of the conversion process to generate a redistribution voltage; A buffer amplifier configured to generate an output voltage based on the redistributed voltage, the buffer amplifier having an input capacitance at an input; and A capacitance compensation circuit, which includes a duplicate input capacitance, and the capacitance compensation circuit is configured to: During an input phase of the conversion process, a reference voltage or a ground is coupled to the copy input capacitor based on the value of the action bit, and During the redistribution phase of the conversion procedure, the duplicate input capacitor is coupled to the input capacitor to adjust the redistribution voltage. For example, the dual-capacitor digital-to-analog converter circuit of claim 1, which further includes: A first set of input switches configured to couple a first capacitor to a reference voltage or a ground based on the value of the action bit during an input stage of the conversion procedure in the first mode ;and A second set of input switches configured to couple a second capacitor to the reference voltage or the ground based on the value of the action bit during the input phase of the conversion procedure in the second mode . For example, the dual-capacitor digital-to-analog converter circuit of claim 1, which further includes: An output switch configured to couple the output voltage to an output of the double-capacitor digital-to-analog converter circuit during an output stage of the conversion process. For example, the two-capacitor digital-to-analog converter circuit of claim 1, wherein the duplicate input capacitor is coupled to the input capacitor to adjust the redistribution voltage, so as to reduce an influence of the input capacitor on the output voltage. For example, the dual-capacitor digital-to-analog converter circuit of claim 1, wherein the capacitance compensation circuit includes: A first compensation input switch, which is configured to couple the duplicate input capacitance during the input phase of the conversion procedure in the first mode or the second mode when the value of the action bit is one Connect to a reference voltage; A second compensation input switch configured to copy the input capacitance when the value of the action bit is zero during the input phase of the conversion procedure in the first mode or the second mode Coupled to a ground; A first compensation switch configured to couple the duplicate input capacitance to a positive terminal of the first capacitor during the redistribution phase of the conversion procedure in the first mode; A second compensation switch configured to couple the duplicate input capacitance to a positive terminal of the second capacitor during the redistribution phase of the conversion procedure in the second mode; A first capacitor coupled switch configured to couple the positive terminal of the first capacitor to the input of the buffer amplifier during the input phase of the conversion procedure in the second mode The input capacitance; and A second capacitor coupled switch is configured to couple the positive terminal of the second capacitor to the input of the buffer amplifier during the input phase of the conversion procedure in the first mode The input capacitance. For example, the dual-capacitor digital-to-analog converter circuit of claim 1, where: The buffer amplifier is an operational amplifier, the operational amplifier is configured for single gain and rail-to-rail operation, the input capacitance is at an input of the operational amplifier, and The capacitance compensation circuit includes a transistor configured to replicate the input capacitance of the operational amplifier. For example, the dual-capacitor digital-to-analog converter circuit of claim 1, which further includes: A sample and hold capacitor coupled to an output of the buffer amplifier; and A first reset switch configured to discharge the first capacitor after the conversion process, a second reset switch configured to discharge the second capacitor after the conversion process, and a A sample and hold reset switch, which is configured to discharge the sample and hold capacitor after the conversion procedure. A method for digital to analog conversion, the method includes: Select a mode status of an action bit of a digital word group; Determine a first mode or a second mode for the action bit based on a value of the action bit and the selected mode status; Perform an input phase, which includes: In a first mode, according to the value of the action bit, a first capacitor and a copy input capacitor are charged or discharged, and In a second mode, charge or discharge a second capacitor and the copy input capacitor according to the value of the action bit; and Perform an averaging phase, which includes: Coupling the first capacitor and the second capacitor together to generate an average voltage of the action bit, Coupling the average voltage to a buffer amplifier with an input capacitance, and The duplicate input capacitor and the input capacitor are coupled together to generate an adjusted average voltage of the action bit at an input of the buffer amplifier. For example, the method for digital-to-analog conversion in claim 8, which further includes: Repeat the selection, the determination, the execution of the input phase, and the execution of the average phase to obtain an adjusted average voltage of each bit of the digit word group in a sequence; Outputting the adjusted average voltage of a final bit of the digital word group in the sequence from the buffer amplifier as an output voltage, the output voltage corresponding to an analog conversion of the digital word group; Discharging the first capacitor, the second capacitor, and the duplicate input capacitor; Receive a new group of digits; Repeat the selection, the determination, the execution of the input phase, and the execution of the average phase to obtain an adjusted average voltage of each element of the new digit word group in a sequence; and The adjusted average voltage of the final bit of the digit word group in the sequence is output as the output voltage, and the output voltage corresponds to an analog conversion of the new digit word group. For example, the method for digital-to-analog conversion in claim 8, wherein a mode condition for selecting the action bit includes: Determine the bit position of the action bit, the bit position is in a range from a least significant bit (LSB) to a most significant bit (MSB); and A first mode condition or a second mode condition is selected based on the bit position. The first mode condition and the second mode condition alternate from the LSB to the MSB for each bit position in sequence, wherein the first mode condition includes When the bit value of the action bit is zero, a first mode is determined, and when the bit value of the action bit is one, a second mode is determined; and the second mode status includes when the action When the bit value of the bit is zero, a second mode is determined, and when the bit value of the action bit is one, a first mode is determined. For example, the method for digital-to-analog conversion of claim 8, wherein in the averaging phase, the coupling of the average voltage to a buffer amplifier having an input capacitance includes: In the first mode, coupling a positive terminal of the first capacitor and coupling a positive terminal of the second capacitor to the input of the buffer amplifier; and In the second mode, a positive terminal of the first capacitor and a positive terminal of the second capacitor are coupled to the input of the buffer amplifier. A system for digital-to-analog conversion. The system includes: A stage and mode controller, which is configured to receive a bit of a digital word and according to an input stage, an averaging stage, or an output stage of a conversion process and according to an input to the system A first mode or a second mode determined by each bit in the received digital word group to output a switching signal; An averaging circuit including a first capacitor and a second capacitor, the averaging circuit is configured to charge or discharge the first capacitor or the second capacitor during an input phase, and is configured to an average During the phase, the first capacitor and the second capacitor are coupled together to generate an average voltage; An output circuit including an input capacitor configured to generate an output voltage based on the average voltage received from the averaging circuit, and configured to couple the output voltage to the output voltage during the output phase An output of the system; and A capacitance compensation circuit including a duplicate input capacitance substantially equal to the input capacitance, and the capacitance compensation circuit is configured to couple the duplicate input capacitance and the input capacitance together during an averaging phase to adjust the average voltage To compensate the input capacitance. For example, the system used for digital to analog conversion in claim 12, where: The stage and the mode controller are configured to sequentially receive the bits of the digital word group, and generate a switching signal according to a first mode condition or a second mode condition. The first mode condition and the second mode condition follow The bits in the sequence alternate; The output circuit includes an operational amplifier configured for a single gain, the operational amplifier has the input capacitance at an input to the operational amplifier, and The capacitance compensation circuit includes a transistor configured to replicate the input capacitance of the operational amplifier.

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