TW202105342A - Driving method, shift register, and display device using the same - Google Patents

Abstract

A driving method, applicable to a display device including a shift register and a control circuit, and the control circuit is configured to provide a triggering signal, a first voltage, a second voltage, a third voltage, m high-frequency clock signals, and a low-frequency clock signal to the shift register, includes the following operations: when the control circuit determines a power input is higher than a first predetermined voltage, maintaining the first voltage, the second voltage, the third voltage, the m high-frequency clock signals, and the low-frequency clock signal at a logic low level until the triggering signal being switched from the logic high level to the logic low level, so as to reset voltages of multiple internal nodes of the shift register; utilizing the control signal to periodically switch the triggering signal, the first voltage, the m high-frequency clock signals, and the low-frequency clock between the logic high level and the logic low level, so as to update a display picture of the display device.

Description

Drive method, shift register, and related display Display device

The present disclosure relates to a driving method of a display device, a related display device and a shift register, and in particular to a driving method for removing residual charges inside the display device.

In order to meet the needs of the consumer market for narrow-frame displays, the industry has replaced traditional driver ICs with gate drivers fabricated on glass substrates. When the gate driver completes a frame (fame) screen update, the gate driver will temporarily stop the shift register operation. However, the traditional driving method does not clear the residual charge in the gate driver and gate line after the update of the display image of each frame, so that the internal components of the gate driver and the display may be affected by the bias voltage for a long time. Ageing.

The present disclosure provides a shift register, which includes n stages of shift register units, and n is a positive integer. Each of n-level shift register units Contains output circuit and voltage stabilization and reset circuit. The output circuit includes a first node, a first output terminal, and a second output terminal, for transmitting a first voltage to the first node, and for outputting m at the first output terminal and the second output terminal according to the voltage of the first node For the corresponding one of the two high-frequency clock signals, m is a positive integer. The voltage stabilization and reset circuit is used for transmitting the second voltage to the first node according to the low-frequency clock signal, and transmitting the second voltage and the third voltage to the first output terminal and the second output terminal respectively according to the trigger signal. The shift register is coupled to the control circuit. When the control circuit determines that the power input rises above the first preset voltage, the trigger signal is switched to the logic high level, and m high-frequency clock signals, low-frequency clock signals, first voltage, second voltage, and third The voltage is maintained at the logic low level until the trigger signal is switched from the logic high level to the logic low level to reset the voltage of the first node.

The present disclosure provides a driving method, which is suitable for a display device. The display device includes a shift register and a control circuit. The control circuit is used to provide a trigger signal, a first voltage, a second voltage, a third voltage, m high-frequency clock signals, and a low-frequency clock signal to the shift register. The aforementioned driving method includes the following process: when the control circuit determines that the power input is higher than the first preset voltage, the control circuit switches the trigger signal to a logic high level, and sets the first voltage, the second voltage, the third voltage, and m A high-frequency clock signal and a low-frequency clock signal are maintained at a low logic level until the trigger signal is switched from a high logic level to a low logic level to reset the voltages of multiple internal nodes of the shift register; The control circuit periodically switches the trigger signal, m high-frequency clock signals, low-frequency clock signals, and the first voltage between a logic high level and a logic low level to update the display screen of the display device.

The present disclosure provides a display device, which includes a control circuit and a shift register. The shift register is used to receive the trigger signal, the first voltage, the second voltage, the third voltage, m high-frequency clock signals, and the low-frequency clock signal from the control circuit, and includes n-stage shift register units, n Is a positive integer. Each of the n-stage shift register units includes an output circuit and a voltage stabilization and reset circuit. The output circuit includes a first node, a first output terminal, and a second output terminal, for transmitting a first voltage to the first node, and for outputting m at the first output terminal and the second output terminal according to the voltage of the first node For the corresponding one of the two high-frequency clock signals, m is a positive integer. The voltage stabilization and reset circuit is used for transmitting the second voltage to the first node according to the low-frequency clock signal, and transmitting the second voltage and the third voltage to the first output terminal and the second output terminal respectively according to the trigger signal. The shift register is coupled to the control circuit. When the control circuit determines that the power input rises above the first preset voltage, the trigger signal is switched to the logic high level, and m high-frequency clock signals, low-frequency clock signals, first voltage, second voltage, and third The voltage is maintained at the logic low level until the trigger signal is switched from the logic high level to the logic low level to reset the voltage of the first node.

The aforementioned shift register, driving method, and display device can prevent the shift register and the internal components of the display device from being biased for a long time and aging.

100‧‧‧Display device

110‧‧‧Control circuit

112‧‧‧Timing control circuit

114‧‧‧Level Shifter

116‧‧‧Power Unit

118‧‧‧Diode

120‧‧‧Source Driver

130‧‧‧Gate Driver

140‧‧‧Pixel

DL1~DLn‧‧‧Data line

GL1~GLn‧‧‧Multiple gate lines

200‧‧‧Shift register

210[1]~210[n], 300, 400‧‧‧shift temporary storage unit

VGH‧‧‧First voltage

VQ‧‧‧Second voltage

VG‧‧‧Third voltage

ST‧‧‧Trigger signal

HC1~HCm‧‧‧High frequency clock signal

LC1, LC2‧‧‧Low frequency clock signal

G[1]~G[n]‧‧‧Gate signal

S[1]~S[n]‧‧‧shift signal

310‧‧‧Output circuit

320‧‧‧Regulatory and reset circuit

322‧‧‧Reset Unit

324‧‧‧Pull-down unit

326a, 326b‧‧‧stabilizing unit

T1~T16‧‧‧Transistor

C1‧‧‧Capacitor

CS‧‧‧Capacitor

O1‧‧‧First output

O2‧‧‧Second output

N1, N1[m-2]‧‧‧First node

N2‧‧‧Second node

N3‧‧‧The third node

N4‧‧‧The fourth node

PW1, PW2‧‧‧Power input

DDS‧‧‧Data drive control signal

CIP‧‧‧Clock control signal

600、900‧‧‧Drive method

S602~S608, S910~S916‧‧‧Process

E1, E2‧‧‧ period

F1, F2, F3, F4‧‧‧period

FIG. 1 is a simplified functional block diagram of a display device according to an embodiment of the present disclosure.

FIG. 2 is a simplified functional block diagram of the shift register according to an embodiment of the present disclosure.

FIG. 3 is a functional block diagram of a shift register unit according to an embodiment of the present disclosure.

FIG. 4 is a functional block diagram of a shift register unit according to another embodiment of the present disclosure.

Figure 5 is a simplified functional block diagram of the control circuit of Figure 1.

FIG. 6 is a flowchart of a driving method according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of waveforms illustrating the display operation of the display device.

Fig. 8 is a schematic diagram of the waveform of part of the signal input to the shift register in a frame time.

FIG. 9 is a flowchart of a driving method according to another embodiment of the present disclosure.

Figures 10 and 11 are schematic diagrams of waveforms when the display device of Figure 1 faces different types of power-off events.

The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of the display device 100 according to an embodiment of the present disclosure. The display device 100 includes a control circuit 110, a source driver 120, a gate driver 130, and a plurality of data lines DL1~DLn, multiple gate lines GL1~GLn, and multiple pixels 140. The control circuit 110 is used to provide data driving control signals to the source driver 120 so that the source driver 120 generates a plurality of data signals. The control circuit 110 is also used to provide multiple clock signals and multiple reference voltages to the gate driver 130 so that the gate driver 130 generates multiple gate signals.

A plurality of pixels 140 are respectively disposed at a plurality of intersections of the data lines DL1 ˜DLn and the gate lines GL1 ˜GLn. Each pixel 140 receives a data signal and a gate signal through a corresponding one of the data lines DL1~DLn and a corresponding one of the gate lines GL1~GLn, respectively, for data writing, internal component characteristic compensation, and/ Or shine and so on.

In practice, the display device 100 may be a liquid crystal display, an Organic Light-Emitting Diode (OLED) display, or a Micro LED (Micro LED) display. In order to make the drawing concise and easy to explain, other elements and connection relationships in the display device 100 are not shown in the first figure.

FIG. 2 is a simplified functional block diagram of the shift register 200 according to an embodiment of the present disclosure. The shift register 200 can be set in the gate driver 130 of FIG. 1 to be used according to the high-frequency clock signals HC1~HCm, the low-frequency clock signals LC1 and LC2, the trigger signal ST, the first voltage VGH, the first The second voltage VQ and the third voltage VG sequentially output a plurality of gate signals G[1]~G[n] to the gate lines GL1~GLn, and are used to sequentially output a plurality of shift signals S[1]~ S[n] is used to trigger the shift register operation inside the shift register 200.

In this embodiment, the frequency of the high-frequency clock signal HC1~HCm The rates are the same but the phases are different from each other, and m and n are positive integers and m is less than n.

The shift register 200 includes n stages of shift register units 210[1]~210[n], each of the shift register units 210[1]~210[n] is used to output a gate signal G The corresponding one of [1]~G[n], and the corresponding one of the shift signals S[1]~S[n]. The shift register units 210[1] to 210[n] belong to m phases, and the shift register units in the same phase are coupled in series. Therefore, the gate signals G[1]~G[n] and the shift signals S[1]~S[n] also belong to m phases correspondingly. In addition, the pulses of the gate signals of the same phase do not overlap each other, but the pulses of the gate signals of different phases can overlap each other.

In this embodiment, the gate driving units of the same phase are coupled across m-level gate driving units, and the shift register operations of each other are triggered in sequence. For example, the first stage shift register unit 210[1] will output the shift signal S[1] to the shift register unit 210[m+1] to trigger the shift register unit 210[m+1] Perform shift temporary storage operation. For another example, the second stage shift register unit 210[2] outputs the shift signal S[2] to the shift register unit 210[m+2] to trigger the shift register unit 210[m+2] ]. By analogy, the m-th stage shift register unit 210[m] will output the shift signal S[m] to the shift register unit 210[m+m].

In addition, the shift register operation of the first-stage shift register unit (for example, the shift register units 210[1]~210[m]) of each phase is triggered by the trigger signal ST.

FIG. 3 is a simplified functional block diagram of the shift register unit 300 according to an embodiment of the present disclosure. The shift temporary storage unit 300 can be used for real The shift temporary storage units 210[1]~210[m] in Figure 2 are shown. For the convenience of description, Figure 3 shows the m-th stage shift temporary storage units (for example, the shift temporary storage unit 210[m ]). The shift register unit 300 includes an output circuit 310 and a voltage stabilization and reset circuit 320. The output circuit 310 includes a first node N1, a first output terminal O1, and a second output terminal O2 for transmitting the first voltage VGH to the first node N1 according to the trigger signal ST, and for transmitting the first voltage VGH to the first node N1 according to the voltage of the first node N1 The first output terminal O1 and the second output terminal O2 output a corresponding one of the high-frequency clock signals HC1 to HCm (for example, the high-frequency clock signal HCm).

The voltage of the first output terminal O1 and the second output terminal O2 will be used as the corresponding one of the shift signals S[1]~S[m] and the corresponding one of the gate signals G[1]~G[m]. By. For example, if the shift register unit 300 is the shift register unit 210[1], the shift register unit 300 will output the shift signal S[1] and the gate signal G[1]. For another example, if the shift register unit 300 is the shift register unit 210[2], the shift register unit 300 will output the shift signal S[2] and the gate signal G[2]. By analogy, if the shift register unit 300 is the shift register unit 210[m], the shift register unit 300 will output the shift signal S[m] and the gate signal G[m].

The output circuit 310 includes transistors T1 to T3 and a capacitor C1. The first terminal of the transistor T1 is used for receiving the first voltage VGH, the second terminal is coupled to the first node N1, and the control terminal is used for receiving the trigger signal ST. The capacitor C1 is coupled between the first node N1 and the second output terminal O2. The first end of the transistor T2 and the first end of the transistor T3 are used to receive a corresponding one of the high-frequency clock signals HC1 to HCm. For example, if the shift register unit 300 is the shift register unit 210[1], the first end of the transistor T2 and the first end of the transistor T3 are used for Receive high frequency clock signal HC1. For another example, if the shift register unit 300 is the shift register unit 210[2], the first end of the transistor T2 and the first end of the transistor T3 are used to receive the high-frequency clock signal HC2. By analogy, if the shift temporary storage unit 300 is the shift temporary storage unit 210 [m], the first end of the transistor T2 and the first end of the transistor T3 are used to receive the high-frequency clock signal HCm.

The second terminal of the transistor T2 is coupled to the first output terminal O1, and the control terminal is coupled to the first node N1. The second terminal of the transistor T3 is coupled to the second output terminal O2, and the control terminal is coupled to the first node N1.

The voltage stabilization and reset circuit 320 includes a reset unit 322, a pull-down unit 324, a voltage stabilization unit 326a, and a voltage stabilization unit 326b. The reset unit 322 includes transistors T4 to T5, and is used to reset the voltages of the first output terminal O1 and the second output terminal O2 according to the trigger signal ST, thereby resetting the voltage of the gate line coupled to the second output terminal O2 Voltage. The first terminal of the transistor T4 is coupled to the first output terminal O1, the second terminal is used for receiving the second voltage VQ, and the control terminal is used for receiving the trigger signal ST. The first terminal of the transistor T5 is coupled to the second output terminal O2, the second terminal is used for receiving the third voltage VG, and the control terminal is used for receiving the trigger signal ST.

In this embodiment, the first voltage VGH has a logic high level (Logic High Level), and the second voltage VQ and the third voltage VG have a logic low level (Logic Low Level).

In an embodiment, the second voltage VQ is higher than the third voltage VG. That is, the logic low level of the second voltage VQ is higher than the logic low level of the third voltage VG.

The pull-down unit 324 is used to transfer the second voltage VQ to the first node according to the shift signal of the next m stage (for example, the shift signal S[m+m]) N1, to turn off transistor T2 and transistor T3. The pull-down unit 324 includes a transistor T6, the first terminal of the transistor T6 is coupled to the first node N1, the second terminal of the transistor T6 is used to receive the second voltage VQ, and the control terminal of the transistor T6 is used to receive the aforementioned rear m Level shift signal. For example, if the shift register unit 300 is the shift register unit 210[1], the control terminal of the transistor T6 is used to receive the shift signal S[1+m]. For another example, if the shift register unit 300 is the shift register unit 210[2], the control terminal of the transistor T6 is used to receive the shift signal S[2+m]. By analogy, if the shift temporary storage unit 300 is the shift temporary storage unit 210[m], the control terminal of the transistor T6 is used to receive the shift signal S[m+m].

The voltage stabilizing unit 326a includes transistors T7 to T15 for periodically transmitting the second voltage VQ to the first output terminal O1 and the first node N1 according to the low-frequency clock signal LC1, and periodically transmitting the third voltage VG To the second output terminal O2. The first terminal of the transistor T7 is coupled to the first output terminal O1, and the second terminal is used to receive the second voltage VG. The first terminal of the transistor T8 is coupled to the second output terminal O2, and the second terminal is used to receive the third voltage VG. The first terminal of the transistor T9 is coupled to the first node N1, and the second terminal is used to receive the second voltage VQ. The control terminals of the transistors T7 to T9 are all coupled to the second node N2.

The first end of the transistor T10 is used for receiving the low-frequency clock signal LC1, the second end is coupled to the second node N2, and the control end is coupled to the third node N3. The first end of the transistor T11 is coupled to the second node N2, and the control end is coupled to the first node of the shift register unit of the first two stages (for example, the first node N1[m-2]). The first end of the transistor T12 is coupled to the third node N3, and the control end is coupled to the first node of the shift register unit of the first two stages. Transistor T13 The first end is coupled to the second node N2, and the control end is coupled to the first node N1. The first terminal of the transistor T14 is coupled to the third node N3, and the control terminal is coupled to the first node N1. The second ends of the transistors T11 to T14 are used to receive the second voltage VQ. The first terminal and the control terminal of the transistor T15 are used to receive the low-frequency clock signal LC1, and the second terminal is coupled to the third node N3. When the low-frequency clock signal LC1 has a logic high level, the transistors T7 to T10 and T15 will be turned on, thereby stabilizing the voltages of the first node N1, the first output terminal O1, and the second output terminal O2.

The voltage stabilizing unit 326b is similar to the voltage stabilizing unit 326a. The difference is that the first end of the transistor T10 and the first end and the control end of the transistor T15 of the voltage stabilizing unit 326b are used to receive the low-frequency clock signal LC2. The low-frequency clock signals LC1 and LC2 are mutually inverse signals. That is, when the low-frequency clock signal LC1 has a logic high level, the low-frequency clock signal LC2 has a logic low level, and when the low-frequency clock signal LC1 has a logic low level, the low-frequency clock signal LC2 has a logic high level Bit.

In this embodiment, the high-frequency clock signal HC1~HCm, the low-frequency clock signal LC1, the low-frequency clock signal LC2, the trigger signal ST, the first voltage VGH, the second voltage VQ, and the third voltage VG can be changed from the first The control circuit 110 of the figure is provided.

In an embodiment, one cycle of the low-frequency clock signals LC1 and LC2 includes tens to hundreds of frame times. Therefore, by alternately using two sets of voltage stabilizing units 326a and 326b, the aging of the components of the voltage stabilizing units 326a and 326b can be reduced.

FIG. 4 is a simplified functional block diagram of the shift register unit 400 according to an embodiment of the present disclosure. The shift temporary storage unit 400 can be used for real The shift register units 210[m+1]~210[n] in Fig. 2 are shown for convenience of description. Fig. 4 shows the shift register unit of the nth stage (for example, the shift register unit 210). [n]). The shift register unit 400 is similar to the shift register unit 300. The difference is that the reset unit 322 of the shift register unit 400 additionally includes a transistor T16, and the control terminal of the transistor T1 of the shift register unit 400 is It is used to receive the shift signal of the first m stages (for example, the shift signal [nm]). The first terminal of the transistor T16 is coupled to the first node N1, the second terminal is used to receive the second voltage VQ, and the control terminal is used to receive the trigger signal ST.

Fig. 5 is a simplified functional block diagram of the control circuit 110 of Fig. 1. The control circuit 110 includes a timing control circuit 112, a level shifter 114, a power unit 116, a diode 118, and a capacitor CS. The timing control circuit 112 is used to provide the data driving control signal DDS to the source driver 120 in FIG. 1. The timing control circuit 112 is also used to provide the power input PW1 and the clock control signal CIP to the level shifter 114.

The level shifter 114 generates the signals required for the operation of the shift register 200 in FIG. 2 according to the power input PW1 and the clock control signal CIP. For example, the level shifter 114 can shift the voltage of the power input PW1, and then output the first voltage VGH, the second voltage VQ, and the third voltage VG of different levels to the shift register 200. For another example, the level shifter 114 is also used to shift the voltage of one or more clock signals in the clock control signal CIP, and then output high-frequency clock signals HC1~HCm, low-frequency clock signals LC1 and LC2, and trigger The signal ST is sent to the shift register 200.

The power unit 116 is coupled to the level shifter 114 through the diode 118, and the capacitor CS is coupled between the level shifter 114 and the diode 118 The fourth node N4. The power unit 116 is used to provide the power input PW2 to the fourth node N4 through the diode 118. When the display device 100 faces a power-off event, the level shifter 114 will switch to use the voltage of the fourth node N4 to maintain at least a part of the output signal at the logic high level, and then the drain gate level lines GL1~GLn And the charge of the internal node of the shift register 200. In this way, the internal components of the display device 100 can be prevented from aging due to the long-term bias, and the display device 100 can be prevented from malfunctioning when it is restarted. The aforementioned power failure events include the user pressing the shutdown button, the user removing the power plug, and the power supply caused by component failure.

In practice, the level shifter 114 may include one or more amplifiers and one or more switch circuits to implement the aforementioned comparison and switching operations.

In one embodiment, the timing control circuit 112, the level shifter 114, the power unit 116, the diode 118, and the capacitor CS can be fabricated on the same glass substrate, and can be fabricated on the same chip or on different chips. in. In another embodiment, the power unit 116, the diode 118, and/or the capacitor CS are fabricated on an additional flexible printed circuit board, and the timing control circuit 112 and the level shifter 114 are fabricated on a glass substrate.

FIG. 6 is a flowchart of a driving method 600 according to an embodiment of the present disclosure. The driving method 600 is applicable to the display device 100 to realize the operation of the aforementioned control circuit 110. In the process S602, the level shifter 114 determines whether the voltage of the power input PW1 rises above a first predetermined voltage (for example, 2.2V). If not, the display device 100 performs the process S604 to convert the first voltage VGH, the second voltage VQ, the third voltage VG, the high-frequency clock signals HC1~HCm, the low-frequency clock signals LC1 and LC2, and the trigger signal ST is maintained at the logic low level. If so, it means that the user may press the power-on button of the display device 100, and the display device 100 will perform the process S606. In the process S604 of an embodiment, the trigger signal ST is switched to a high logic level for a predetermined period of time, and then switched back to a low logic level to reset the multiple internal nodes of the shift register 200 For example, shift the voltages of the first node N1, the first output terminal O1, and the second output terminal O2 of the temporary storage units 300 and 400 to reset the voltages of the gate lines GL1~GLn.

FIG. 7 is a schematic diagram of waveforms illustrating the display operation of the display device 100. Hereinafter, the process S606 will be further described with reference to Figs. 2-7. The display device 100 resets the voltages of multiple internal nodes of the shift register 200 in the process S606, such as the first node N1, the first output terminal O1, and the second output terminal of the shift register units 300 and 400 The voltage of O2 resets the voltages of the gate lines GL1~GLn. When the voltage of the power input PW1 rises above the first predetermined voltage, the control circuit 110 will switch the trigger signal ST from the logic low level to the logic high level in the period E1. In addition, the control circuit 110 also maintains the first voltage VGH, the second voltage VQ, the third voltage VG, the high-frequency clock signals HC1~HCm, and the low-frequency clock signals LC1 and LC2 at the logic low level during the period E1. , Until the trigger signal ST switches from the logic high level to the logic low level.

Therefore, in the period E1, the transistors T1, T4, and T5 of the shift register unit 210[1]~210[m] in Figure 2 will be turned on, and the shift register unit 210[m+1]~ The transistors T4, T5, and T16 of 210[n] will be turned on, and the first node N1, the first output terminal O1, and the second output terminal O2 of the shift register unit 210[1]~210[n] will be turned on. Reset voltage to logic low Bit.

Next, the display device 100 executes the process S608 to periodically set the trigger signal ST, the high-frequency clock signals HC1~HCm, the low-frequency clock signals LC1 and LC2, and the first voltage VGH to the logic high level in the period E2 Switch between and logic low level. Therefore, the shift register units 210[1]~210[n] will sequentially output gate signals G[1]~G[n] and shift signals S[1]~S[n] to update the display device 100 display screen.

FIG. 8 is a schematic diagram of the waveform of part of the signal input to the shift register 200 in a frame time. Hereinafter, the process S608 will be further described with FIGS. 2 to 5 and FIG. 8. For the convenience of description, FIG. 8 only shows a high-frequency clock signal HCm. As shown in FIG. 8, a frame time includes periods F1 and F2. The display device 100 will update the display screen in the period F1 and maintain the same display screen in the period F2. In the period F1, the control circuit 110 maintains the first voltage VGH at a logic high level, and periodically switches the high-frequency clock signals HC1 to HCm between the logic high level and the logic low level. In addition, the control circuit 110 uses the trigger signal ST to provide a pulse P1 with a logic high level.

Therefore, when the trigger signal ST has a logic high level, the transistor T1 of the shift register unit 210[1]˜210[m] will be turned on to set the voltage of the first node N1 to the logic high level. Then, when the high-frequency clock signal HC1~HCm has a high logic level, the transistors T2 and T3 of the shift register unit 210[1]~210[m] will be turned on to output the high-frequency clock signal HC1~ HCm is used as the gate signal G[1]~G[m] and the shift signal S[1]~S[m] respectively.

In the period F2, the control circuit 100 maintains the first voltage VGH and the high-frequency clock signals HC1~HCm at the logic low level. The control circuit 100 also uses the trigger signal ST to provide a pulse P2 with a logic high level.

Therefore, the transistors T1, T4, and T5 of the shift register unit 210[1]~210[m] will be turned on, and the transistors T4, T5 of the shift register unit 210[m+1]~210[n] , And T16 will be turned on, so that the first node N1, the first output terminal O1, and the second output terminal O2 of the shift register units 210[1]~210[n] are all set to logic low levels.

It can be seen from the above that when the display device 100 is about to perform display operation (for example, the period E1 in FIG. 7), the display device 100 resets the voltage of the internal node to surely turn off the transistors T11 in the voltage stabilizing units 326a and 326b. ~T14. Therefore, when the low-frequency clock signals LC1 and LC2 begin to change periodically, the transistors T11~T14 will not be in the conduction state by mistake, thereby avoiding short-circuit currents between the low-frequency clock signals LC1 and LC2 and the second voltage VQ. .

In addition, when the shift register 200 completes the update of a frame image and temporarily does not need to perform the shift register operation (for example, the period F2 in FIG. 8), the display device 100 will adjust the internal of the shift register 200 The node is set to a logic low level, thereby preventing the internal components of the shift register 200 from aging due to long-term bias.

FIG. 9 is a flowchart of a driving method 900 according to an embodiment of the present disclosure. Figures 10 and 11 are schematic diagrams of waveforms when the display device 100 faces different types of power-off events. The driving method 900 is similar to the driving method 600, the difference is that the driving method 900 additionally includes the processes S914~S916 In order to avoid excess charge remaining in the shift register 200 after the aforementioned power-off event. In the process S910, the level shifter 114 determines whether the power input PW1 drops below the aforementioned first predetermined voltage (for example, 2.2V). If not, the display device 100 will execute the aforementioned process S608 again. If it is, it means that the display device 100 may be facing a power-off event, the level shifter 114 will switch to supply power from the capacitor CS, and the display device 100 will then execute the process S912.

In the process S912, the level shifter 114 further determines whether the power input PW1 drops below a second predetermined voltage (for example, 1V). If not, it means that the display device 100 may be faced with the event type in which the external power supply is not removed in the power failure event (for example, the shutdown button is triggered but the plug is not unplugged), and it can still obtain a stable power supply. The process S914 will be executed next. If so, it means that the display device 100 may be faced with the event type of the external power supply has been removed or the component is seriously faulted in the power failure event, and thus cannot obtain a stable power supply. Therefore, the display device 100 will then perform the process S916.

As shown in FIG. 10, the control circuit 110 will combine the high frequency clock signal HC1~HCm, the trigger signal ST, the first voltage VGH, the second voltage VQ, the third voltage VG, the low frequency clock signal LC1 and LC2 switches to the logic high level (period E3). In addition, the trigger signal ST will remain at the logic high level until the control circuit 110 switches the high-frequency clock signals HC1~HCm, the first voltage VGH, the second voltage VQ, the third voltage VG, and the low-frequency clock signals LC1 and LC2. After reaching the logic low level, the control circuit 110 will also switch the trigger signal ST to the logic low level (period E4).

In the period E3, the transistors T1~T15 of the shift register unit 210[1]~210[m] will be turned on, and the transistors T1~ of the shift register unit 210[m+1]~210[n] T16 will turn on. Therefore, the gate signals G[1] to G[n] all have a logic high level to drain the internal charges of the pixel 140.

In the period E4, the transistors T4 and T5 of the shift register unit 210[1]~210[m] will be turned on, and the transistors T4 and T5 of the shift register unit 210[m+1]~210[n] T5 and T16 will be turned on. Therefore, the voltages of the first node N1, the first output terminal O1, and the second output terminal O2 of the shift register units 210[1]~210[n] will be set to logic low levels to discharge the gates. The charge on the line and the charge on the internal node of the shift register 200.

In the period E4 of an embodiment, after the second voltage VQ, the third voltage VG, and the low-frequency clock signals LC1 and LC2 are switched to the logic low level, the first voltage VGH and the high-frequency clock signals HC1~HCm Will switch to logic low level. Therefore, the charges of the second node N2 and the third node N3 of the voltage stabilizing units 326a and 326b are also leaked.

As shown in FIG. 11, the control circuit 110 switches at least the third voltage VG, the trigger signal ST, and the high-frequency clock signals HC1 to HCm to a logic high level in the process S916 (period E5). In addition, the trigger signal ST will be maintained at the logic high level until the control circuit 110 switches the high frequency clock signals HC1~HCm and the third voltage VG to the logic low level, the control circuit 110 will not switch the trigger signal ST also. To the logic low level (period E6).

In period E5, the shift temporary storage unit 210[1]~210[m] At least one of the transistors T1~T5 will enter the conduction state, and at least some of the transistors T1~T5 and T16 will enter the conduction state in the shift register unit 210[m+1]~210[n]. Therefore, the gate signals G[1] to G[n] all have a logic high level to drain the internal charges of the pixel 140.

The operation of the temporary storage units 210[1]~210[n] in the periods E6 and F4 is similar, and for the sake of brevity, the details are not repeated here.

It can be seen from the above that when the display device 100 encounters different types of power-off events, the display device 100 can drain the residual charge inside the panel, thereby preventing internal components from aging due to long-term bias.

The execution sequence of the processes in the foregoing flowcharts is only an exemplary embodiment, and does not limit the actual implementation of the present invention. For example, in the foregoing flowcharts, the process S710 can be performed in parallel with the processes S602 to S608.

In some embodiments, the transistors in the shift temporary storage units 300 and 400 are low-temperature polysilicon transistors, or other transistors that are less prone to aging. Therefore, the shift register units 300 and 400 may only include one of the voltage stabilizing units 326a and 326b, that is, the shift register 200 may perform voltage stabilization operation only based on a low-frequency clock signal. In this case, when the display device 100 including the shift register 200 executes the aforementioned driving methods 600 and 900, only the voltage level of a corresponding low-frequency clock signal can be adjusted.

In the specification and the scope of the patent application, certain words are used to refer to specific elements. However, a person with ordinary knowledge in the relevant technical field should understand that the same element may be called by different terms. The specification and the scope of patent application do not use the difference in name as a way to distinguish components. The difference is based on the functional difference of the components as the basis for distinction. The "including" mentioned in the specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection methods, or through other elements or connections. The means is indirectly connected to the second element electrically or signally.

The description method of "and/or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case.

300‧‧‧shift temporary storage unit

310‧‧‧Output circuit

320‧‧‧Regulatory and reset circuit

322‧‧‧Reset Unit

324‧‧‧Pull-down unit

326a, 326b‧‧‧stabilizing unit

T1~T15‧‧‧Transistor

C1‧‧‧Capacitor

N1, N1[m-2]‧‧‧First node

N2‧‧‧Second node

N3‧‧‧The third node

VGH‧‧‧First voltage

VQ‧‧‧Second voltage

VG‧‧‧Third voltage

ST‧‧‧Trigger signal

HCm‧‧‧High frequency clock signal

LC1~LC2‧‧‧Low frequency clock signal

G[m]‧‧‧Gate signal

S[m], S[m+m]‧‧‧shift signal

O1‧‧‧First output

O2‧‧‧Second output

Claims (11)

A shift register includes: n stages of shift register units, and n is a positive integer, wherein each of the n stages of shift register units includes: an output circuit including a first node, a first node An output terminal and a second output terminal are used to transmit a first voltage to the first node, and are used to output m highs at the first output terminal and the second output terminal according to the voltage of the first node One of the corresponding one of the high-frequency clock signals, where m is a positive integer; a voltage stabilizing and resetting circuit is used to transmit a second voltage to the first node according to a low-frequency clock signal, and according to a trigger signal The second voltage and a third voltage are respectively transmitted to the first output terminal and the second output terminal; wherein, the shift register is coupled to a control circuit, and when the control circuit determines that a power input rises above At a first preset voltage, the trigger signal is switched to a logic high level, and the m high-frequency clock signals, the low-frequency clock signals, the first voltage, the second voltage, and the third voltage Maintaining at a logic low level until the trigger signal is switched from the logic high level to the logic low level to reset the voltage of the first node. The shift register according to claim 1, wherein the output circuit of each of the first to m-th stages of shift register units in the n-stage shift register unit is used to respond to the trigger signal The first voltage is delivered to the first node. The shift register according to claim 2, wherein the n-stage shift register unit is used to output a plurality of shift signals, and the output circuit of each shift register unit transmits through the first output terminal A corresponding one of the multiple shift signals is output, and the multiple output circuits of the m+1 to n-th shift temporary storage units in the n-level shift temporary storage unit are each used for according to the multiple shift temporary storage units. The corresponding one of the bit signals transmits the first voltage to the respective first node. The shift register according to claim 1, wherein the reset circuit of each of the n-stage shift register units includes: a first transistor including a first terminal, a second terminal, And a control terminal, wherein the first terminal of the first transistor is coupled to the first output terminal, the second terminal of the first transistor is used for receiving the second voltage, and the The control terminal is used to receive the trigger signal; and a second transistor, including a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor is coupled to the second output terminal , The second terminal of the second transistor is used for receiving the third voltage, and the control terminal of the second transistor is used for receiving the trigger signal. The shift register according to claim 4, wherein the reset circuit of each of the m+1 to nth stages of shift register units in the n stages of shift register units further includes a first Three transistors, and the third transistor includes a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the first node, the second terminal of the third transistor is used for receiving the second voltage, and the control terminal of the third transistor is used for receiving the trigger signal. The shift register according to claim 1, wherein when the control circuit determines that the power input drops below the first preset voltage, the m high-frequency clock signals, the trigger signal, and the The third voltage is switched to the logic high level, and until the m high-frequency clock signals and the third voltage are switched from the logic high level to a logic low level, the trigger signal is switched to the logic low level Bit. A driving method suitable for a display device, wherein the display device includes a shift register and a control circuit for providing a trigger signal, a first voltage, a second voltage, and a third voltage , M high-frequency clock signals, and a low-frequency clock signal to the shift register, and the driving method includes: when the control circuit determines that a power input is higher than a first preset voltage, the control circuit The trigger signal is switched to a logic high level, and the first voltage, the second voltage, the third voltage, the m high-frequency clock signals, and the low-frequency clock signal are maintained at a logic low level Until the trigger signal is switched from the logic high level to the logic low level to reset the voltages of the multiple internal nodes of the shift register; and use the control circuit to the trigger signal and the m high Frequency clock signal, the low frequency clock signal, and the first voltage periodically in the logic Switch between the high level and the logic low level to update a display screen of the display device. The method according to claim 7, further comprising: when the control circuit determines that a power input is lower than the first preset voltage, the control circuit performs the m high-frequency clock signals, the trigger signal, and the first The three voltages are switched to the logic high level, and the trigger signal is switched to the logic low level until the m high-frequency clock signals and the third voltage are switched from the logic high level to the logic low level . The method according to claim 8, wherein the process of the control circuit switching the m high-frequency clock signals, the trigger signal, and the third voltage to the logic high level includes: if the power input is lower than the logic high level The first preset voltage is higher than a second preset voltage, and the control circuit uses the m high-frequency clock signals, the trigger signal, the first voltage, the second voltage, the third voltage, and the low-frequency clock signal. The pulse signal is switched to the logic high level, wherein until the m high-frequency clock signals, the first voltage, the second voltage, the third voltage, and the low-frequency clock signal are switched to the logic low level , The trigger signal is switched to the logic low level; and if the power input is lower than the second preset voltage, the control circuit switches the m high-frequency clock signals, the trigger signal, and the third voltage to The logic high level, wherein the trigger signal is switched off until the m high-frequency clock signals and the third voltage are switched from the logic high level to the logic low level Switch to the logic low level. The method according to claim 7, wherein the trigger signal, the m high-frequency clock signals, and the low-frequency clock signal are periodically set between the logic high level and the logic low level by using the control circuit The process of switching between switches includes: in a frame, when the first voltage has the logic high level, using the trigger signal to provide a first pulse so that the shift register sequentially outputs a plurality of gate signals And in the frame, when the first voltage has the logic low level, the trigger signal is used to provide a second pulse to reset the shift register. A display device comprising: a control circuit; a shift register for receiving a trigger signal, a first voltage, a second voltage, a third voltage, and m high-frequency clock signals from the control circuit , And a low-frequency clock signal, and includes n-level shift register units, where n is a positive integer, and each of the n-level shift register units includes: an output circuit, including a first node, a A first output terminal and a second output terminal are used to transmit a first voltage to the first node, and are used to output the m at the first output terminal and the second output terminal according to the voltage of the first node Corresponding one of the two high-frequency clock signals, where m is a positive integer; a voltage stabilization and reset circuit is used to convert A second voltage is transmitted to the first node, and the second voltage and a third voltage are respectively transmitted to the first output terminal and the second output terminal according to a trigger signal; wherein, the shift register is coupled Connected to a control circuit, when the control circuit determines that a power input rises above a first preset voltage, the trigger signal switches to a logic high level, and the m high-frequency clock signals and the low-frequency clock Signal, the first voltage, the second voltage, and the third voltage are maintained at a logic low level until the trigger signal is switched from the logic high level to the logic low level to reset the first node Voltage.

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