TW202022938A - Slotting method for suppressing defects capable of preventing cracks generated by dividing a wafer from exceeding a metamorphic region and avoiding grain defects - Google Patents

Abstract

The present invention relates to a slotting method for suppressing defects, which is a wafer division process. The method includes the following steps: firstly, defining a first processing line from one side of a wafer dividing line of a wafer; performing laser processing at a processing position of the first processing line with a low-power laser, such that a processing groove and a laser processing heat affected zone are formed at the processing position by a laser processing; successively, performing laser processing with the low-power laser at different depths of the processing position until the depth of the processing groove meets a predetermined depth; then, performing laser processing at a plurality of successive processing positions of the first processing line with the low-power laser until the processing of the first processing line is completed; and finally cutting off the wafer dividing line by a processing.

Description

Slotting method to suppress defects

The present invention relates to a pre-processing method for wafer dicing, and in particular to splitting the wafer and causing cracks at the dicing site. The integrated circuit damage caused by the dicing cracks. The continuous processing of low-power lasers generates processing grooves to limit cutting. Crack range.

After the semiconductor device is processed, the surface of the semiconductor wafer is successively formed into a grid-shaped wafer dividing line to divide into a plurality of areas, and then each area is divided along the wafer dividing line to make each The semiconductor components.

In recent years, due to the tendency of miniaturization of products, the dies are generally divided by laser processing, and each area on the surface is divided along the predetermined line of wafer dividing, so that the dies are divided from the wafer.

The following documents on wafer cutting, multiple patents are as follows:

US 61/267,194 discloses a laser stripping system and method, which can be used to provide integral laser stripping and minimize cracks by reducing the size of one or more beam spots in one or more dimensions to Reduce plume pressure while maintaining enough energy to achieve separation. By irradiating irradiated areas with various shapes and patterns, these laser stripping systems and methods can more effectively use laser energy, reduce cracks during layer separation, and improve productivity. Certain laser lift-off systems and methods described herein separate individual material layers by irradiating the lift off zone (LOZ) to extend the laser lift off zone (LOZ) beyond the non-adjacent irradiation zone of the irradiation zone. As described in this article Other laser stripping systems and methods separate each material layer by shaping the irradiation area and by controlling the overlap of each irradiation area in a way that prevents the workpiece from being unevenly exposed. According to at least one embodiment, a laser lift-off system and method can be used to provide integrated lift-off of one or more epitaxial layers on a substrate of a semiconductor wafer.

JP2013-193200 discloses a method for processing a wafer that can be internally processed even when an insulating reinforcing sheet is attached to the back of the wafer. The solution is to form a grid on the surface with a plurality of predetermined dividing lines while forming a wafer with devices formed in a plurality of regions divided by the plurality of predetermined dividing lines, and divide the wafers into individual devices along the predetermined dividing lines. The round processing method includes a protective member attaching step of attaching a protective member to the surface of a wafer, a back grinding step of grinding the back of the wafer to form a predetermined thickness, and a back surface of the wafer from the back side of the wafer. The laser light of the penetrating wavelength is positioned inside the condensing point to be irradiated along the planned dividing line, and then forming the reforming layer inside the wafer along the planned dividing line. Reinforcement sheet installation step for installing a reinforcement sheet with insulation function, a reinforcement sheet heating step for heating the reinforcement sheet to solidify the reinforcement sheet, attaching dicing tape to the cured reinforcement sheet installed on the back of the wafer, and The wafer support step of mounting the outer peripheral portion of the dicing tape on the ring frame, and the dividing step of applying external force to the wafer to divide the wafer into individual devices, while breaking the reinforcing sheet along the individual devices.

TW I603391 discloses a laser cutting method for semiconductor wafers, which includes the following steps: step one, providing a semiconductor wafer having a front surface and a back surface provided with a plurality of circuit elements, and The semiconductor chip is turned over so that the back side faces up and the front side faces down; step two, apply an adhesive layer on a tape base film, and attach the front side of the semiconductor chip to the adhesive layer, and The glue layer is heated to fill the glue layer In the gap between the tape base film and the semiconductor chip; and, in step three, a laser is preset on the back of the semiconductor chip and located between the respective circuit elements by a laser cutter The laser full cut through cutting is performed on the shot cutting path to form a plurality of dies with the circuit element.

However, it is generally known in the industry that the semiconductor device manufacturing process is based on the functional layer of insulating film and functional film laminated on the surface of a silicon substrate, and a plurality of IC, LSI and other components constitute a matrix-shaped semiconductor wafer ; And, the semiconductor wafer is divided by a predetermined dividing line called a dicing lane to divide the above-mentioned components, and individual semiconductor components are manufactured by dividing along the dicing lane. When laser processing is used to divide components, cracks will inevitably occur on both sides of the dicing path on the wafer, and the multilayer structure of semiconductors is likely to cause the density of each layer to be different, which will cause thermal stress generated by laser processing. The cracks are more serious.

Please refer to Figure 1a, a wafer (10) has a first integrated circuit structure (14) and a second integrated circuit structure (15) and other integrated circuit products, on the surface of the wafer (10) Define a wafer dicing line (11); the wafer dicing line (11) is processed by a laser, as shown in Figure 1b (this figure is the build-up layer processed on the substrate), and the wafer dicing line (11) Irregular cracks are generated on the side, and these irregular cracks are adjacent to the first integrated circuit structure (14) and the second integrated circuit structure (15) and other integrated circuit products; when the first integrated circuit structure (14) and When the second integrated circuit structure (15) is a product component, the electrical connection is likely to be unstable, and the surface of the wafer (10) shows irregular cracks as shown in Figure 1c.

Therefore, in order to solve the above problems, the main purpose of the present invention is to provide a slotting method that suppresses defects so as to improve the above problems.

In view of the above problems, the present invention provides a slotting method that suppresses defects. Continuously process grooves to limit the cracks generated by laser processing within the range.

Therefore, the main purpose of the present invention is to provide a grooving method that suppresses defects, and achieves the purpose of improving the wafer processing yield by continuously processing the grooves generated by the separation.

Another object of the present invention is to provide a grooving method that suppresses defects, generates laser processing heat-affected zones through processing grooves, and further releases thermal stress cracks generated by laser processing in advance.

Another object of the present invention is to provide a grooving method for suppressing defects, which uses multiple laser processing to generate connected processing grooves, which can avoid residual thermal stress in the multilayer structure.

Another object of the present invention is to provide a slotting method that suppresses defects, which can be selectively used in areas with high integrated circuit density, which can improve yield and reduce costs.

In order to achieve the above objective, the main technical means used in the present invention are achieved by the following technical solutions. The present invention is a grooving method for suppressing defects, which is a wafer dicing process, which includes: Step 1: Define a first processing line from one side of a wafer dicing line of a wafer; Step 2: Use a low The power laser performs laser processing at a processing position of the first processing line, and the laser processing produces a processing groove and a laser processing heat-affected zone at the processing position, and then the low-power laser is applied to the processing position Laser processing is performed at different depths until the processing groove depth meets the predetermined; Step 3: Then the low-power laser is used to sequentially perform laser processing at the multiple consecutive processing positions of the first processing line until the first processing line The processing line completes the processing; Step 4: The wafer dividing line is then cut off by processing.

The purpose of the present invention and the solution of its technical problems can be further achieved by adopting the following technical measures.

In the foregoing method, in step 1, at the same time, one of the wafers and the other The side defines a second processing line.

In the foregoing method, after step 3, the low-power laser is used to perform laser processing at a processing position of the second processing line, and the laser processing generates a processing groove and a laser processing heat-affected zone at the processing position , Continue to use the low-power laser to perform laser processing at the processing position until the processing groove depth meets the preset.

In the foregoing method, the low-power laser is then used to sequentially perform laser processing on the plurality of consecutive processing positions of the second processing line until the second processing line completes processing.

In the aforementioned method, a part of the heat-affected zone of the laser processing is vaporized by the low-power laser during the subsequent laser processing of the processing position.

In the foregoing method, the processing and cutting of the wafer dicing line in step 4 refers to the rapid cutting of the wafer dicing line by a high-power laser.

In the foregoing method, the processing and cutting of the wafer dicing line in step 4 means that the diamond cutting equipment quickly cuts the wafer dicing line.

In the aforementioned method, there is no overlap between the processing position and the consecutive processing positions.

In the aforementioned method, the processing position and the processing grooves generated by the consecutive processing positions overlap each other.

In the aforementioned method, the low-power laser can emit three shots simultaneously.

Compared with the conventional technology, the present invention has the following effects: (1) The separation produced by the continuous processing grooves is used to achieve the purpose of improving the wafer processing yield; (2) The laser processing heat-affected zone is generated by processing the grooves, Further release the thermal stress cracks caused by laser processing in advance; (3) Selective use in areas with high integrated circuit density can increase yield and reduce costs.

10‧‧‧ Wafer

11‧‧‧Wafer dividing line

12‧‧‧The first processing line

121‧‧‧Processing position

121`‧‧‧Processing position

122‧‧‧Machining groove

122’‧‧‧Machining groove

123‧‧‧Heat Affected Zone of Laser Processing

13‧‧‧Second processing line

131‧‧‧Processing position

131`‧‧‧Processing position

132‧‧‧Machining groove

133‧‧‧Heat Affected Zone of Laser Processing

14‧‧‧The first integrated circuit structure

15‧‧‧Second integrated circuit structure

21‧‧‧Step 1

21a‧‧‧Step 1a

22‧‧‧Step 2

23‧‧‧Step 3

23a‧‧‧Step 3a

23b‧‧‧Step 3b

24‧‧‧Step 4

Figure 1a: It is a top view of a wafer of the prior art.

Figure 1b: is a cross-sectional view of the prior art wafer after dicing.

Figure 1c: It is a top view of the prior art wafer after dicing.

Figure 2a: is the first top view of the wafer in the first embodiment of the present invention.

Figure 2b: is a schematic diagram of the first processing line and processing position of the first embodiment of the present invention.

Figure 2c: is a schematic diagram of the processing groove of the first processing line of the first embodiment of the present invention.

Figure 2d: is a schematic diagram of the processing groove and the laser processing heat-affected zone of the first processing line of the first embodiment of the present invention.

Figure 2e: is a schematic view of the processing groove of the first processing line of the first embodiment of the present invention not being completely broken.

Figure 3a: is the first cross-sectional view of the processing groove of the first processing line of the best embodiment of the present invention.

Figure 3b: is the second cross-sectional view of the processing groove of the first processing line of the best embodiment of the present invention.

Figure 3c: is the third cross-sectional view of the processing groove of the first processing line of the best embodiment of the present invention.

Figure 3d: is the first cross-sectional view of the wafer dicing line after laser processing in the preferred embodiment of the present invention.

Figure 3e: Wafer dicing line after laser processing in the best embodiment of the invention The second cross-sectional view.

Figure 4a: is a second top view of the wafer in the second embodiment of the present invention.

Figure 4b: is a schematic diagram of the second processing line and processing position of the second embodiment of the present invention.

Fig. 4c is a schematic diagram of the processing groove of the second processing line of the second embodiment of the present invention.

Figure 4d: is a schematic diagram of the processing groove and the laser processing heat-affected zone of the second processing line of the second embodiment of the present invention.

Figure 4e: is a third cross-sectional view of the wafer dividing line after laser processing in the second embodiment of the present invention.

Figure 5a: is a flowchart of the first embodiment of the present invention.

Figure 5b: is a flowchart of the second embodiment of the present invention.

In order to make the purpose, features and effects of the present invention more comprehensible, the following specifically lists the first embodiment of the present invention:

First, refer to the flowchart shown in Figure 5a, which consists of step 1 (21), step 2 (22), step 3 (23), and step 4 (24).

Among them, as shown in Figures 2a and 5a, this step 1 (21) is to define a first processing line (12) from one side of a wafer (10) and a wafer dividing line (11)

In layman's terms, wafer (10) refers to the silicon chip used in the production of silicon semiconductor integrated circuits. In this case, wafer (10) is presented as a build-up on the silicon chip. In practice, it can also include the silicon chip part; , The wafer dividing line (11) refers to the planning line that will be processed on the wafer (10), Individual semiconductor components are manufactured by dividing the dicing line along the wafer dividing line (11); the first processing line (12) is a line segment parallel to the wafer dividing line (11), and the processing position is provided (121) For positioning purposes.

Among them, as shown in Figures 2b, 3a and 5a, this step 2 (22) is to use a low-power laser to perform laser processing at one of the processing positions (121) of the first processing line (12). A processing groove (122) and a laser processing heat-affected zone (123) are generated at the processing position (121), and then the low-power laser is used for laser processing at different depths of the processing position (121), Until the depth of the processing groove (122) meets the predetermined.

Generally speaking, "laser processing" must be explained first. Laser processing uses the high-intensity and high parallelism of laser light to converge it to a power density of 103~109 watts/cm² by focusing lens and other optical devices. After the light spot, local heating, melting, vaporization and other thermal effects are generated on the surface of the workpiece to achieve the purpose of processing. Because the time to convert light energy into heat energy is very short, and the power density is quite high, it provides extremely high light energy per unit time and unit area, so that the surface of the material can obtain a large amount of heat energy in an instant. The speed of heating the surface of the material can generally reach thousands of degrees per second, and the mixed mode of "liquid/gas" or "solid/gas" is prone to occur in the process of laser processing; the low-power laser means super High-speed and low-energy Pulsed Lasers, such as picosecond lasers. Relatively high-energy laser processing often changes materials due to thermal energy and cannot achieve detailed processing. An ideal industrial-grade picosecond laser The source should generate pulse energy in the range of 10~50μJ and a repetition rate of about 1MHz. The better one can use the burst mode to achieve several picosecond pulses, which can significantly improve the stripping rate and the quality of micro-processing. The definition of burst mode refers to the rapid and continuous generation of pulses in the nanosecond time interval. Compared with a longer interval time (such as nanosecond time), the same effect of increasing the removal rate will not be produced. In this case, there are three consecutive shots; the processing position (121) refers to the plane position where the low-power laser focus is processed. It can be seen that the processing position (121) and the continuous processing position (121`) shown in Figure 2b, There is no overlap between the positions; and the processing groove (122) is produced by the laser processing on the wafer (10) at the processing position (121), which can be seen in Figure 3a, and its function is to reduce the processing and cutting of the When the wafer dicing line (11), cracks derive beyond the processing groove (122) to prevent semiconductor components from being affected; the laser processing heat affected zone (123) is laser processing on the wafer (10) at the processing position (121) The surrounding area is essentially due to the gasification and extrusion of the processed groove (122), resulting in a cracked area around the processed groove (122).

As shown above, continue to perform laser processing at different depths of the processing position (121) with the low-power laser until the depth of the processing groove (122) meets the preset; among them, please refer to Figures 3a, 3b and 3c. It can be seen that part of the laser processing heat-affected zone (123) is vaporized by the low-power laser during the subsequent laser processing of the processing position (131).

Among them, as shown in Figures 2c, 2d, and 5a, the step 3 (23) is followed by the low-power laser in sequence at the multiple consecutive processing positions (121, 121`) of the first processing line (12). Processing until the first processing line (12) completes processing.

Generally speaking, the same laser processing as in step 2 (22) is carried out at the multiple consecutive processing positions (121, 121`) of the first processing line (12) in order until the depth of the processing groove (122) meets the predetermined; Figure 2c shows that the processing position (121) and the processing grooves (122) generated by the consecutive processing positions (121) overlap each other (the remaining laser processing heat affected zone (123) at the bottom also overlaps each other, Refer to Figure 2d); when the processing positions (121, 121`) of the first processing line (12) are all processed, you can see the processing groove (122) shown in Figure 2c; in addition, you can refer to Figure 2e again Machining groove (122) and processing groove (122') are essentially unfinished Fully bonded, so that factors such as laser processing energy and processing materials may affect the bonding state between the processed grooves (122, 122').

Finally, as shown in Figures 3e and 5a, the step 4 (24) is to cut the wafer dividing line (11) by processing.

Specifically, processing and cutting the wafer (10) division line refers to the rapid cutting of the wafer division line (11) by a high-power laser; or, processing and cutting the wafer (10) division line refers to diamond The cutting device quickly cuts the wafer dividing line (11).

Hereinafter, taking the first embodiment of a slotting method for suppressing defects of the present invention as an example, a detailed description of the implementation process of the present invention is as follows.

First, referring to Figure 2a, first determine the location of a wafer dividing line (11) required for cutting a wafer (10); then, referring to Figures 2a and 2b, in the first integrated circuit structure (14) A first processing line (12) is defined between the wafer dividing line (11) and the wafer dividing line (11) and the first processing line (12) is a processing lossable area.

Then, since the wafer (10) is composed of a multi-layer structure, after scanning and positioning one of the processing positions (121) of the first processing line (12), the laser can penetrate the wafer (10) continuously. Laser is used to make the processing groove (122), and the laser processing is currently recommended as picosecond laser. Using the laser pulse width below 15 picoseconds (ps, picosecond), the light energy will not diffuse to the surroundings. Reduce the interference to the outside of the processing area, and the time difference between consecutive multiple lasers is between tens of picoseconds (ps, picosecond) to tens of nanoseconds (ns, nanoseconds); first refer to Figure 3a, which is represented by the laser Processed on the processing position (121) of the wafer (10), a processing groove (122) and the surrounding laser processing heat-affected zone (123) begin to be generated. At this time, the laser processing is in the first integrated circuit structure (14)Upper position; follow, refer to Figure 3b, which is processed by laser in the processing groove of wafer (10) (122) Continuous laser processing, so that the processing groove (122) and the surrounding laser processing heat-affected zone (123) continue to extend downward, and part of the laser processing heat-affected zone (123) is controlled by the low-power laser It vaporizes during laser processing at the processing position (131). In addition, referring to Figure 3c, the processing groove (122) of the wafer (10) is processed by the laser to continue laser processing, so that The processing groove (122) and the remaining laser processing heat-affected zone (123) around it extend to the other surface of the wafer; in practice, when the processing groove (122) is scanned and positioned, the laser processing The circle (10) is driven by the platform (XY TABLE), but the speed of the platform (1m/s) is relative to the speed of laser processing (ns level), which has no effect on laser processing.

As shown in Figure 2c, the laser starts from one end of the first processing line (12) to the other end, and executes the laser processing in the multiple consecutive processing positions (121, 121`) of the first processing line (12) in sequence Achieve until the depth of the processing groove (122) meets the preset, as shown in Figure 2c, the processing position (121) and the processing grooves (122) generated by the consecutive processing positions (121) overlap each other. See also The remaining laser processing heat-affected zones (123) at the bottom of Figure 2d also overlap each other; the first isolation holes (1211) appear as shown in Figure 2d, and the processing grooves (122) and the surrounding laser processing heat affect The section state of area (123) is shown in Figure 3c.

Finally, as shown in Figures 3e and 5a, the wafer dicing line (11) is cut by a high-power laser rapid cutting process.

From the above, the first embodiment of the grooving method for suppressing defects of the present invention has been completed. Finally, referring to Figure 3d, the laser starts from one end to the other end of the wafer dividing line (11) to cut the wafer Circle (10), it can be seen that there is a crack in the wafer dividing line (11) of the laser processing and the first integrated circuit structure (14) by the processing groove (122) and the surrounding residual laser processing heat-affected zone (123) ) Isolation, at this time the first integrated circuit structure (14) yield rate will definitely increase; also As shown in Fig. 3e, another wafer dividing line (11) is located on the other side of the second integrated circuit structure (15). At this time, there are no other semiconductor components on the other side of the second integrated circuit structure (15). Another wafer split line (11) produced by laser processing is separated from the second integrated circuit structure (15) by the processing groove (122) and the surrounding residual laser processing heat affected zone (123).

As shown in Figures 4a, 4b, 4c, 4d, 4e, and 5b, it is the second embodiment of a slotting method for suppressing defects of the present invention; in the first embodiment and the second embodiment of 2a, 2b, 2c, 2d, The features described in figures 3a, 3b, 3c, 3d, 3e and 5b are the same as those in figures 4a, 4b, 4c, 4d, 4e and 5b, and the symbols in figures 4a, 4b, 4c, 4d, 4e and 5b The mark or omission will not be repeated. The main method difference between the second embodiment and the first embodiment is that step 1a (21a), step 3a (23a) and step are added in comparison between Figure 5b of the second embodiment and Figure 5a of the first embodiment. 3b(23b).

First, refer to the flowchart shown in Figure 5b, which consists of step 1(21), step 1a(21a), step 2(22), step 3(23), step 3a(23a), step 3b(23b) and Step 4 (24) constitutes.

Among them, as shown in Figures 4a and 5b, this step 1 (21) is to define a first processing line (12) from one side of a wafer (10) and a wafer dividing line (11); at the same time, perform Step 1a (21a) is to define a second processing line (13) for the other side of a wafer dividing line (11) of the wafer (10).

Wherein, the second processing line (13) is a line segment parallel to the wafer dividing line (11) and is used for positioning the processing position (131).

Among them, as shown in Figures 2b, 3a and 5b, this step 2 (22) is to use a low-power laser to perform laser processing at one of the processing positions (121) of the first processing line (12). A processing groove (122) and a laser processing heat-affected zone (123) are generated at the processing position (121), and then the low-power laser is used to perform laser at different depths of the processing position (121) Process until the depth of the processed groove (122) meets the preset; then, as shown in Figures 2c, 2d, and 5a, step 3 (23) is followed by the low-power laser in the first processing line ( 12) Laser processing is carried out at the multiple consecutive processing positions (121, 121`) until the first processing line (12) is completed.

Again, referring to Figures 3a, 4b and 5b, the step 3a (23a) is to use the low-power laser to perform laser processing at one of the processing positions (131) of the second processing line (13). A processing groove (132) and a laser processing heat-affected zone (133) are generated at the processing position (131), and then the low-power laser is used to perform laser processing at the processing position (131) until the processing The depth of the groove (132) meets the predetermined; then, as shown in Figures 4c, 4d, and 5b, the step 3b (23b) is followed by the low-power laser in sequence on the second processing line (13). The processing position (131) performs laser processing until the second processing line (13) completes processing.

Finally, as shown in Figures 4e and 5b, the wafer dicing line (11) is cut by a high-power laser rapid cutting process.

Therefore, the effect of the present invention is different from the general grooving method. It is the first in semi-conducted cutting, and it meets the requirements of the invention patent.

However, it needs to be reiterated that the above are only the preferred implementation forms of the present invention. Any equivalent changes made by applying the specification, scope of patent application, or drawings of the present invention still belong to the technical scope protected by the present invention. Therefore, The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10‧‧‧ Wafer

11‧‧‧Wafer dividing line

122‧‧‧Machining groove

123‧‧‧Heat Affected Zone of Laser Processing

14‧‧‧The first integrated circuit structure

15‧‧‧Second integrated circuit structure

Claims (10)

A grooving method for suppressing defects is a wafer slicing process, which includes: Step 1: Define a first processing line from one side of the wafer dicing line of a wafer; Step 2: Use a low-power laser Laser processing is performed at a processing position of the first processing line, and the laser processing produces a processing groove and a laser processing heat-affected zone at the processing position, followed by the low-power laser at different depths of the processing position Perform laser processing again until the depth of the processing groove meets the preset; Step 3: Then use the low-power laser to sequentially perform laser processing at the multiple consecutive processing positions of the first processing line until the first processing line is completed Processing; Step 4: Then cut the wafer dividing line by processing. According to the method described in the first item of the scope of patent application, wherein at the same time as step 1, a second processing line is defined on the other side of the wafer dividing line of one of the wafers. The method described in item 2 of the scope of patent application, wherein after step 3, the low-power laser is used to perform laser processing at a processing position of the second processing line, and the laser processing produces a processing groove at the processing position And a laser processing heat-affected zone, followed by laser processing at the processing position with the low-power laser until the processing groove depth meets the preset. According to the method described in item 3 of the scope of patent application, the low-power laser is then used to sequentially perform laser processing on the plurality of consecutive processing positions of the second processing line until the second processing line is completed. For the method described in item 1 or 3 of the scope of patent application, part of the heat-affected zone of the laser processing is vaporized by the low-power laser during the subsequent laser processing of the processing position. For the method described in item 1 of the scope of patent application, the processing and cutting of the wafer dicing line in step 4 refers to the rapid cutting of the wafer dicing line by a high-power laser. For the method described in item 1 of the scope of patent application, the processing and cutting of the wafer dicing line in step 4 means that the diamond cutting equipment quickly cuts the wafer dicing line. For the method described in item 1 or 4 of the scope of patent application, there is no overlap between the processing position and the successive processing positions. For the method described in item 1 or 4 of the scope of patent application, the processing position and the processing grooves generated by the consecutive processing positions overlap each other. Such as the method described in item 1 or 4 of the scope of patent application, wherein the processing position is connected to the The processing grooves generated by the processing position overlap each other.

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