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TW202027236A - Packaging structure for reducing residual air and method thereof capable of effectively preventing the chip module package from electrical connection failure - Google Patents

Packaging structure for reducing residual air and method thereof capable of effectively preventing the chip module package from electrical connection failure Download PDF

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Publication number
TW202027236A
TW202027236A TW108100190A TW108100190A TW202027236A TW 202027236 A TW202027236 A TW 202027236A TW 108100190 A TW108100190 A TW 108100190A TW 108100190 A TW108100190 A TW 108100190A TW 202027236 A TW202027236 A TW 202027236A
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TW
Taiwan
Prior art keywords
chip module
substrate
conductive
gasket
active surface
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TW108100190A
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Chinese (zh)
Inventor
陳文科
林育民
陶聖璋
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華東科技股份有限公司
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Priority to TW108100190A priority Critical patent/TW202027236A/en
Publication of TW202027236A publication Critical patent/TW202027236A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention describes a packaging structure for reducing residual air and a method thereof, which are applied to chip module packaging and can be implemented in various embodiments. In one embodiment, a spacer is fixed to an active surface of a substrate by an adhesive material, and a chip module is disposed on one side of the spacer. The chip module has a plurality of conductive balls combined with a plurality of conductive points of the active surface. A plurality of solder balls are implanted on a plurality of pre-implantation points on the back of the substrate. An insulating package covers the chip module, the spacer and the active surface. In another embodiment, a spacer is fixed on the conductive surface of a chip module by an adhesive material. The spacer is disposed on one side of the active surface of a substrate. The chip module has a plurality of conductive balls combined with a plurality of conductive points of the active surface. A plurality of solder balls are implanted on a plurality of pre-implantation points on the back of the substrate. An insulating package covers the chip module, the spacer and the active surface. According to the above examples, the chip module package can be effectively improved, which often causes electrical connection failure due to excess amount of residual air.

Description

減少空氣殘留的封裝結構及其方法 Packaging structure and method for reducing air residue

本發明係關於一種晶片模組封裝,特別要降低晶片模組在封裝後,因氣體侵入封裝體內,導致爆米花現象,進而導致晶片模組引出的錫球電性連結不穩定,使最終產品可靠度下降。 The present invention relates to a chip module package, in particular to reduce the popcorn phenomenon caused by gas intruding into the package body after the chip module is packaged, which in turn leads to unstable electrical connections of the solder balls drawn from the chip module, so that the final product is reliable Degree drops.

半導體封裝(semiconductor package)是指一種用於容納、包覆一個以上半導體元件或積體電路的載體/外殼,半導體封裝為晶片提供一定的保護,為晶片提供與外部電路連接的引腳或觸點,在晶片工作時幫助將晶粒工作產生的熱量帶走。 Semiconductor package (semiconductor package) refers to a carrier/housing used to contain and wrap more than one semiconductor element or integrated circuit. The semiconductor package provides a certain degree of protection for the chip, and provides pins or contacts for the chip to connect to the external circuit. , When the wafer is working, it helps to take away the heat generated by the die work.

在封裝的過程中,一般至於具有低污染水準的環境中加工,此處所指的污染來源有灰塵、空氣傳播的微生物和化學揮發性氣體等等,尤其在半導體業對室內之溫濕度、潔淨度要求特別嚴格,故其必須控制在某一個需求範圍內,才不會對製程產生影響。 In the packaging process, generally as for processing in an environment with a low pollution level, the pollution sources referred to here include dust, airborne microorganisms and chemical volatile gases, etc., especially in the semiconductor industry for indoor temperature, humidity, and cleanliness. The requirements are particularly strict, so it must be controlled within a certain range of requirements so that it will not affect the manufacturing process.

然而,在嚴格要求的環境下,製作封裝仍然會有眾多因素導致封裝體損壞。 However, in a strictly required environment, there are still many factors that cause the package to be damaged.

關於封裝之文獻,多個專利如下: Regarding the packaging literature, several patents are as follows:

TW I441296揭示一種封裝結構及其製法,該封裝結構係包括置晶墊、跡線、電性接點、第一電鍍層、第二電鍍層、第三電鍍層、半導體晶片、封裝材料及防銲層,該跡線的厚度係小於該電性接點的厚度, 該第一電鍍層係形成於該跡線與該電性接點的一表面上,該第二電鍍層係形成於該電性接點與該置晶墊之另一表面上,該第三電鍍層係形成於該跡線之另一表面上,該半導體晶片係設於該置晶墊上,該封裝材料係包覆該半導體晶片、第一電鍍層、跡線的部分側表面、與電性接點的部分側表面,該防銲層係覆蓋該第三電鍍層、封裝材料、跡線的部分側表面、與電性接點的部分側表面。本發明除了可避免該跡線與電性接點的銲料橋接,還能夠使該防銲層不易產生會導致爆米花效應的氣泡。 TW I441296 discloses a package structure and its manufacturing method. The package structure includes chip placement pads, traces, electrical contacts, a first electroplating layer, a second electroplating layer, a third electroplating layer, a semiconductor chip, packaging materials, and solder resist Layer, the thickness of the trace is smaller than the thickness of the electrical contact, The first electroplating layer is formed on one surface of the trace and the electrical contact, the second electroplating layer is formed on the other surface of the electrical contact and the chip placement pad, and the third electroplating The layer is formed on the other surface of the trace, the semiconductor chip is set on the wafer placement pad, and the packaging material covers the semiconductor chip, the first electroplating layer, part of the side surface of the trace, and is electrically connected Part of the side surface of the point, the solder mask covers the third electroplating layer, the packaging material, part of the side surface of the trace, and part of the side surface of the electrical contact. In addition to avoiding solder bridging between the trace and the electrical contact, the present invention can also make the solder resist layer less likely to generate bubbles that can cause popcorn effect.

TW I635595揭示一種晶片封裝體,包括電路板、封裝膠體、複數個導電結構以及電磁干擾防護層。電路板包括複數個接地導電墊,設置於其下表面上。封裝膠體設置於電路板的上表面上。導電結構設置於封裝膠體中,並電連接接地導電墊,其中各導電結構的端點從封裝膠體的側壁露出。電磁干擾防護層設置於封裝膠體上,並透過導電結構的端點與接地導電墊電連接。 TW I635595 discloses a chip package, including a circuit board, a package glue, a plurality of conductive structures, and an electromagnetic interference protection layer. The circuit board includes a plurality of ground conductive pads, which are arranged on the lower surface. The packaging glue is arranged on the upper surface of the circuit board. The conductive structure is arranged in the packaging glue and is electrically connected to the ground conductive pad, wherein the end of each conductive structure is exposed from the sidewall of the packaging glue. The electromagnetic interference protection layer is arranged on the packaging gel and is electrically connected to the ground conductive pad through the end of the conductive structure.

TW I623068揭示一種可兼顧基板的彎曲抑制和基板的兩面成型的樹脂封裝裝置。本發明的樹脂封裝裝置為將基板的兩面以壓縮成型進行樹脂封裝的裝置,其中上模以及下模中的一個包含剛性部件以及第一彈性部件,另一個包含與該第一彈性部件相比具有更大彈簧常數的第二彈性部件;上模框架部件以及下模框架部件中的一個在開合該上模以及該下模的方向上的移動通過該剛性部件而停止;基板銷在下模型腔的外側以向上方突出的方式設置,該基板銷將該基板以從該下模上表面脫離的狀態載置,或包含外部氣體阻斷部件以及基板支撐元件,以模具型腔內減壓並支撐基板的未被樹脂封裝的一面的狀態,將另一面通過壓縮成型而進行樹脂 封裝。 TW I623068 discloses a resin packaging device that can balance the suppression of substrate bending and the molding of both sides of the substrate. The resin encapsulation device of the present invention is a device that performs resin encapsulation on both sides of a substrate by compression molding, wherein one of the upper mold and the lower mold includes a rigid member and a first elastic member, and the other includes a The second elastic member with a larger spring constant; the movement of one of the upper mold frame member and the lower mold frame member in the direction of opening and closing the upper mold and the lower mold is stopped by the rigid member; the substrate pin is in the lower mold cavity The outer side is provided so as to protrude upward, and the substrate pin is placed on the substrate in a state detached from the upper surface of the lower mold, or includes an external gas blocking member and a substrate support element, and supports the substrate by reducing the pressure in the mold cavity The state of the side that is not encapsulated by resin, and the other side is compressed and molded to resin Package.

然而,封裝用的高分子材料具有易吸濕的特性,而殘餘溼氣在迴焊製程時會發生爆米花現象,使構裝體損壞;因此,減少氣體殘留於封裝體中將是重要課題。 However, the polymer materials used in packaging have the characteristics of easy moisture absorption, and the residual moisture will popcorn during the reflow process, which will damage the structure; therefore, reducing the residual gas in the package will be an important issue.

有鑑於以上問題,本發明提供一種減少空氣殘留的封裝結構及其方法,主要利用墊片置於基板與晶片模組間,以減少氣體佔用基板與晶片模組間距比例過高的可能。 In view of the above problems, the present invention provides a packaging structure and method for reducing air residues, which mainly use gaskets between the substrate and the chip module to reduce the possibility that the gas occupying the space between the substrate and the chip module is too high.

本發明再一目的係在提供一種減少空氣殘留的封裝結構及其方法,可有效改善晶片模組封裝常因爆米花現象導致之電性連結失效。 Another object of the present invention is to provide a packaging structure and method for reducing air residue, which can effectively improve the electrical connection failure of chip module packaging caused by popcorn phenomenon.

本發明再一目的係在提供一種減少空氣殘留的封裝結構及其方法,提昇晶片模組堆疊良率,可增加封裝內堆疊高度。 Another object of the present invention is to provide a package structure and a method for reducing air residue, improve the stacking yield of chip modules, and increase the stacking height in the package.

為達成上述目地,本發明所使用的主要技術手段是採用以下技術方案來實現的。本發明為一種減少空氣殘留的封裝結構,其應用於晶片模組封裝,其包含:一墊片、一基板、一晶片模組、一絕緣封裝體與複數錫球;其特徵在於,該墊片由一粘膠材料固定於該基板之一主動面,該晶片模組位於該墊片一側,該晶片模組之複數導通球與該主動面之複數導通點相結合,複數錫球植於該基板之一背面之複數預植點,該絕緣封裝體包覆於該晶片模組、該墊片與該主動面。 In order to achieve the above objective, the main technical means used in the present invention are achieved by the following technical solutions. The present invention is a packaging structure for reducing air residue, which is applied to chip module packaging, and includes: a gasket, a substrate, a chip module, an insulating package and a plurality of solder balls; the gasket is characterized in that Fixed on an active surface of the substrate by an adhesive material, the chip module is located on the side of the gasket, the plurality of conductive balls of the chip module are combined with the plurality of conductive points of the active surface, and the plurality of solder balls are implanted on the A plurality of pre-planted points on the back of a substrate, the insulating package covers the chip module, the gasket and the active surface.

再,本發明之另一封裝結構為一種減少空氣殘留的封裝結構,其應用於晶片模組封裝,其包含:一墊片、一基板、一晶片模組、一絕緣封裝體與複數錫球;其特徵在於,該墊片由一粘膠材料固定於該晶片 模組之一導通面,該墊片位於該基板之一主動面一側,該晶片模組之複數導通球與該主動面之複數導通點相結合,複數錫球植於該基板之一背面之複數預植點,該絕緣封裝體包覆於該晶片模組、該墊片與該主動面。 Furthermore, another package structure of the present invention is a package structure for reducing air residue, which is applied to chip module packaging, and includes: a gasket, a substrate, a chip module, an insulating package and a plurality of solder balls; It is characterized in that the gasket is fixed to the chip by an adhesive material A conductive surface of the module, the gasket is located on the side of an active surface of the substrate, a plurality of conductive balls of the chip module and a plurality of conductive points of the active surface are combined, and a plurality of solder balls are implanted on the back of the substrate A plurality of pre-planted points, the insulating package body covers the chip module, the gasket and the active surface.

又,本發明之再一封裝結構為一種減少空氣殘留的封裝結構,其應用於晶片模組封裝,其包含:一基板、一晶片模組、一絕緣封裝體與複數錫球;其特徵在於,將一粘膠材料固定於該基板之一主動面,該晶片模組位於該粘膠材料一側,該晶片模組之複數導通球與該主動面之複數導通點相結合,複數錫球植於該基板之一背面之複數預植點,該絕緣封裝體包覆於該晶片模組與該主動面。 In addition, another package structure of the present invention is a package structure for reducing air residue, which is applied to chip module packaging, and includes: a substrate, a chip module, an insulating package, and a plurality of solder balls; characterized in that, An adhesive material is fixed to an active surface of the substrate, the chip module is located on the side of the adhesive material, the plurality of conductive balls of the chip module are combined with the plurality of conductive points of the active surface, and the plurality of solder balls are planted on A plurality of pre-planted points on the back of a substrate, the insulating package covers the chip module and the active surface.

本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。 The purpose of the present invention and the solution of its technical problems can be further achieved by the following technical measures.

前述的封裝結構,其中該墊片可為導電、不導電或半導體材料。 In the aforementioned packaging structure, the gasket may be conductive, non-conductive or semiconductor material.

前述的封裝結構,其中該粘膠材料可為導電膠材或非導電膠材。 In the aforementioned packaging structure, the adhesive material can be a conductive adhesive or a non-conductive adhesive.

前述的封裝結構,其中該晶片模組係為已封裝之晶片。 In the aforementioned packaging structure, the chip module is a packaged chip.

前述的封裝結構,其中該墊片另一側由一增強粘膠材料固定於該晶片模組之一導通面。 In the aforementioned packaging structure, the other side of the gasket is fixed to a conducting surface of the chip module by a reinforced adhesive material.

前述的封裝結構,其中該墊片另一側由一增強粘膠材料固定於該基板之該主動面。 In the aforementioned packaging structure, the other side of the gasket is fixed to the active surface of the substrate by a reinforced adhesive material.

為達成上述目地,本發明所使用的再依主要技術手段是採用以下技術方案來實現的。本發明為一種減少空氣殘留的封裝方法,其應 用於晶片模組封裝,其包含:步驟1:將一墊片藉由一粘膠材料結合於一基板之一主動面;步驟2:以一晶片模組之複數導通球與該主動面之複數導通點相貼合;步驟3:形成一絕緣封裝體包覆於該晶片模組、該墊片與該基板,所述該絕緣封裝體未包覆所述該基板之一背面。 In order to achieve the above objective, the main technical means used in the present invention are realized by the following technical solutions. The present invention is a packaging method for reducing residual air, which should be For chip module packaging, it includes: Step 1: Bonding a pad to an active surface of a substrate by an adhesive material; Step 2: Using a plurality of conductive balls of a chip module and a plurality of the active surface The conductive points are attached to each other; Step 3: An insulating package is formed to cover the chip module, the gasket and the substrate, and the insulating package does not cover a back surface of the substrate.

再,本發明之另一封裝方法為一種減少空氣殘留的封裝方法,其應用於晶片模組封裝,其包含:步驟1a:將一墊片藉由一粘膠材料結合於一晶片模組之一導通面;步驟2:以該晶片模組之複數導通球與一基板之一主動面之複數導通點相貼合;步驟3:形成一絕緣封裝體包覆於該晶片模組、該墊片與該基板,所述該絕緣封裝體未包覆所述該基板之一背面。 Furthermore, another packaging method of the present invention is a packaging method for reducing air residue, which is applied to chip module packaging, which includes: Step 1a: bonding a gasket to one of the chip modules by an adhesive material Conduction surface; Step 2: Attach a plurality of conductive balls of the chip module to a plurality of conductive points of an active surface of a substrate; Step 3: Form an insulating package covering the chip module, the gasket and The substrate, the insulating package body does not cover a back surface of the substrate.

另,本發明之其一封裝方法為一種減少空氣殘留的封裝方法,其應用於晶片模組封裝,其包含:步驟1c:將一粘膠材料結合於一基板之一主動面;步驟2:以一晶片模組之複數導通球與該主動面之複數導通點相貼合;步驟3a:形成一絕緣封裝體包覆於該晶片模組與該基板,所述該絕緣封裝體未包覆所述該基板之一背面。 In addition, one of the packaging methods of the present invention is a packaging method for reducing air residue, which is applied to chip module packaging, which includes: Step 1c: bonding an adhesive material to an active surface of a substrate; Step 2: A plurality of conductive balls of a chip module are attached to a plurality of conductive points of the active surface; step 3a: forming an insulating package covering the chip module and the substrate, the insulating package not covering the One of the back of the substrate.

本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。 The purpose of the present invention and the solution of its technical problems can be further achieved by the following technical measures.

前述的封裝方法,其中該步驟2之前,該墊片一側塗設一增強粘膠材料。 In the aforementioned packaging method, before step 2, a reinforced adhesive material is applied to one side of the gasket.

前述的封裝方法,承上所述步驟之後,將複數錫球植於該背面上,再由分割加工將已封裝之該晶片模組分離。 In the aforementioned packaging method, after following the steps described above, a plurality of solder balls are planted on the back surface, and then the packaged chip module is separated by a dividing process.

相較於習知技術,本發明具有功效在於:(1)利用墊片減 少氣體干擾;(2)藉由改善電性連結失效以降低封裝成本;(3)憑藉提昇晶片模組堆疊良率,可增加封裝內堆疊高度。 Compared with the conventional technology, the present invention has the following effects: (1) Using gaskets to reduce Less gas interference; (2) Reduce packaging costs by improving electrical connection failure; (3) By improving the stacking yield of chip modules, the stack height in the package can be increased.

10‧‧‧墊片 10‧‧‧Gasket

20‧‧‧基板 20‧‧‧Substrate

21‧‧‧主動面 21‧‧‧Active surface

211‧‧‧導通點 211‧‧‧on point

22‧‧‧背面 22‧‧‧Back

221‧‧‧預植點 221‧‧‧Pre-planting point

30‧‧‧晶片模組 30‧‧‧Chip Module

31‧‧‧複數導通球 31‧‧‧Complex ball

32‧‧‧導通面 32‧‧‧Through surface

40‧‧‧絕緣封裝體 40‧‧‧Insulation package

50‧‧‧錫球 50‧‧‧Tin ball

60‧‧‧粘膠材料 60‧‧‧Viscose material

61‧‧‧增強粘膠材料 61‧‧‧Reinforced viscose material

71‧‧‧步驟1 71‧‧‧Step 1

71a‧‧‧步驟1a 71a‧‧‧Step 1a

71b‧‧‧步驟1b 71b‧‧‧Step 1b

71c‧‧‧步驟1c 71c‧‧‧Step 1c

72‧‧‧步驟2 72‧‧‧Step 2

73‧‧‧步驟3 73‧‧‧Step 3

73a‧‧‧步驟3a 73a‧‧‧Step 3a

74‧‧‧步驟4 74‧‧‧Step 4

X‧‧‧底部空隙 X‧‧‧Bottom gap

第1a圖為本發明第一實施型態之第一示意圖;第1b圖為本發明第一實施型態之第二示意圖;第1c圖為本發明第一實施型態之第三示意圖;第1d圖為本發明第一實施型態之第四示意圖;第1e圖為本發明第一實施型態之第五示意圖;第2a圖為本發明第二實施型態之第一示意圖;第2b圖為本發明第二實施型態之第二示意圖;第2c圖為本發明第二實施型態之第三示意圖;第2d圖為本發明第二實施型態之第四示意圖;第2e圖為本發明第二實施型態之第五示意圖;第3a圖為本發明第三實施型態之第一示意圖;第3b圖為本發明第三實施型態之第二示意圖;第3c圖為本發明第三實施型態之第三示意圖;第3d圖為本發明第三實施型態之第四示意圖;第3e圖為本發明第三實施型態之第五示意圖;第4a圖為本發明最佳實施型態之晶片模組示意圖;第4b圖為本發明最佳實施型態之晶片模組與墊片示意圖;第5a圖為本發明第一實施型態之流程圖; 第5b圖為本發明第二實施型態之流程圖;第5c圖為本發明第三實施型態之流程圖;第5d圖為本發明第四實施型態之流程圖;第6a圖為本發明第四實施型態之第一示意圖;第6b圖為本發明第四實施型態之第二示意圖;第6c圖為本發明第四實施型態之第三示意圖;第6d圖為本發明第四實施型態之第四示意圖;第6e圖為本發明第四實施型態之第五示意圖。 Figure 1a is a first schematic diagram of the first embodiment of the present invention; Figure 1b is a second schematic diagram of the first embodiment of the present invention; Figure 1c is a third schematic diagram of the first embodiment of the present invention; Figure is the fourth schematic diagram of the first embodiment of the present invention; Figure 1e is the fifth schematic diagram of the first embodiment of the present invention; Figure 2a is the first schematic diagram of the second embodiment of the present invention; Figure 2b is The second schematic diagram of the second embodiment of the present invention; Figure 2c is the third schematic diagram of the second embodiment of the present invention; Figure 2d is the fourth schematic diagram of the second embodiment of the present invention; Figure 2e is the present invention The fifth schematic diagram of the second embodiment; Figure 3a is the first schematic diagram of the third embodiment of the present invention; Figure 3b is the second schematic diagram of the third embodiment of the present invention; Figure 3c is the third schematic diagram of the third embodiment of the present invention The third schematic diagram of the embodiment; Figure 3d is the fourth schematic diagram of the third embodiment of the invention; Figure 3e is the fifth schematic diagram of the third embodiment of the invention; Figure 4a is the best embodiment of the invention Fig. 4b is a schematic diagram of the chip module and spacers of the best embodiment of the present invention; Fig. 5a is a flowchart of the first embodiment of the present invention; Figure 5b is a flowchart of the second embodiment of the present invention; Figure 5c is a flowchart of the third embodiment of the present invention; Figure 5d is a flowchart of the fourth embodiment of the present invention; Figure 6a is a flowchart of the fourth embodiment of the present invention The first schematic diagram of the fourth embodiment of the present invention; Figure 6b is the second schematic diagram of the fourth embodiment of the present invention; Figure 6c is the third schematic diagram of the fourth embodiment of the present invention; Figure 6d is the third schematic diagram of the fourth embodiment of the present invention. The fourth schematic diagram of the fourth embodiment; Figure 6e is the fifth schematic diagram of the fourth embodiment of the present invention.

為了讓本發明之目的、特徵與功效更明顯易懂,以下特別列舉本發明之較佳實施型態: In order to make the purpose, features and effects of the present invention more comprehensible, the following specifically enumerates the preferred embodiments of the present invention:

如第1a、1b、1c、1d、1e及5a圖所示,為本發明一種減少空氣殘留的封裝結構及其方法之第一實施型態;請先參考第1e圖所示,具有一墊片(10)、一基板(20)、一晶片模組(30)、一絕緣封裝體(40)、複數錫球(50)與粘膠材料(60)。 As shown in Figures 1a, 1b, 1c, 1d, 1e, and 5a, this is the first embodiment of a package structure and method for reducing air residue in the present invention; please refer to Figure 1e first, which has a gasket (10) A substrate (20), a chip module (30), an insulating package (40), a plurality of solder balls (50) and an adhesive material (60).

具體而言,該墊片(10)可為導電、不導電或半導體材料,其作用為填補基板與晶片模組間,以減少氣體佔用基板與晶片模組間距比例過高的可能;其中,基板(20)通常為一種高密度雙面導通之多層印刷電路板,內部形成有線路(未顯示於圖式),可作為電性傳遞介面;該晶片模組(30)係為已封裝之晶片;又,絕緣封裝體(40)為半導體封裝之封裝用高分子材料,其為內容物提供一定的保護;而,複數錫球(50)為晶片提供與外部電路連接的觸點;該粘膠材料(60)可為導電膠 材或非導電膠材,其功效為固定該墊片(10)於預定位置。 Specifically, the gasket (10) can be conductive, non-conductive or semiconductor material, and its function is to fill the gap between the substrate and the chip module to reduce the possibility of the gas occupying an excessively high ratio of the distance between the substrate and the chip module; wherein, the substrate (20) Usually a high-density double-sided conduction multilayer printed circuit board with circuits (not shown in the drawings) formed inside which can be used as an electrical transmission interface; the chip module (30) is a packaged chip; In addition, the insulating package (40) is a polymer material for semiconductor packaging, which provides a certain degree of protection for the content; and the plural solder balls (50) provide the chip with contacts for connecting with the external circuit; the adhesive material (60) Can be conductive adhesive Material or non-conductive adhesive material, its function is to fix the gasket (10) at a predetermined position.

其中,該基板(20)如第1a圖呈現,其包含一主動面(21)及一背面(22),該主動面(21)具有複數導通點(211)、該背面(22)具有複數預植點(221);其中,該主動面(21)如第1b圖呈現為承載晶片模組(30)之作用;另,該背面(22)為裝設錫球與對外之面;而,該些導通點(211)係為如第1b圖所述與該晶片模組(30)之複數導通球(31)相接合,其作用為將導通球(31)電性導通到預植點(221);再,該些預植點(221)作用如1d圖所示為將電性導通到錫球(50)。 Wherein, the substrate (20) is shown in Figure 1a, which includes an active surface (21) and a back surface (22). The active surface (21) has a plurality of conduction points (211), and the back surface (22) has a plurality of presets. Planting point (221); wherein, the active surface (21) as shown in Figure 1b shows the function of carrying the chip module (30); in addition, the back surface (22) is the surface for mounting the solder balls and the outside; and, the The conduction points (211) are connected with the plurality of conduction balls (31) of the chip module (30) as described in Figure 1b, and their function is to electrically conduct the conduction balls (31) to the pre-planting point (221). ); Furthermore, the pre-planting points (221) function as shown in Figure 1d to electrically conduct to the solder balls (50).

其中,該晶片模組(30)係為已封裝之晶片,可參考第4a圖呈現有複數導通球(31)位於下側,由該些導通球(31)電性導通已封裝之晶片,而該晶片模組(30)內側具有一導通面(32),該導通面(32)承載該些導通球(31)。 Among them, the chip module (30) is a packaged chip. As shown in Figure 4a, a plurality of conductive balls (31) are located on the lower side, and the packaged chip is electrically connected by the conductive balls (31), and The chip module (30) is provided with a conducting surface (32) on the inside, and the conducting surface (32) carries the conducting balls (31).

請再參閱第5a圖所示,其中步驟1(71)為將一墊片(10)藉由一粘膠材料(60)結合於一基板(20)之一主動面(21);該步驟1(71)可參考第1a圖。 Please refer to Figure 5a again, in which step 1 (71) is to bond a gasket (10) to an active surface (21) of a substrate (20) by an adhesive material (60); this step 1 (71) Refer to Figure 1a.

跟著,再參閱第5a圖所示,其中步驟2(72)為以一晶片模組(30)之複數導通球(31)與該主動面(21)之複數導通點(211)相貼合;該步驟2(72)可參考第1b圖。 Then, refer to Figure 5a again, where step 2 (72) is to attach the plurality of conductive balls (31) of a chip module (30) to the plurality of conductive points (211) of the active surface (21); Refer to Figure 1b for this step 2 (72).

最後,參閱第5a圖所示,其中步驟3(73)為形成一絕緣封裝體(40)包覆於該晶片模組(30)、該墊片(10)與該基板(20),所述該絕緣封裝體(40)未包覆所述該基板(20)之一背面(22);該步驟3(73)可參考第1c圖。 Finally, referring to Figure 5a, where step 3 (73) is to form an insulating package (40) covering the chip module (30), the gasket (10) and the substrate (20), the The insulating package (40) does not cover a back surface (22) of the substrate (20); the step 3 (73) can refer to Figure 1c.

可接續,參閱第5a圖所示,其中步驟4(74)為將複數錫球(50)植於該背面(22)上,再由分割加工將已封裝之該晶片模組(30)分離;該步驟4(74)可先參考第1d圖,再參考第1e圖。 It can be continued, as shown in Figure 5a, in which step 4 (74) is to plant a plurality of solder balls (50) on the back surface (22), and then separate the packaged chip module (30) by a dividing process; This step 4 (74) can first refer to Figure 1d, and then refer to Figure 1e.

請再參照第2a、2b、2c、2d、2e及5b圖所示,為本發明一種減少空氣殘留的封裝結構及其方法之第二實施型態;第二實施型態與第一實施型態的主要差異在於墊片(10)固定位置不同。 Please refer to Figures 2a, 2b, 2c, 2d, 2e, and 5b, which are the second embodiment of a package structure and method for reducing air residue according to the present invention; the second embodiment and the first embodiment The main difference lies in the fixed position of the gasket (10).

請先參考第2e圖所示,具有一墊片(10)、一基板(20)、一晶片模組(30)、一絕緣封裝體(40)、複數錫球(50)與粘膠材料(60);以上與第一實施型態介紹相同。 Please refer to Figure 2e, which has a gasket (10), a substrate (20), a chip module (30), an insulating package (40), a plurality of solder balls (50) and adhesive materials ( 60); The above is the same as the introduction of the first implementation type.

請再參閱第5b圖所示,其中步驟1a(71a)為將一墊片(10)藉由一粘膠材料(60)結合於一晶片模組(30)之一導通面(32);該步驟1a(71a)可參考第2a圖,可見第4a與4b所示,將墊片(10)貼附在晶片模組(30)之底部空隙(X)上。 Please refer to Figure 5b again, in which step 1a (71a) is to bond a gasket (10) to a conducting surface (32) of a chip module (30) through an adhesive material (60); Step 1a (71a) can refer to Figure 2a. As shown in Figures 4a and 4b, the spacer (10) is attached to the bottom gap (X) of the chip module (30).

跟著,再參閱第5b圖所示,其中步驟2(72)為以一晶片模組(30)之複數導通球(31)與該主動面(21)之複數導通點(211)相貼合;該步驟2(72)可參考第2b圖。 Then, refer to Fig. 5b again, where step 2 (72) is to attach the plurality of conductive balls (31) of a chip module (30) to the plurality of conductive points (211) of the active surface (21); Refer to Figure 2b for this step 2 (72).

最後,參閱第5b圖所示,其中步驟3(73)為形成一絕緣封裝體(40)包覆於該晶片模組(30)、該墊片(10)與該基板(20),所述該絕緣封裝體(40)未包覆所述該基板(20)之一背面(22);該步驟3(73)可參考第2c圖。 Finally, referring to Figure 5b, where step 3 (73) is to form an insulating package (40) covering the chip module (30), the spacer (10) and the substrate (20), the The insulating package (40) does not cover a back surface (22) of the substrate (20); this step 3 (73) can refer to Figure 2c.

可接續,參閱第5b圖所示,其中步驟4(74)為將複數錫球(50)植於該背面(22)上,再由分割加工將已封裝之該晶片模組(30) 分離;該步驟4(74)可先參考第2d圖,再參考第2e圖。 It can be continued, please refer to Figure 5b, where step 4 (74) is to plant a plurality of solder balls (50) on the back surface (22), and then divide the packaged chip module (30) Separation; this step 4 (74) can first refer to Figure 2d, and then refer to Figure 2e.

請再參照第3a、3b、3c、3d、3e及5c圖所示,為本發明一種減少空氣殘留的封裝結構及其方法之第三實施型態;第三實施型態與第一實施型態的主要差異在於增加墊片(10)一側塗設一增強粘膠材料(61)。 Please refer to Figures 3a, 3b, 3c, 3d, 3e, and 5c, which are the third embodiment of a package structure and method for reducing air residue according to the present invention; the third embodiment and the first embodiment The main difference lies in adding a reinforced adhesive material (61) on one side of the gasket (10).

請先參考第3e圖所示,具有一墊片(10)、一基板(20)、一晶片模組(30)、一絕緣封裝體(40)、複數錫球(50)與粘膠材料(60);以上與第一實施型態介紹相同,另含一增強粘膠材料(61),其可為導電膠材或非導電膠材,其功效為固定該墊片(10)於預定位置。 Please refer to Figure 3e, which has a gasket (10), a substrate (20), a chip module (30), an insulating package (40), a plurality of solder balls (50) and adhesive materials ( 60); The above description is the same as the first embodiment, and it also contains a reinforced adhesive material (61), which can be a conductive adhesive or a non-conductive adhesive, and its function is to fix the gasket (10) in a predetermined position.

請再參閱第5c圖所示,其中步驟1(71)為將一墊片(10)藉由一粘膠材料(60)結合於一基板(20)之一主動面(21);該步驟1(71)可參考第3a圖。 Please refer to Figure 5c again, where step 1 (71) is to bond a gasket (10) to an active surface (21) of a substrate (20) by an adhesive material (60); this step 1 (71) Refer to Figure 3a.

再,參閱第5c圖所示,其中步驟1b(71b)為該墊片(10)一側塗設一增強粘膠材料(61);該步驟1b(71b)可參考第3a圖。 Again, refer to Figure 5c, where step 1b (71b) is to coat one side of the gasket (10) with a reinforced adhesive material (61); this step 1b (71b) can refer to Figure 3a.

跟著,再參閱第5c圖所示,其中步驟2(72)為以一晶片模組(30)之複數導通球(31)與該主動面(21)之複數導通點(211)相貼合;該步驟2(72)可參考第3b圖。 Then, refer to Figure 5c again, where step 2 (72) is to attach the plurality of conductive balls (31) of a chip module (30) to the plurality of conductive points (211) of the active surface (21); Refer to Figure 3b for this step 2 (72).

最後,參閱第5c圖所示,其中步驟3(73)為形成一絕緣封裝體(40)包覆於該晶片模組(30)、該墊片(10)與該基板(20),所述該絕緣封裝體(40)未包覆所述該基板(20)之一背面(22);該步驟3(73)可參考第3c圖。 Finally, referring to Figure 5c, where step 3 (73) is to form an insulating package (40) covering the chip module (30), the gasket (10) and the substrate (20), the The insulating package (40) does not cover a back surface (22) of the substrate (20); this step 3 (73) can refer to FIG. 3c.

可接續,參閱第5c圖所示,其中步驟4(74)為將複數錫球 (50)植於該背面(22)上,再由分割加工將已封裝之該晶片模組(30)分離;該步驟4(74)可先參考第3d圖,再參考第3e圖。 Can be continued, refer to Figure 5c, where step 4 (74) is to put the plural solder balls (50) Plant on the back surface (22), and then separate the packaged chip module (30) by a dicing process; for step 4 (74), please refer to Figure 3d first, and then Figure 3e.

請再參照第6a、6b、6c、6d、6e及5d圖所示,為本發明一種減少空氣殘留的封裝結構及其方法之第四實施型態;第四實施型態與第一實施型態的主要差異在於移除墊片(10)。 Please refer to Figures 6a, 6b, 6c, 6d, 6e, and 5d, which are the fourth embodiment of a package structure and method for reducing air residue according to the present invention; the fourth embodiment and the first embodiment The main difference is the removal of the gasket (10).

請先參考第6e圖所示,具有一基板(20)、一晶片模組(30)、一絕緣封裝體(40)、複數錫球(50)與粘膠材料(60);以上與第一實施型態介紹相同,另移除墊片(10),其由粘膠材料(60)完全取代該墊片(10)功效。 Please refer to Figure 6e, which has a substrate (20), a chip module (30), an insulating package (40), a plurality of solder balls (50) and adhesive materials (60); the above is the same as the first The description of the implementation type is the same, except that the gasket (10) is removed, and the adhesive material (60) completely replaces the effect of the gasket (10).

請再參閱第5d圖所示,其中步驟1c(71c)為將一粘膠材料(60)結合於一基板(20)之一主動面(21);該步驟1c(71c)可參考第6a圖。 Please refer to Figure 5d again, where step 1c (71c) is to bond an adhesive material (60) to an active surface (21) of a substrate (20); this step 1c (71c) can refer to Figure 6a .

跟著,再參閱第5d圖所示,其中步驟2(72)為以一晶片模組(30)之複數導通球(31)與該主動面(21)之複數導通點(211)相貼合;該步驟2(72)可參考第6b圖。 Then, refer to Fig. 5d again, in which step 2 (72) is to attach the plural conductive balls (31) of a chip module (30) to the plural conductive points (211) of the active surface (21); Refer to Figure 6b for this step 2 (72).

最後,參閱第5d圖所示,其中步驟3a(73a)為形成一絕緣封裝體(40)包覆於該晶片模組(30)與該基板(20),所述該絕緣封裝體(40)未包覆所述該基板(20)之一背面(22);該步驟3a(73a)可參考第6c圖。 Finally, referring to Figure 5d, where step 3a (73a) is to form an insulating package (40) covering the chip module (30) and the substrate (20), the insulating package (40) One of the back sides (22) of the substrate (20) is not covered; this step 3a (73a) can refer to Figure 6c.

可接續,參閱第5d圖所示,其中步驟4(74)為將複數錫球(50)植於該背面(22)上,再由分割加工將已封裝之該晶片模組(30)分離;該步驟4(74)可先參考第6d圖,再參考第6e圖。 It can be continued, as shown in Fig. 5d, in which step 4 (74) is to plant a plurality of solder balls (50) on the back surface (22), and then separate the packaged chip module (30) by a dividing process; This step 4 (74) can first refer to Figure 6d and then Figure 6e.

因此本發明之功效有別一般半導體封裝結構,此於半導體封裝當中實屬首創,符合發明專利要件,爰依法俱文提出申請。 Therefore, the effect of the present invention is different from the general semiconductor packaging structure. It is the first in semiconductor packaging and meets the requirements of an invention patent. The application is filed in accordance with the law.

惟,需再次重申,以上所述者僅為本發明之較佳實施型態,舉凡應用本發明說明書、申請專利範圍或圖式所為之等效變化,仍屬本發明所保護之技術範疇,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 However, it needs to be reiterated that the above are only the preferred implementation forms of the present invention. Any equivalent changes made by applying the specification, scope of patent application, or drawings of the present invention still belong to the technical scope protected by the present invention. Therefore, The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10‧‧‧墊片 10‧‧‧Gasket

20‧‧‧基板 20‧‧‧Substrate

30‧‧‧晶片模組 30‧‧‧Chip Module

40‧‧‧絕緣封裝體 40‧‧‧Insulation package

50‧‧‧錫球 50‧‧‧Tin ball

60‧‧‧粘膠材料 60‧‧‧Viscose material

Claims (13)

一種減少空氣殘留的封裝結構,其應用於晶片模組封裝,其包含:一墊片、一基板、一晶片模組、一絕緣封裝體與複數錫球;其特徵在於,該墊片由一粘膠材料固定於該基板之一主動面,該晶片模組位於該墊片一側,該晶片模組之複數導通球與該主動面之複數導通點相結合,複數錫球植於該基板之一背面之複數預植點,該絕緣封裝體包覆於該晶片模組、該墊片與該主動面。 A packaging structure for reducing air residue, which is applied to chip module packaging, which comprises: a gasket, a substrate, a chip module, an insulating package and a plurality of solder balls; characterized in that the gasket is made of an adhesive The glue material is fixed on an active surface of the substrate, the chip module is located on the side of the gasket, the plurality of conductive balls of the chip module are combined with the plurality of conductive points of the active surface, and the plurality of solder balls are implanted on one of the substrates For a plurality of pre-planted points on the back, the insulating package covers the chip module, the gasket and the active surface. 一種減少空氣殘留的封裝結構,其應用於晶片模組封裝,其包含:一墊片、一基板、一晶片模組、一絕緣封裝體與複數錫球;其特徵在於,該墊片由一粘膠材料固定於該晶片模組之一導通面,該墊片位於該基板之一主動面一側,該晶片模組之複數導通球與該主動面之複數導通點相結合,複數錫球植於該基板之一背面之複數預植點,該絕緣封裝體包覆於該晶片模組、該墊片與該主動面。 A packaging structure for reducing air residue, which is applied to chip module packaging, which comprises: a gasket, a substrate, a chip module, an insulating package and a plurality of solder balls; characterized in that the gasket is made of an adhesive The glue material is fixed on a conductive surface of the chip module, the gasket is located on the side of an active surface of the substrate, the plurality of conductive balls of the chip module are combined with the plurality of conductive points of the active surface, and the plurality of solder balls are planted on A plurality of pre-planted points on the back of the substrate, the insulating package covers the chip module, the gasket and the active surface. 一種減少空氣殘留的封裝結構,其應用於晶片模組封裝,其包含:一基板、一晶片模組、一絕緣封裝體與複數錫球;其特徵在於,將一粘膠材料固定於該基板之一主動面,該晶片模組位於該粘膠材料一側,該晶片模組之複數導通球與該主動面之複數導通點相結合,複數錫球植於該基板之一背面之複數預植點,該絕緣封裝體包覆於該晶片模組與該主動面。 A packaging structure for reducing air residue, which is applied to chip module packaging, comprising: a substrate, a chip module, an insulating package, and a plurality of solder balls; and it is characterized in that an adhesive material is fixed on the substrate An active surface, the chip module is located on the side of the adhesive material, the plurality of conductive balls of the chip module are combined with the plurality of conductive points of the active surface, and the plurality of solder balls are implanted on the plurality of pre-planted points on the back of the substrate , The insulating package covers the chip module and the active surface. 如申請專利範圍第1或2項所述的封裝結構,其中該墊片可為導電、不導電或半導體材料。 According to the package structure described in item 1 or 2 of the scope of patent application, the gasket can be conductive, non-conductive or semiconductor material. 如申請專利範圍第1、2或3項所述的封裝結構,其中該粘膠材料可為導 電膠材或非導電膠材。 Such as the package structure described in item 1, 2 or 3 of the scope of patent application, wherein the adhesive material can be conductive Electric plastic or non-conductive plastic. 如申請專利範圍第1、2或3項所述的封裝結構,其中該晶片模組係為已封裝之晶片。 For the package structure described in item 1, 2 or 3 of the scope of patent application, the chip module is a packaged chip. 如申請專利範圍第1項所述的封裝結構,其中該墊片另一側由一增強粘膠材料固定於該晶片模組之一導通面。 According to the package structure described in claim 1, wherein the other side of the gasket is fixed to a conducting surface of the chip module by a reinforced adhesive material. 如申請專利範圍第2項所述的封裝結構,其中該墊片另一側由一增強粘膠材料固定於該基板之該主動面。 According to the package structure described in item 2 of the scope of patent application, the other side of the gasket is fixed to the active surface of the substrate by a reinforced adhesive material. 一種減少空氣殘留的封裝方法,其應用於晶片模組封裝,其包含:步驟1:將一墊片藉由一粘膠材料結合於一基板之一主動面;步驟2:以一晶片模組之複數導通球與該主動面之複數導通點相貼合;步驟3:形成一絕緣封裝體包覆於該晶片模組、該墊片與該基板,所述該絕緣封裝體未包覆所述該基板之一背面。 A packaging method for reducing air residue, which is applied to chip module packaging, includes: step 1: bonding a gasket to an active surface of a substrate by an adhesive material; step 2: using a chip module The plurality of conductive balls are attached to the plurality of conductive points of the active surface; Step 3: An insulating package is formed to cover the chip module, the gasket and the substrate, and the insulating package does not cover the The back of one of the substrates. 一種減少空氣殘留的封裝方法,其應用於晶片模組封裝,其包含:步驟1a:將一墊片藉由一粘膠材料結合於一晶片模組之一導通面;步驟2:以該晶片模組之複數導通球與一基板之一主動面之複數導通點相貼合;步驟3:形成一絕緣封裝體包覆於該晶片模組、該墊片與該基板,所述該絕緣封裝體未包覆所述該基板之一背面。 A packaging method for reducing air residue, which is applied to chip module packaging, includes: Step 1a: bonding a gasket to a conductive surface of a chip module by an adhesive material; Step 2: using the chip mold The plurality of conductive balls of the set are attached to the plurality of conductive points of an active surface of a substrate; Step 3: An insulating package is formed to cover the chip module, the gasket and the substrate, and the insulating package is not Covering the back of the substrate. 一種減少空氣殘留的封裝方法,其應用於晶片模組封裝,其包含:步驟1c:將一粘膠材料結合於一基板之一主動面;步驟2:以一晶片模組之複數導通球與該主動面之複數導通點相貼 合;步驟3a:形成一絕緣封裝體包覆於該晶片模組與該基板,所述該絕緣封裝體未包覆所述該基板之一背面。 A packaging method for reducing air residue, which is applied to chip module packaging, comprises: Step 1c: bonding an adhesive material to an active surface of a substrate; Step 2: Using a plurality of conductive balls of a chip module to connect the The complex conduction points of the active surface are close to each other 合; Step 3a: forming an insulating package covering the chip module and the substrate, and the insulating package does not cover a back surface of the substrate. 如申請專利範圍第9或10項所述的封裝方法,其中該步驟2之前,該墊片一側塗設一增強粘膠材料。 For the packaging method described in item 9 or 10 of the scope of patent application, before step 2, a reinforced adhesive material is coated on one side of the gasket. 如申請專利範圍第9、10或11項所述的封裝方法,承上所述步驟之後,將複數錫球植於該背面上,再由分割加工將已封裝之該晶片模組分離。 For the packaging method described in item 9, 10 or 11 of the scope of patent application, after the above steps, a plurality of solder balls are planted on the back surface, and then the packaged chip module is separated by a dividing process.
TW108100190A 2019-01-03 2019-01-03 Packaging structure for reducing residual air and method thereof capable of effectively preventing the chip module package from electrical connection failure TW202027236A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113725140A (en) * 2021-08-30 2021-11-30 盛合晶微半导体(江阴)有限公司 Packaging carrier, preparation method thereof and packaging method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113725140A (en) * 2021-08-30 2021-11-30 盛合晶微半导体(江阴)有限公司 Packaging carrier, preparation method thereof and packaging method

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