TW201933585A - Forming method of three dimensional integrated circuit - Google Patents

Abstract

Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure. A stacked device is formed by bonding a die to a first substrate, the die having a smaller width than a width of the first substrate, depositing a planarization material over the die, planarizing the planarization material to form a planarized upper surface, and stacking a third substrate on the planarized upper surface.

Description

Forming method of three-dimensional integrated circuit

This disclosure relates generally to the manufacture of integrated circuit devices. More specifically, the present disclosure provides a method and resulting device for stacking and interconnecting three-dimensional devices using heterogeneous and non-uniform layers, such as fully fabricated integrated circuits. By way of example, the integrated circuit may include, in particular, a memory device, a processor device, a digital signal processing device, a special application device, a controller device, a communication device, and others.

Mechanical back grinding processes are commonly used to thin semiconductor substrates in conventional wafer stacks. Back grinding imparts a high level of mechanical stress to these devices and can result in large thickness variations. Therefore, other processes for separating substrates are desirable.

One method of thinning a substrate is described in US Patent No. 6,316,333 (hereinafter, "Bruel"). Bruel describes implanting ions through a gate structure to form a split plane in a substrate, and removing a portion of the substrate by splitting along the split plane. Bruel acknowledges that ion implantation causes damage to the device structure (eg, the channel area), which can render the device inoperable. Bruel describes building structures on the exposed surface of the substrate to selectively block ion implantation, thereby reducing damage to structures placed directly under the blocking structure.

However, there are several restrictions on Bruel's proposal. The structure described by Bruel is relatively large, for example, a gate length of 0.5 microns. Current devices use much smaller structures, for example, A gate length of 30 nm or less is more than an order of magnitude smaller than the gate length described by Bruel. In order to accumulate enough hydrogen ions to perform a split operation, ions must be implanted through most of the surface of the device. In addition, modern devices are becoming increasingly complex and include higher amounts of sensitive structures. Some of these structures (such as vertical transistors) have vertical components that are longer than horizontal components, which brings a greater chance of damage from a vertically oriented ion passing through the structure.

In addition, larger structures are generally more robust to ionic damage than smaller structures. Smaller structures will have fewer atoms and will be more sensitive to breakage of atoms within the structure. For example, a barrier layer having a characteristic size of 10 nm may have a thickness of one dozens of atoms, so that the breakdown of a single atom may have a significant effect on the barrier properties.

Embodiments of the present disclosure relate to semiconductor devices including ion splitting technology. Embodiments can be used to form a three-dimensional integrated circuit (3DIC) by implanting ions through a circuit layer to form a split plane, repairing damage caused by the implantation, and stacking semiconductor substrates. These substrates can be processed on a wafer scale.

In an embodiment, the process of forming a 3DIC includes providing a first substrate having a circuit layer including a plurality of dielectric and conductive structures, implanting ions through the circuit layer and implanting the first substrate into the first substrate. A substrate to form a split plane, and after the plasma is implanted through the circuit layer, the semiconductor substrate is exposed to a hydrogen mixture at a first temperature for a first time to repair the implanted ions damage. A first portion of the first substrate on which the plurality of dielectric and conductive structures are disposed is separated from a second portion of the first substrate by splitting at the split plane, and the first portion of the substrate is bonded to A second substrate. At least a portion of the conductive structures of the first substrate may then be connected to the conductive structures of the second substrate. The first temperature may be from 300C to 500C, and the time may be at least half an hour. The conductive and dielectric structures may include high-K dielectric structures that include at least one material with a K value of 10 or greater.

The first substrate and the second substrate may be wafer-scale substrates, and the first substrate may not be exposed to higher than (for example) 300C, 400C, 450C or 500C.

In one embodiment, the hydrogen mixture has at least 1% hydrogen, and the remainder of the gas mixture is one or more inert gases. For example, the gas mixture may be a synthetic gas.

Ions can be implanted at a temperature below 100C and a proton energy sufficient to place most recoil damage and split planes deeper than the depletion layer thickness of the operating transistor.

In one embodiment, a procedure for repairing damage caused by implanting ions into a semiconductor substrate via a circuit layer including a conductive and dielectric structure is performed by using the conductive and After the dielectric structure is implanted with ions, the semiconductor substrate is exposed to a hydrogen mixture at a first temperature for a first time. The conductive and dielectric structures may include high-K dielectric structures, including hafnium oxide (HfO ₂ ), hafnium oxide (HfSiO ₂ ), hafnium silicate (HfSiO ₄ ), tantalum oxide (TaO ₅ ), tungsten oxide (WO ₃ ), cerium oxide (CeO ₂ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), strontium titanate (SrTiO ₃ ), lanthanum aluminate (LaAlO ₃ ), niobium pentoxide (NiO ₅ ), at least one of zirconium silicate (ZrSiO ₄ ) and zirconia (ZrO ₂ ).

The hydrogen mixture may have at least 1% hydrogen, and the remainder of one or more inert gases, such as a synthesis gas. The exposure time may be at least 30 minutes, and the first temperature may be, for example, from 300C to 500C or from 350C to 450C. In one embodiment, the first time is from half an hour to five hours, and the first temperature is from 350C to 450C.

In an embodiment, the dielectric structure may include at least one dielectric material having a K value of 20 or greater, the first temperature is from 300C to 500C, the hydrogen mixture includes at least 1% hydrogen, and the temperature is at least 30 Minutes, and the plasma is implanted to form under the circuit layer A split plane.

A method of forming a device includes: providing a first substrate; depositing a thickness range compensation material on a first surface of the first substrate; implanting ions into the first substrate, and the ions travel through the range Compensating the material to define a split profile in the first substrate, the split profile including at least one profile of the absorbent material corresponding to the thickness; removing the absorbent material; and splitting the first substrate at the split profile, This exposes the at least one contour. In one embodiment, the at least one contour is a coolant channel. The range compensation material may be a photoresist material.

A method of forming a device may include coating the exposed surface of the coolant channel with a coating after splitting the first substrate. The coating material may be a material that prevents a chemical reaction between a coolant fluid and the first substrate material. For example, the coating material may be a nitride material or an oxide material. The thermal conductivity of the coating material may be higher than that of a bulk material of the first substrate. In some embodiments, the first substrate has a thermal conductivity greater than 130 W / m-K at a temperature of 25 degrees Celsius. The first substrate may include carbon, for example, in embodiments where the first substrate is a diamond or graphite material.

After splitting, the split surface of the first substrate may be bonded to a second substrate having a circuit layer. In this embodiment, the bonding may be formed by an oxide layer deposited on a surface of the second substrate. When the range compensation layer is removed, a bonding layer may be deposited on the first surface of the first substrate and used to bond a third substrate including a circuit layer to the first substrate on the first substrate. The bonding layer on the surface. The first substrate, the second substrate, and the third substrate may be wafer-scale substrates.

In some embodiments, the hydrogen ions are implanted via one or more circuit layers including a high-K dielectric and a conductive element. In these embodiments, ion implantation can damage dielectric and conductive elements. By exposing the substrate to a temperature ranging from 350 ° C to 500 ° C The atmosphere of hydrogen and inert gas is at least 30 minutes to repair the damage to the dielectric structure.

In one embodiment, a method for forming a stacked semiconductor device includes: implanting ions through a dielectric and conductive structure of a first substrate to define a split plane in the first substrate; and in the split plane Splitting the first substrate to obtain a split layer including one of the dielectric and conductive structures; bonding at least one die to the first substrate, the at least one die having a smaller width than one of the first substrates A width; depositing a planarizing material on the at least one die; planarizing the planarizing material to form a planarized upper surface on the at least one die; and stacking a third on the planarized upper surface Substrate.

Plasma can be implanted at temperatures at or below 100 ° C. In one embodiment, the plasma is implanted at room temperature.

In some embodiments, the total thickness change (TTV) of the material split from the substrate is 4% or less, 2% or less than 2% or 1% or less than 1%. The first substrate, the second substrate, and the third substrate may be wafer-scale substrates. In addition, after the first substrate is split, the first substrate may be annealed to repair damage to the dielectric and conductive structures caused by the plasma.

In one embodiment, an annealing process for repairing the damage of the dielectric and conductive structures is performed in an environment including hydrogen at a temperature of 350 degrees Celsius or more. Conditions in a repair procedure should be sufficient to allow hydrogen to penetrate the surface of the device and bind to molecules damaged by an implantation process. In a specific embodiment, the repair annealing is performed in an atmosphere including from 2% to 5% hydrogen (the remaining is one or more inert gases) at a temperature of 400 degrees Celsius. In one embodiment, the repair annealing is performed to allow passivation of hydrogen despite passivation of the circuit structure in the device (which may include an interconnect network of metal and one of the low-k dielectric materials) and occupying the damaged dielectric junction. One time period of loci. In one embodiment, the annealing is performed at a temperature of 400 degrees Celsius for one hour.

An embodiment may include depositing a dielectric material on the at least one die after bonding the at least one die to the first substrate and before bonding the at least one die to the third substrate.

Before implanting the plasma, a range compensation layer may be formed on the first substrate.

After the first substrate is split, the first substrate may be bonded to a second substrate. In one embodiment, the second substrate has a second dielectric and conductive structure, and the second substrate is formed by implanting ions through the second dielectric and conductive structure. The first substrate, the second substrate, and the third substrate may be wafers.

The small die may be one of several types of devices, including amplifiers, RF tuners, radio tuners, light emitting diodes, and optical sensors.

The plurality of conductive structures may be a plurality of transistors having respective plurality of conductive gates separated from respective channel regions by a gate dielectric.

In one embodiment, a method for forming a three-dimensional integrated circuit includes: providing a first semiconductor substrate having a first circuit layer including a conductive metal and a dielectric material; and via the first circuit Layer of the plurality of conductive metals and dielectric materials implanted with ions to establish a first split plane in the first substrate; split the first substrate at the first split plane; provide a second semiconductor substrate, the The second semiconductor substrate has a second circuit layer including one of a conductive metal and a dielectric material; implanting ions through the conductive metal and the dielectric material of the second circuit layer to establish a second in the second substrate A splitting plane; splitting the second substrate at the second splitting plane; bonding the first substrate to the second substrate; stacking at least one die on the second substrate, the die having less than the first plurality Depositing a planarizing material on the at least one die; planarizing the planarizing material to form a planarized upper surface on the at least one die; On the planarized upper surface of a third substrate stacked.

In one embodiment, a method for forming a semiconductor device includes: forming an ion range compensation layer on a surface of a first substrate; and passing the ion range compensation layer of the first substrate and a dielectric and conductive structure. Ion implantation to define a split plane in the first substrate; split the first substrate at the split plane to obtain a split layer including one of the dielectric and conductive structures; and bond at least one grain to the first A substrate, the at least one die having a width smaller than a width of the first substrate; a planarizing material is deposited on the at least one die; and the planarizing material is planarized to form a warp on the at least one die. Planarizing the upper surface; and stacking a third substrate on the planarized upper surface.

According to the present disclosure, techniques related generally to the manufacture of integrated circuit devices are provided. More specifically, the present disclosure provides a method and resulting device for stacking and interconnecting three-dimensional (3-D) devices using heterogeneous and non-uniform layers, such as fully fabricated integrated circuits. By way of example, the integrated circuit may include, in particular, a memory device, a processor device, a special application device, a controller device, a communication device, and others.

A method includes providing a first substrate having a dielectric structure and a conductive structure. Ions are implanted into the first substrate, and the ions travel through the dielectric structures and the conductive structures to define a split plane in the first substrate. The first substrate is split at the split plane to obtain a split layer having the dielectric structure and the conductive structure. The split layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, and the split layer is one of the stacked IC layers.

Provides three-dimensional stacking and interconnection of heterogeneous and non-uniform layers, such as fully fabricated integrated circuits. Includes technologies for significantly reducing inter-layer separation and increasing available inter-layer connection density (resulting in increased signal bandwidth and system functionality) compared to existing wafer stacking methods using interposers and TSVs. This technology expands the use of high-energy proton implantation for segmentation and layer transfer developed for homogeneous materials, such as the manufacture of silicon-on-insulator (SOI) wafers, which are suitable for Layer transfer of heterogeneous layers and modification of considerations for damage effects in the device structure.

In one example, the present disclosure provides techniques including a method for manufacturing an integrated circuit. The method includes: providing a semiconductor substrate including a surface region, a plurality of transistor devices formed overlying the surface region, a layer-to-layer interconnection including a structured metal layer and a structured dielectric layer. The connection region and one of the dielectric devices overlying the plurality of transistor devices are interlayer connected, and the interconnection region is overlying a dielectric material to provide a bonding interface, but there may be variations. The method includes forming an unpatterned photoresist material overlying one of the bonding interfaces provided by the dielectric material. In one example, the unpatterned photoresist material is configured to shield one or more of the plurality of transistors from electromagnetic radiation in a wavelength range below 400 nm, and selectively adjust a subsequent One depth of the implantation process. The method subjects the unpatterned photoresist material to the implantation process to introduce a plurality of hydrogen particles through the unpatterned photoresist material to a portion of a split region underlying the surface region of the semiconductor substrate. Select a depth to define a transfer device between the split region and a surface of the dielectric material to form a plurality of interconnected conductive metal layers and insulation having a total metal thickness of 3 to 5 microns or less Dielectric is one of multiple layers and one thickness. The method removes the unpatterned photoresist material after the hydrogen implantation step. The method bonds the surface of the dielectric material overlying the transfer device to a transfer substrate to temporarily bond the semiconductor substrate to the transfer substrate.

In one example, the method enables sufficient energy to a portion of the split region to remove an upper portion of the semiconductor substrate from a lower bulk substrate material, while using the transfer substrate to hold the upper portion of the semiconductor substrate such that the upper portion Contains a hydrogen damaged area. The energy can be provided spatially or globally as described in US Patent No. 6,013,563 (the '563 patent), which is incorporated herein by reference in its entirety. In one example, the method subjects the hydrogen-damaged area overlying the transfer device to a smoothing process to remove part or all of the hydrogen-damaged area and form a backside surface. In one example, the method forms a dielectric material overlying the backside surface One thickness.

In one example, the backside surface is configured with one or more layouts for forming a bottom landing pad in the structured metal layer connected to the transfer device and for accessing one of the adjacent device layers. An interlayer conductive path of a landing pad combined with a conductive path.

In one example, the method further includes depositing a dielectric layer to form a suitable bonding interface on the structured metal layer, the structured metal layer including a densely patterned metal interconnect multilayer 5 to 10 micron thick conductive layer for providing a device power signal, a ground signal, and a frequency synchronization signal, and the dielectric layer has a plurality of conductive paths through the dielectric layer for communication with an upper transfer device Interlayer conductor bonding in layers.

In one example, the method further includes alignment of the transfer device layer and the semiconductor substrate to permanently bond the interlayer conduction path. In one example, the method further includes removing the temporarily bonded semiconductor substrate from the transfer device. In an example, the method further includes forming an internal flow path to allow a coolant to pass through it to cool the transfer device. The interlayer coolant channels may be formed by using a patterned photoresist layer added on the unpatterned photoresist layer. The thickness and / or position of the patterned photoresist layer can be selected to adjust the local penetration depth of the proton beam to form a non-planar split surface in the substrate on the top surface of the coolant channel, where the bottom surface is bounded by the lower plane provide.

In one example, the plurality of transistor devices are selected from a CMOS device, a bipolar transistor, a logic device, a memory device, a digital signal processing device, an analog device, a light absorption and imaging device, a photovoltaic battery, or a micro-electromechanical structure. (MEMS) or any combination thereof.

In one example, the implantation process has a proton energy range from 500 kV to 2 MeV. In one example, the split region is located 1 to 10 microns from the top surface of the dielectric material. In an example, an unpatterned pattern having a high absorptivity of electromagnetic radiation having a wavelength of less than 400 nm is selected. Chemical photoresist material. In one example, the semiconductor substrate includes a silicon or other suitable material for forming an electrical, optical or electromechanical device.

In one example, the implantation process is provided at a dose ranging from 5E16 to 5E17 particles / cm 2. In one example, a beam line implanter is used to provide the implantation process. In one example, the implantation process is provided by a linear accelerator (LINAC) or other variations.

In one example, the split region has a peak concentration at the edge of the implantation range. In one example, the split region contains a plurality of hydrogen-filled microplates. In one example, the split region is characterized by a stress sufficient to induce propagation of a substantially flat split region. In one example, the split region is configured as a uniform implanted region or a patterned implanted region. In one example, the split region is patterned or graded to facilitate a controlled splitting action.

In one example, the method includes forming a plurality of interconnect structures between a backside surface and a plurality of transistors or interconnect regions. In an example, the method further includes: providing a second semiconductor substrate including a plurality of second transistor devices and an overlying second dielectric material; and combining the second semiconductor substrate configured with the second semiconductor substrate A dielectric material to form a stacked semiconductor structure. In one example, the method further includes forming a patterned photoresist material overlying the unpatterned photoresist material.

In one example, the plurality of transistor devices and the interconnection region are characterized by a thickness of three microns and less; wherein the implantation process is characterized by a range of five microns to ten microns, so that the plurality of transistor devices are And one characteristic size of the interconnection area does not affect the implantation process. In an example, the plurality of transistor devices and the interconnection region are characterized by a thickness of three microns and less; wherein the implantation process is characterized by a range of five microns to ten microns, making the range of the implantation A characteristic space dimension is not disturbed by the plurality of transistor devices and the thickness of the interconnection region. In one example, the plurality of transistor devices are provided for a memory array or a logic array.

In one example, the energy is selected from thermal, mechanical, chemical, electrical, or a combination thereof. Provides a split-inducing energy. In one example, the energy is provided to cause a controlled divisional action, including the onset of division and the propagation of division. In one example, the energy is provided to form a plurality of microplate bubbles in the split region. A split surface can be connected to a network of tiny plate bubbles.

This disclosure achieves these benefits and others with known process technologies. However, a further understanding of the nature and advantages of this disclosure can be achieved with reference to the later part of this specification and accompanying drawings.

1000‧‧‧ Procedure

1002‧‧‧ donor substrate

1004‧‧‧ split plane formation

1006‧‧‧Disposal substrate

1008‧‧‧Plasma activation combined process

1010‧‧‧ via transfer layer

1011‧‧‧Recycling

1012‧‧‧Epicrystalline (EPI) smoothed and thickened

1014‧‧‧ separable substrate

1050‧‧‧Simplified procedure

1052‧‧‧IC Processing

1054‧‧‧ Thin

1100‧‧‧General IC program flow

1102‧‧‧wafer

1104‧‧‧IC layer `` n + 1 ''

1106‧‧‧Wafer Scale Processing (WSP) stacking (1 to n)

1108‧‧‧Floor

1200‧‧‧Simplified procedure

1202‧‧‧ split plane

1203‧‧‧ substrate

1204‧‧‧ split

1206‧‧‧IC processing

1300‧‧‧Simplified procedure

1302‧‧‧ substrate

1304‧‧‧ Etching

1400‧‧‧Procedure

1402‧‧‧ substrate

1500‧‧‧Simplified procedure

1502‧‧‧ Silicon Film

1504‧‧‧Releasable substrate

1506‧‧‧IC process

1508‧‧‧treated layer

2100‧‧‧Procedure for forming a 3DIC structure with different grain sizes

2102‧‧‧Procedure

2104‧‧‧Procedure

2106‧‧‧Procedure

2108‧‧‧Procedure

2110‧‧‧program / die

2112‧‧‧flattening process

2202‧‧‧ Base Device Structure

2202A‧‧‧Wafer level semiconductor layer

2202B‧‧‧ Wafer-level combined semiconductor layer

2204‧‧‧Metal connection layer between devices

2206‧‧‧Vertical Through Hole

2208‧‧‧Interconnect Layer

2210‧‧‧ Grain

2212‧‧‧ Dielectric Materials

2214‧‧‧Filling material

2216‧‧‧Interconnection Structure

2218‧‧‧ Upper Device Level

2702‧‧‧ base device structure

2710‧‧‧ Grain

2718‧‧‧Superstructure

2720‧‧‧ cooling channel

2722‧‧‧Vertical Through Hole

2902‧‧‧ patterned range compensation layer

FIG. 1 is a schematic diagram of an embodiment of the present disclosure.

FIG. 2 illustrates a heterostructure including an transistor device layer and an upper network of a metal and a low-dielectric constant material in an example, wherein the structure is provided by implantation through an additional patterned photoresist layer Interlayer coolant channels.

2A to 2B are simplified cross-sectional views showing the use of a patterned oxide as an absorbent.

FIG. 3 is a schematic diagram of a transferred device layer viewed at an uneven surface splitting point after protons are implanted through a patterned double-layer photoresist (PR) layer in an example, with the PR layer removed and attached Rear view of a temporary combined transfer stand.

FIG. 4 outlines an IC device to be transferred at a high-dose proton implantation point in an example, where a uniform PR layer is in place on the device metal interconnect layer.

FIG. 5 is a simplified diagram of a transfer device layer after proton implantation, removal of a temporarily combined transfer mount PR layer, and completion of a wafer-level splitting process in an example.

FIG. 6 shows the main steps applied to the bottom region of the transferred device layer in an example, including removing an implantation damage layer and finally adjusting the thickness of the device layer substrate layer to form an oxide layer suitable for bonding, and forming Dense array of interlayer metal connections and bonding pads.

FIG. 7 shows an upper surface of a lower device layer in a stack with a developing 3D device in an example Split and prepared transferred device layers at points where mating interconnect structures are precisely aligned on the face.

Figure 8 shows a compact 3D stack completed by one of the transferred IC devices bonded to the lower device layer in one example, with the alignment interlevel metal wires in place and bonded to the landing pad along the oxide layer bonding interface Office.

FIG. 9 shows a schematic example of two device layers stacked with a thick metal interconnect layer in an example.

FIG. 10 shows an example of a process flow for preparing a detachable substrate according to an embodiment.

FIG. 10A shows IC processing and / or thinning steps performed downstream of the program flow shown in FIG. 10.

FIG. 11 shows a simplified diagram of a general IC program flow according to an embodiment.

12 to 15 show simplified processing flows according to various alternative embodiments.

FIG. 16 is a simplified cross-sectional view of one of the patterned high-K layers in a suitable location showing a coolant channel.

FIG. 17A is a simplified cross-sectional view showing an example of a thin substrate layer under a net compressive stress after its manufacture, with a disassembled, unsupported device layer deforming the thin substrate layer into a concave shape.

17B is a simplified cross-sectional view of the effect of adding a stress compensation layer to the back side of a thin substrate containing a stressed device layer on the top side.

FIG. 18 is a simplified diagram of a chemical or mechanical "weak" separation layer incorporating a high purity, single crystal transfer layer on a substrate.

FIG. 19A shows a simplified cross-sectional view of a high-energy, high-dose proton implantation to form a hydrogen-rich layer placed several microns below the CMOS transistor layer.

FIG. 19B is a CMOS device after the final gate stack and metal interconnection structure are formed. A simplified cross-sectional view of a layer in which the hydrogen-rich layer is formed by a high-energy, high-dose proton implantation performed before the "replacement gate" manufacturing step.

FIG. 20 shows a simplified cross-sectional view of a combination of a "top-to-top" metal layer of a transfer device layer and a lower device layer in a 3DIC stack.

FIG. 21 illustrates a procedure for forming a 3DIC structure with different grain sizes.

Fig. 22 is a simplified cross-sectional view showing an example of the structure of the lower device.

FIG. 23 is a simplified cross-sectional view showing an example of a stacked device structure.

FIG. 24 is a simplified cross-sectional view showing an example of a smaller grain size device incorporated on a 3DIC.

25 is a simplified cross-sectional view showing one example of a material deposited on a smaller grain size device bonded on a 3DIC.

FIG. 26 is a simplified cross-sectional view showing an example of a 3DIC structure with different grain sizes.

FIG. 27 is a simplified cross-sectional view showing another example of a 3DIC structure with different grain sizes.

FIG. 28 is a simplified cross-sectional view showing an example of proton implantation.

FIG. 29 is a simplified cross-sectional view showing an example of proton implantation through a range compensation layer.

Figure 30 illustrates the thermal conductivity of silicon substrates at various concentrations and temperatures of phosphorus-containing dopants.

FIG. 31 illustrates the thermal conductivity of a silicon substrate at various boron dopant concentrations and temperatures.

FIG. 32 illustrates temperature-dependent thermal conductivity of 6H-SiC at various temperatures and dopant concentrations.

Figure 33 illustrates the thermal conductivity of various carbon materials.

Figure 34 illustrates a bonding step for a transfer layer.

Figure 35 illustrates the formation of a buried hydrogen cross section under a partially completed device layer.

Figure 36 illustrates a complete device layer on a hydrogen profile.

FIG. 37 illustrates a 1 MeV proton implanted into a 3 μm-thick multilayer containing Cu metal and SiO ₂ dielectric layers on a Si substrate, with a CMOS device layer positioned immediately below the metal / oxide multilayer.

38A and 38B illustrate a recoil profile and an ionization profile for the implant of FIG. 37, respectively.

According to the present disclosure, techniques related generally to the manufacture of integrated circuit devices are provided. More specifically, the present disclosure provides a method and resulting device for stacking and interconnecting three-dimensional (3-D) devices using heterogeneous and non-uniform layers, such as fully fabricated integrated circuits. By way of example, the integrated circuit may include, in particular, a memory device, a processor device, a digital signal processing device, a special application device, a controller device, a communication device, and others.

An embodiment establishes and expands the technical capabilities of two large regions, a layer transfer method for forming a bonded stack of homogeneous layers (such as forming a silicon-on-insulator (SOI) wafer), and the complexity in current use and development. A sparse array of interposer layers and metal vias are used in various methods for connecting devices to form a 3-D stack of electrical devices.

One embodiment provides stacking and interconnection of a variety of electrical and electromechanical layers by simplifying the bonding and interconnecting structure with a physical scale of a factor of 10 or greater than the currently available insert / TSV method, and provides a significant increase A method of electrical connection paths between a number of devices (which results in greatly expanded data transfer bandwidth and 3-D device functionality). This disclosure also provides protection of sensitive device layers from the harmful UV radiation associated with the use of high-energy proton beam lines, and the construction of an interlevel network that provides coolant flow channels for self-functional 3-D device stacking. Volume to remove heat. Additional details of this disclosure may be found throughout this specification and more particularly below.

Embodiments can combine technologies such as H-cut separation and plasma activation to achieve room temperature transfer procedures and Si separation using MeV proton technology to combine silicon-on-insulator (SOI) wafer formation methods to achieve full CMOS 3D stacking.

This layer transfer (LT) applied to 3D wafer-scale packaging (WSP) can allow a large number of benefits due to its highly parallel connectivity and its ability to go to different processes. The embedded RAM / cache layer is a natural application.

Knowing the WSP approach can experience challenges in one or more of the various areas: bonding, layer alignment, layer thinning, and layer interconnection. For example, thinning a layer to less than 10 μm may desirably result in a conductor with a smaller aspect ratio.

The use of a plasma fusion combination allows favorable alignment. Also, embodiments as described herein may enable layer alignment and interconnection as a practically achievable goal.

Embodiments utilizing LT technology involving cold processing allow processing of wafers with interlayer dielectric (ILD) / metal interconnects. Fusion activation of plasma activation gives bonding strength, ultra-thin bonding, no glue layer. As described below, rapid thinning operations are possible and do not necessarily require chemical mechanical polishing (CMP), polishing, or grinding operations.

The embodiments are compatible with a variety of IC processes, including processes for manufacturing complementary metal oxide semiconductor (CMOS) and random access memory (RAM) devices.

The use of implantation at MeV energy allows for thicker implantation through all device layers (10 μm). As a result, full CMOS device layers can be transferred instead of partial layers.

Implant scanning techniques can be used. Examples may include obtaining channel effect improvements via "dithering".

According to embodiments, the use of MeV protons for full CMOS stacking may provide certain benefits. Embodiments may allow avoiding shadows due to CMOS layers including transistors, dielectrics, and / or metal layer structures.

The 1MeV proton beam is sufficient to perform H-cut implantation through 8 Cu metal interconnect layers and a full-depth CMOS microprocessor (MPU). 10 μm Si penetration.

For a 1 MeV proton beam through a model 8-layer Cu interconnect array and connected CMOS transistor layers, this 10 μm depth in Si is large enough to separate the damage peak from the CMOS device region. The desired minimum separation of the CMOS transistor layer in the proton-damaged region and the combined oxide surface through the substrate layer of the transfer layer is the depletion in the substrate material of a biased, energized bulk CMOS array substrate. Depth is about 1 micron for 1V supply voltage and 10 ohm-cm substrate material. Depending on the device design and power supply voltage, the CMOS transistor layer including block-type "finFET" and "fully depleted SOI" devices may have a slightly thinner substrate depletion thickness. The relative accuracy (dispersion / range) of the 1MeV proton profile is higher than that of a standard SOI wafer fabrication implant (in 40keV).

It should be further noted that the H peak depth may be reduced by spin-coating the resist absorbing layer. This aspect is further described in conjunction with FIGS. 1 to 9 discussed later.

FIG. 10 shows an example of a process flow 1000 for preparing a detachable substrate according to an embodiment. Here, the donor substrate 1002 is subjected to a split plane formation 1004, for example, by implantation of hydrogen ions.

Next, the donor substrate including the split plane is bonded to a processing substrate 1006, for example, by a plasma activation bonding process 1008. Next, LT occurs by performing a room temperature controlled splitting process (rT-CCP ^™ ), so that a portion of the donor remains with the processing substrate. Alternatively, a portion of the donor may remain with a temporary carrier substrate, provided that this layer is to be re-transferred to a permanent processing substrate again (for example, for a backside illuminated CMOS image sensor).

The rest of the 1011 donor substrate is recovered for additional use. The treatment including the transferred layer 1010 may be subjected to further processing, such as epitaxial (EPI) smoothing and thickening 1012 to produce a detachable substrate 1014.

FIG. 10A shows a simplified process flow 1050 illustrating the downstream steps performed on the substrate provided by the substrate manufacturer of FIG. 10. These steps may include IC processing 1052 (see, for example, Figure 11 below) and / or thinning 1054 (for example, see Figures 12 to 15 below).

Specifically, FIG. 11 shows a simplified diagram of a general IC program flow 1100 according to an embodiment. Here, the IC maker receives the "special wafer" 1102 and processes the IC layer "n + 1" 1104 without any modification.

Next, the IC layers are bonded onto a wafer scale processing (WSP) stack (1 to n) 1106. After bonding, the wafer 1102 can be released.

The last shown in FIG. 11 is to perform steps such as interconnect processing, chemical mechanical polishing (CMP), etc. to surface-treat layer 1108. This step can be repeated for layer "n + 2".

At least four layer transfer (LT) packaging variants are possible. Figures 12 to 15 describe four options for thinned LT.

FIG. 12 shows an embodiment of the LT after IC processing. The simplified program flow 1200 shown in this figure involves placing a split plane 1202 within a substrate 1203, and then split 1204 after the IC process 1206. It requires more invasive post-IC process steps.

FIG. 13 shows an embodiment utilizing splitting onto an etchable substrate. The simplified process flow 1300 according to this embodiment allows the 1304 substrate 1302 to be etched more easily than the SOI bonding back grinding process.

In these embodiments, the etchable substrate may be thin. An electrostatic (ES) chuck can be used to help strengthen splitting and dispose of thin substrates. A transparent substrate helps layer alignment.

FIG. 14 shows an embodiment of a process flow 1400 in which the substrate 1402 includes a "thin" substrate attached to a releasable base substrate. This thin substrate can be used in the final 3D product. Releasable substrates are only used for handling during the IC manufacturing process.

FIG. 15 shows a simplified program flow 1500 according to one of the other embodiments. Here, The silicon film 1502 is mounted on a releasable substrate 1504. The releasable substrate is used only for handling during the IC process 1506, resulting in a processed layer 1508. An internal release layer is used after the LT. The release layer is placed in the bonding plane. LT is used to release the treated Si layer, which is then thickened if necessary.

In the case of one or more embodiments, certain features and benefits may be accumulated. For example, with the close-stacked specific application of fully-manufactured integrated circuits (including transistor layers and multilayer interconnect networks), H-cut segmentation and layer transfer technology can be extended beyond lamination of uniform composition layers Wafer-scale stacking of heterogeneous and uneven individual layers.

Embodiments can use the "tight combination" and layer transfer technology with H-cuts to achieve high data transfer bandwidth with high-density inter-die interconnects with thin device stacks.

Embodiments can increase manufacturability and device yield by using a room temperature to appropriate temperature process through the stack process.

Some implementations can draw device layer laminations using H-cut and plasma combined operations (using high alignment accuracy combined with tools).

Certain embodiments may utilize changes regarding front-to-back stacking and front-to-front stacking combinations, with corresponding interconnect depth and location.

Some embodiments can make the overall device layer components thin (no need for inserts), with reduced RC losses, even for high-density device-to-body connection.

Certain embodiments may implement methods suitable for bonding and thermal transfer requirements (much less stringent than SOI wafer layer lamination) for post-segmentation damage layer removal and substrate thickness reduction (selective etching).

Certain additional factors for specific embodiments are also described. In various IC designs, some of these factors can deal with uneven total Cu interconnect thickness.

For example, weights and measures can be used. The scanning effect of uneven Cu density collects backscattered proton currents from a large angle collector facing the metal surface of the IC. For MeV proton beams, it has 1 × 1 μm ² pore size. An accuracy-level scanner for IC motion under the aperture plans the net Cu density by backscattering the current.

Design rules can be used to resolve inhomogeneities. These design rules may specify allowable variations in the total Cu thickness across the IC device region. Wafer level division can be achieved by a large area checkerboard H distribution.

A manufacturing process can be used to resolve the non-uniformities. For example, a "dummy" Cu or other similar material layer may be added at a location with a low Cu thickness, such as an interlayer metal via channel. Examples of other materials include materials such as CVD-deposited oxide and nitride dielectrics, polymers, and other metals. In general, the material should have sufficient ion stopping power and thickness to bring the position of the deep proton peak to a substantially similar depth across a split plane.

Embodiments can set the split plane depth (not directly affected by changes in proton energy or total Cu layer density) by constructing an IC device on a highly stressed surface layer, such as a graded Si-Ge thin layer. After the high stress interface, the H concentration stops. The split plane will be set by the location of the high concentration H distribution accumulated at the high stress interface of the stack.

By increasing the accumulation of proton lattice-like damage (via the nuclear auto-stop event) with a reduced wafer temperature during proton implantation, the total proton dose and dielectric-bond damage from the electronic auto-stop event (at low k interconnects and high k gate dielectrics).

FIG. 1 is a schematic diagram of an embodiment when a two-device 3D stacking process is completed. After the formation process by hydrogen implantation and the associated splitting process, the upper device layer (a heterogeneous layer containing a transistor formed in a semiconductor material usually Si and a metal usually Cu is used for the lining and The dense network of various other metals of the conductor (layer separated by a low dielectric constant electrical insulator material) is separated from a semiconductor wafer. During proton implantation, the transfer device structure is covered with a uniform photoresistive layer of sufficient thickness and properties to protect the device layer from heavy particles from the proton beamline plasma. Damaged exposure to ultraviolet radiation in combination processes. For the situation shown in Figure 1, the transfer device layer is also coated with a second photoresist layer, which is patterned to adjust the depth of the proton beam and follow the path of the network of coolant flow channels The resulting split surface is designed to remove heat from the volume of the completed 3-D device stack. The conductive structure includes a transistor interface in a metal interconnection network contacting the transistor layer.

After mounting the upper device layer to a temporary combined processing band switch, the split lower surface of the transfer device is processed to remove implant damage in the region of the split surface and adjust the thickness of the transfer device substrate layer. A CVD oxide layer is then deposited on the lower surface to provide an efficient bonding surface, and to provide an electrically insulating and passivated surface for the coolant flow channel (if present). The lower device surface is then etched and filled with metal to form an interlevel electrical connection to a transfer device interconnect layer through a substrate and a deposited oxide layer thickness of about 1 or greater than 1 micron. The interlevel metal wires in the upper transfer device layer are terminated with bonding pads, where the bonding surface is at the same plane as the deposited oxide bonding layer.

A similarly deposited oxide is formed on the top surface of the lower device to provide efficient bonding, and the network of conductors is etched and filled with metal to provide electrical connection to the interconnect layer of the lower device. The lower metal line is terminated by a metal bonding pad at the same plane as the surface of the lower deposited oxide.

The two sets of metal bonding pads are aligned in a precision bonding device and subjected to bonding annealing, thereby completing the 2-stage stacking (with coolant channels) shown in FIG. 1.

Figure 2 shows a view of the patterned PR and device layers after the layer transfer to the lower device layer. In FIG. 2, a heterostructure containing a transistor device layer and an upper network providing a metal and a low dielectric constant material for interconnects of an integrated circuit (IC) is coated with a uniform photoresist (PR) Layer, in which the photoresistive properties and thickness are selected to provide adequate protection of sensitive IC layers and interfaces from ultraviolet (less than 400nm) radiation caused by recombination events exposed to the plasma beam from the proton accelerator. The thickness and termination of the uniform PR layer are also selected to The range is adjusted to a desired depth below one of the IC device transistor and the depletion layer.

In FIG. 2, a second patterned PR layer is added on the uniform PR layer, wherein the thickness and termination of the second PR layer are selected to locally adjust the depth of the implanted proton distribution to provide a non-planar material dividing surface. When the transferred device layer is bonded to the lower device layer, after the PR layer is removed and temporarily bonded to a shelf layer, the non-planar split surface provides a flow of coolant in the completed IC device stack for device operation A network path that removes heat during the period reflects the patterning of the upper PR layer.

Also shown in FIG. 2 are inter-level metal conductors and bonded landing pads and oxide bonding interfaces that are added to the lower section of the device layer before being bonded to the lower device layer, as described in more detail in the following figure. .

The top absorbing layer can be used to (1) locally control the depth of the peak of the proton damage profile in the substrate of the transfer device, thereby controlling the position of the split surface at the separation; (2) defining the coolant channel formed by the change in depth of the split surface Lateral position and depth; and / or (3) providing a protective layer to absorb UV radiation caused by electron capture and subsequent radiative processes by proton ions in the accelerator beamline.

Some embodiments of this process use an unpatterned cross-linked photoresist (PR) layer, in which a second PR layer is deposited on top, exposed by lithography and developed to leave a patterned PR upper layer.

Other embodiments of this process may use a CVD deposited dielectric film. In some embodiments, an unpatterned CVD oxide layer is deposited on the top surface of the metal interconnect network to be transferred to the device layer of the 3DIC stack. The thickness of this first CVD oxide layer can be selected so that the combination of CVD oxide, device metal interconnection network, and device substrate stops the power effect. Protons and damage peaks are placed on the surface of the main split plane below the transistor layer of the transfer device. Desired depth.

A CVD nitride layer is then deposited on the first CVD oxide layer to act as An etch stop layer protects the underlying oxide layer during the etching of the top CVD oxide layer.

Next, a second CVD oxide layer is deposited on the nitride layer. The thickness of the top CVD oxide layer can be selected to locally shift the position of the peak of the incident proton beam to a lower level than the position of the main split surface according to the desired height of the coolant flow channel. The subsequent bonding of layers to a flat bonding surface over one of the underlying device layers in the 3DIC stack is formed.

A PR layer can then be deposited on the top oxide, lithographically exposed and developed to leave a patterned PR upper layer. This patterned PR layer protects the top CVD oxide layer in a location where a coolant channel will be formed during a subsequent oxide etch step, where the nitride layer protects the lower oxide layer.

FIG. 2A is a simplified cross-sectional view of one of the transfer device layers at the proton implantation site, showing an unpatterned top CVD layer with a top CVD layer selected to shift the peaks of the proton profile to the split surface Depth thickness at one of the desired positions. Once patterned, the second CVD oxide layer has a thickness selected to shift the proton beam peak to the height of the (optional) coolant channel to be formed during a subsequent bonding step to the 3DIC device stack. A CVD nitride layer deposited between the two oxide layers serves as an etch stop layer for the top oxide patterned etch.

FIG. 2B is a simplified diagram of the upper layers of the transfer device after the deposition of unpatterned CVD oxide and nitride layers and the top CVD oxide and PR layers. After the lithographic exposure and development of the PR pattern, the exposed top CVD layer material is etched away. The nitride layer protects the lower CVD layer from being removed by etching. The PR layer is removed before proton implantation.

The use of a CVD dielectric layer to form the top absorber layer can provide manufacturing benefits that avoid process complexity that is accompanied by high-energy implants that pass through the polymer PR film, such as due to collisions with the proton beams that pass through The combined destruction of hydrogen and other volatility in PR materials Outgassing of materials.

Local control of proton implantation profiles into the device and substrate layers through the use of patterned and unpatterned CVD top layers can be used to compensate across complex wafer dies and for processing of large area wafers in the process Local variations in pattern density and total layer thickness in metal interconnect networks with various chip designs. This ability for local control of the proton profile depth and the position of the split surface at the separation enables the use of constant energy proton beams for processing of a wide variety of device types, thereby improving the efficiency of embedded wafer manufacturing.

FIG. 3 is a schematic diagram of a transferred device layer viewed at a non-uniform surface split point after protons are implanted through a patterned double-layered PR layer, which is viewed after removing the PR layer and attaching a temporarily bonded transfer mount . After the uneven surface is divided, the damaged material surrounding the split plane (the small plate with H filling and the adjacent grid-like damaged area) is removed, and the extra underlying material is removed, leaving the IC device transistor and depletion. The desired depth of the substrate material for the area.

In addition, the non-planar segmented surface is then treated with a deposited oxide film to form a passivated surface wall for the coolant channel, and an efficient bonding surface for attachment to adjacent device layers. The lower region of the transferred device layer is also processed to form an interlayer metal connection path between the device layers, which is described later in the figures and discussion.

4 to 9 illustrate a 3D stacking process for a set of general IC layers using a uniform top PR layer. For simplicity, the incorporated coolant channel is not provided. Additional details of these drawings may be found throughout this specification and more particularly below.

Figure 4 outlines the IC device to be transferred at the high-dose proton implantation site, where a uniform PR layer is in place on the metal interconnect layer of the device. The metal interconnect layer is usually a densely patterned multilayer structure for advanced logic devices (less commonly used for memory devices) and contains 10 to 15 Cu metal layers. The Cu metal layer is electrically isolated from the conductive body by a staggered layer of a low dielectric constant insulating material. In modern practice, the net Cu layer thickness is usually 3 microns or less. 5 to 8 micron-thick metal layers with accurate distribution of "clock", signal, power, and ground. The provision for the extras in thick metal interconnects is provided as part of the inter-level stacking process.

Select the density, optical properties, and thickness of the PR to provide adequate protection of the underlying device layer from exposure to UV wavelength recombination radiation from the proton accelerator beamline plasma, and adjust the proton peaks and split planes in the transistor doping And the depth below the depletion layer.

A view of the transfer device layer after proton implantation, removal of the PR layer attachment of the temporarily bonded transfer mount, and completion of the wafer-level splitting process is shown in FIG. 5. The splitting action may be affected by the local application of energy in the form of mechanical, chemical, laser or other thermal exposure or global energy or any combination thereof. Splitting can occur using any of the techniques disclosed in the '563 patent, which has been incorporated by reference, or foaming techniques, or others.

Figure 6 shows the main steps applied to the bottom region of the transferred device layer, which includes removing the proton-damaging material and any additional materials in the immediate vicinity of the split plane in order to obtain the desired transfer substrate thickness, (CVD) forming a flat bonding interface and forming interlevel metal lines connecting the transferred device metal interconnect network with the lower bonding pad at the plane of the deposited bonding oxide interface. Demonstrate the formation of interlayer conductors.

Figure 7 shows the split and prepared transferred device layer at a point precisely aligned with the mating interconnect structure on the upper surface of the lower device layer in the developing 3D device stack. One embodiment employs the ability of advanced alignment and bonding equipment. For 300mm wafers, the equipment has a wafer level alignment tolerance in the range of 150nm. Demonstration of through hole and via body landing pads.

Figure 8 shows a compact 3D stack completed by one of the transferred IC devices bonded to the lower device layer, with the alignment interlevel metal wires in place and bonded to the landing pad along the oxide layer bonding interface. Also shown in FIG. 8 is a top-deposited oxide layer, in which the metal vias and landing pads are used at the bonding interface level for subsequent stacking of additional device layers over the currently transferred device layer.

For 3D stacking of large-area, high-performance logic IC devices, the accurate transfer of power, clock, and signal pulses requires a low-resistance path provided by several micron-thick metal wires. These metal layers are too thick to be implanted with an appropriate (1MeV or 2MeV) energy proton beam, and can be used as part of the implantation and splitting after interlevel processing if required and provided before subsequent device layer stacking . Figure 9 shows a schematic example of one of two device layers stacked with a thick metal interconnect layer. The power device has a completed metal layer in place (if it is the bottom device layer), and the upper transferred device has an on-device transfer. And thick metal interconnects that are added after permanent bonding and before deposition of bonded oxides and formation of interlevel metal wires and bonding pads. The dual device stack has a thick metal clock and power distribution layer incorporated.

The discussion here is in terms of a stack of general CMOS devices. A useful example is a stack-expanded memory element connected to one of the data transfer layers for high-frequency signal processing and calculations, such as currently formed by using an interposer layer and a metal interconnect called TSV The memory stack, which has a length of about 30 to 50 microns, is more than 10 times longer than the inter-level connection foreseen in one embodiment.

The use of the embodiments can be used to provide a variety of electrical and electromechanical devices with heterogeneous device layers (for sensing visual images, chemical environments, and a variety of physical conditions) to provide integrated and stable signals in 3-D devices. Manufacturing method of compact 3-D stacking of stacked integrated circuits for processing, memory and data transmission.

Although the above description is for silicon wafers, other substrates can be used. For example, the substrate may be almost any single crystal, polycrystalline, or even amorphous substrate. In addition, the substrate may be made of a group III / V material such as gallium arsenide, gallium nitride (GaN), and others. According to an embodiment, the multilayer substrate may also be used. The multilayer substrate includes a silicon-on-insulator substrate, various interlayers on a semiconductor substrate, and many other types of substrates. Those skilled in the art will readily recognize many alternatives, modifications, and variations.

Generally, high-performance logic devices generate heat in areas with high switching activity in the logic core. These switching heating sources are well-known design concerns in complex system-on-chip (SoC) and central processing unit (CPU) devices. The storage of data in memory devices usually degrades with increasing temperature, so the integrated stacking of logic and memory layers is challenged by these hot concerns. As the density and variety of 3D device stacks increase, thermal control becomes more important.

Although beneficial for thermal bonding efficiency, the use of an oxide layer in a bonded stack can be limited by the relatively low thermal conductivity of SiO ₂ as a heat transfer layer. The use of higher thermal conductivity, electrical insulation materials as interlayer structures can increase heat transfer from the heat source area of the local device.

Therefore, in some embodiments, it may be necessary to add a structured high thermal conductivity layer between the heat generating device layers in order to facilitate heat dissipation and removal of heat from the device stack. Specifically, using a combination of high-energy proton implantation, low thermal budget layer splitting, and transfer can help to dissipate heat from the "hot spots" of the local device structure and efficiently remove the device's thermal energy through the use of local coolant flow.

Proton splitting and layer transfer methods, and a patterned top layer (combined to a flat device surface to form an interlayer for stacking coolant flow) using a photoresist (or oxide, as discussed below) during the proton implantation step The combination of patterned split regions formed by channels) and the use of interlayer structures with high thermal conductivity (and low electrical conductivity) provide flexible design elements for controlling the thermal environment in a complex 3D device stack.

The thermal conductivity of a variety of common semiconductor materials indicates a variety of materials with substantially higher thermal conductivity than SiO ₂ , of which SiC and Al ₂ O ₃ (sapphire) include candidates for this purpose. Compared with the equivalent SiO ₂ layer, for this purpose, other high thermal conductivity materials can also be used, so that 10 to A factor of 100 enhances heat spreading and transportation.

The following Table 1 lists the thermal conductivity (in W / m-K) of some common semiconductor and insulator films:

Si: 130 (W / m-K)

SiO ₂ : 1.3 (W / mK)

SiC: 120 (W / m-K)

Ge: 58 (W / m-K)

GaAs: 52 (W / m-K)

Al ₂ O ₃ : 30 (W / mK)

For efficient heat flow, one can expect Interlayer heat spreading layer thickness of 0.5 μM to 2 μM.

FIG. 16 shows a simplified cross-sectional view of one of the high-K layers including a coolant channel in place including a high-K layer.

Integrated circuit devices containing a variety of semiconductor, dielectric, and metal material layers can generate significant internal stresses during manufacturing. It is unresolved that these stresses can be high enough to warp a sufficiently thick Si wafer (where the thickness is greater than 700 microns) into various concave, convex, and complex shapes. These distortions can be large enough to cause problems in fine-line lithographic optical devices during device fabrication.

If a stress-bearing device layer on a disassembled thin (e.g., several micron) substrate is placed on a flat surface in an unsupported manner, the stress-induced deformation of the wafer-scale assembly can cause bonding to the surface of a planar substrate problem. Due to these effects, the thin device layer can be attached to the rigid bonding structure before it is detached from its initial substrate wafer, which can maintain a planar bonding interface with the attached stressed layer.

FIG. 17A shows a simplified diagram of an example of a thin substrate layer under a net compressive stress after its manufacture, with a disassembled, unsupported device layer deforming the thin substrate layer into a concave shape. The deformation of the actual device layer can be concave, convex, and a complex shape. These deformations can cause problems when bonding to a flat surface, and due to excessive local stress during additional thermal steps during subsequent manufacturing steps and during device operation, leading to bonding failures and device degradation.

Even by using a rigid temporary joint mount to form a stress-containing layer as Suitable for bonding in a flat form, uncompensated stresses in a complex bonded stack can lead to bonding failures and IC device degradation due to thermal stress during subsequent manufacturing steps and during device operation.

Thus, embodiments may provide the addition of a stress compensation layer to the backside of a thin transfer layer of a stressed device to facilitate a bonding process, including improved interlayer device and bonding pad alignment, and to compensate for subsequent manufacturing and device operation thermal cycles Adverse effects. US Patent No. 7,772,088 is hereby incorporated by reference for all purposes.

The back-side stress compensating material can be selected from materials that have a complementary thermal expansion property to the device layer and have a thickness sufficient to offset the distortion effects of stresses within the device structure.

FIG. 17B is a simplified cross-sectional view showing the effect of adding a stress compensation layer to the back side of a thin substrate containing a stressed device layer on the top side. The role of the stress-compensating backside layer is to: (1) help bond to a flat bonding surface, (2) improve bond pad alignment accuracy during wafer-level bonding, and / or (3) offset in subsequent manufacturing steps Effects of differential thermal stress during and during device stacking operations.

The stress compensation layer can be formed by direct layer transfer to the back side of the transfer device layer when the transfer device layer is attached to the temporary bonding structure. In some cases, the stress compensation layer may be deposited by CVD or other methods.

Note that a flat, stress-compensated transfer layer can provide a desirable geometry for achieving high bonding pad alignment during wafer-level bonding, which is a consideration for successful wafer-level bonding for 3DIC manufacturing.

Embodiments may use single crystal layer transfer to chemical or mechanical "weak" separation layers. In particular, it may be necessary to allow a layer of high purity single crystal material to be attached to a temporary holding layer that is sufficiently stable to survive the thermal, chemical, and mechanical stresses of the IC or other device manufacturing process, but is sufficient " "Weak" to form a separation path under guided chemical or mechanical action.

Examples of such weak temporary separation layers may include (but are not limited to) (1) an oxide layer that can be formed by thermal growth, CVD deposition by direct implantation and subsequent heat treatment, which can Actions (such as HF attacks on underlying SiO ₂ layers) to form a separation path under an overlying layer, and (2) various forms of polycrystalline or porous materials that are sensitive to forming a separation path under a selected chemical or mechanical attack Form of general substrate material. Forms of guided mechanical attack may include (but are not limited to) (1) stress-assisted crack formation initiated by a lateral guiding force on a detached wedge tool, and (2) through to areas such as porous substrate material A dynamic attack by a laterally directed fluid jet within a weak layer of machinery.

Some forms of chemically or mechanically weak separation layers may lack the high-order crystal interface required for epitaxial growth of a high-purity and high-quality crystal upper layer suitable for manufacturing high-performance semiconductor devices.

Using high-energy proton implants to form a hydrogen-rich layer for mechanical, room-temperature separation along a well-defined split surface, embodiments can be used to separate all device structures (including fully-formed transistor layers and multilayer metal interconnect networks) and It is bonded to a suitably selected temporary separation layer for later manufacturing and device integration processing. This may then be followed by a subsequent separation from the carrier substrate.

The method and equipment according to the embodiments can also be used to separate and combine uniform, high-purity, and crystalline layers to form electrical, mechanical, or optical devices, followed by subsequent separation from the carrier substrate.

FIG. 18 is a simplified diagram of a chemical or mechanical "weak" separation layer incorporating a high purity, single crystal transfer layer on a substrate. The upper crystal transfer layer is formed to a desired thickness by using high-energy proton implantation and room temperature separation along the peaks of the proton distribution. The upper transfer layer may be a uniform crystalline layer or a combination of IC, mechanical or optical devices and its corresponding metal interconnection network.

Embodiments can also provide proton implantation suitable for separation and layer transfer stacking of highly sensitive CMOS device structures. As mentioned earlier, the embodiment uses high-energy proton implantation to form a hydrogen-rich split surface several microns below the combined thickness, and stops the top layer of photoresist or CVD dielectric and a multilayer metal interconnect network and transistor layer. A combined power effect.

Radiation damage effects caused by high-dose, high-energy proton beams passing through metal interconnects and transistor layers can be at a manageable level that can be recovered by standard annealing cycles at appropriate temperatures. Further, where a particular radiation damage effect has a particular concern, embodiments may include an implementation that bypasses the focus on radiation damage effects in the device's dielectric layer.

One problem with possible radiation damage during high-dose, high-energy proton implantation into the CMOS device layer and its associated metal interconnect network layer is the combined destruction effect in various dielectric layers. This can be attributed to UV self-stopping events from the passage of high-energy proton beams or UV radiation from ion-electron relaxation, followed by recombination events in the accelerator beamline.

When high-dose, high-energy proton implantation is performed at a specific point during the CMOS device manufacturing process, the radiation effect from the proton beam can be substantially avoided. One point in the CMOS process can be identified as occurring after completion of the high temperature (e.g., greater than 500C) process associated with the activation of dopants in the CMOS interface and the deposition and interlayer interposer of the sensitive gate stack oxide Electrical properties occur before subsequent mergers in metal interconnect networks.

At this point in the CMOS manufacturing process, the main materials in the device wafer are doped junctions with lateral isolation regions filled with polycrystalline silicon and crystalline silicon in the substrate wafer. The only significant, long-term radiation damage effect in major silicon materials is associated with lattice damage caused by the nuclear stop component of the proton slowing process.

The lattice damage event of the high-energy proton beam can be limited to the peak near the proton profile. According to an embodiment, the peak can be placed several microns below the CMOS junction in the transistor layer, and a key hydrogen sink site is provided for localization of the split surface during layer separation. Several micron separations between the CMOS transistor layer and its associated carrier depletion layer and proton-induced lattice damage in the area of subsequent layer separation may be sufficient to avoid the risk of adverse device effects from the proton lattice damage layer.

In many advanced CMOS devices, the gate stack area The film and after the completion of the high temperature thermal cycle are defined by a structure that "replaces" the final device structure with a high dielectric constant ("high k") gate oxide and a multilayer metal gate electrode. After the "replacement gate" manufacturing cycle, the material properties of the final gate and intermetallic ("low-k") dielectric material limit the allowable thermal cycle for the final CMOS device manufacturing process to less than 500C.

The high-dose proton implantation performed immediately before the manufacture of the "replacement gate" will avoid the risk of damage to the gate and intermetal dielectric of the final device, and will not be exposed to 500C or thermal cycling at 500C, This may result in spontaneous layer separation after the completion of the manufacture of the transfer device layer, before the desired non-thermal separation procedure at the time of layer separation.

FIG. 19A shows a simplified cross-sectional view of a high-energy, high-dose proton implantation to form a hydrogen-rich layer placed several microns below the CMOS transistor layer. This is performed after completion of the> 500C anneal associated with dopant activation in the transistor junction and before fabrication of the "replacement gate" including the final device gate dielectric and metal gate electrode.

FIG. 19B is a simplified cross-sectional view of a CMOS device layer after the final gate stack and metal interconnect structure formation is completed, in which the hydrogen-rich layer is a high-energy, high-dose proton implantation performed before the “replace gate” manufacturing step Into formation. The material properties of the final gate and interlayer dielectric limit the manufacturing process temperature to less than 500C, which also avoids causing spontaneous movement along the hydrogen-rich region before the desired separation by the non-thermal method after completion of the complete device structure The state of division.

Utilization of the method and equipment according to the embodiments may allow inter-layer bandwidth to be adjusted in stacking order and inter-layer thickness. Specifically, the main goal of the 3DIC stack is to provide an alternative path for increasing the bandwidth for signal processing communications between devices.

Bandwidth is the product of the frequency of the data signal (often estimated by the CPU clock frequency) and the number of external communication channels. For most of its history, IC development has focused on increasing the cycle frequency of CPU and other data processing chips, possibly at the cost of increased chip power usage. The number of communication channels has been limited by the density of bonding pads available along the perimeter of the flat device.

The development of 3DIC stacking methods has increased the number of possible vertical channels measured by density interlayer communication lines. This density of the inter-layer communication channels increases as the density of the vertical connection channels increases. A convenient measure of the density of the layer-to-layer connections is the inverse square of the communication pin separation or "pitch". Specifically, the IO density = 1 / (pin pitch) ² .

The minimum metal channel or "pin" pitch depends on a variety of process and device considerations. One factor is the aspect ratio (AR) of interlayer metal channels: the ratio of the diameter of the metal wire to the length of the vias to be filled. The conventional "Through Silicon Via" (TSV) structure can typically exhibit AR between about 5 and 20. This is significantly higher than the typical design rule for vias in high-density metallization for IC devices that often have ARs less than 2.

One device consideration that affects the packing density of conventional TSV structures is the inter-device stress caused by different thermal expansions of micro-scale Cu cylinder and Si device materials. Poor local stresses in the near-side environment of Cu via lines can lead to design rules that define micron-scale "no entry" zones, where active circuit components are excluded from near the Cu via landing pads. This affects circuit density, performance, and yield.

Therefore, the method and device of the specific embodiment can provide one or more procedures for locally increasing the density of metal channels between levels and corresponding communication bandwidth between adjacent device layers. High-energy, high-dose proton implantation through a substantially completed metal interconnect network and a fully formed CMOS transistor layer for forming a hydrogen-rich region for non-thermal layer separation and bonding to a 3DIC stack provides a few microns (Or in the case of device layers on SOI buried oxide or other device types with the smallest carrier depletion layer thickness, smaller) inter-layer separation. This allows interlayer separations that are substantially smaller than the tens of microns typical of today's TSV and insert stacking methods. The thinner inter-device Si layer provided by the embodiment and the elimination of interposers and associated adhesion layers allow for shorter and thinner inter-device metal signal connections and greatly reduce the heat from several micron-thick Cu TSV channels today "Zero value zone" effect caused by stress.

In cases where high-layer bandwidth is required (e.g., connection from a CMOS image sensor layer and a signal processing device), some embodiments may use multiple layer transfer technologies to align and bond the top layer of the metal interconnect network of the transfer device to Interlayer connection channels in the top layer of the metal network of the lower device layer in the 3DIC stack. This layer transfer method is outlined in FIGS. 12 to 15.

With this specific procedure, it is expected that the inter-layer communication channel density is similar to the pin density in the top metallization layer in the two device layers, with a pin pitch of about a few microns or less. This "top-to-top" layer combination results in an inter-layer connection density that is 100 to 1,000x times higher than existing 2.5D and 3D chip stacking technologies, and a corresponding increase in bandwidth.

FIG. 20 shows a simplified cross-sectional view of a combination of a "top-to-top" metal layer of a transfer device layer and a lower device layer in a 3DIC stack. Similar to the channel density of the top metal layer of a CMOS device, this method can provide inter-level metal connection channel density and correspondingly increase the bandwidth.

A specific example of the 3DIC structure according to the embodiment may be characterized in that the pin pitch range (in nm) is 1.E + 02 to 1.E + 04 between about 1.0E + 06 to 1.0E + 08. IO density (in pins / cm2). In one example, for a TSV depth of 1 μm, the aspect ratio (depth: minimum width of the diameter) may range from 10 to 1 on a series of TSV diameters from about 0.1 μm to 1 μm.

As mentioned above, proton implantation to form a 3DIC structure according to one of the embodiments may occur at an energy of about 1 MeV, including between about 300 keV to 5 MeV, about 500 keV to 3 MeV, about 700 keV to 2 MeV, or about 800 keV to 1 MeV. energy. For all purposes, U.S. Patent Publication No. 2008/0206962 is incorporated herein by reference.

It should be noted that the implantation properties of hydrogen ions in these higher energy ranges can vary with the energy of 40 keV typical for layer transfer processes used in SOI wafer manufacturing. The first level is described as the "half-width" (<ΔX>) of the proton profile reflecting the "divergence" versus the "projection range" profile. Depth (<X>) ratio.

The comparison of these <ΔX> / <X> results in an example is as follows:

● Proton implantation energy 40keV: <ΔX> / <X> = 0.196 0.2

● Proton implantation energy 1MeV: <ΔX> / <X> = 0.048 0.05

Therefore, the 1MeV proton profile is about 40keV 4x "quasi".

3DIC structures are typically stacked at the wafer level. Wafer-level processing has a number of advantages for economical and efficient processing, especially when combined directly with the transfer method used for the fully metallized CMOS devices described herein.

Wafer-level processing of combined structures typically assumes the use of the same size wafers and tightly coordinate die placement on the bonded wafers to result in a vertically stacked 3DIC structure after separation into discrete systems. For large-area logic and memory devices fabricated on 200mm or 300mm Si wafers in mass production casting processes, these conditions are usually met.

Many of the desirable component (such as, the RF tuner, an amplifier and the like) for communication links on the grain size of the apparatus considerably smaller than the size of ² cm logic and memory. These smaller die sizes can be fabricated on a wide variety of wafer sizes, such as 100mm and 150mm, and can use non-block silicon substrates such as silicon-on-insulator (RF-SOI), GaAs, and the like.

There are many difficulties associated with stacked structures with a variety of grain sizes. Device alignment is important and can be complicated by the thickness differences inherent in the back-grinding process used to thin the grains. The total thickness change (TTV) used in the back grinding process is typically in the range of about 5%. This change can be complicated when multiple layers are stacked, thereby making it possible to perform semiconductor formation processes to facilitate interlayer connection difficulties. As a result, stacked devices use relatively large solder bumps and interposer layers to connect the devices in the vertical stack. In addition, many devices use bonding wires to connect multiple layers side by side in a package.

Embodiments of the present disclosure include a device and process for a 3DIC structure including a heterogeneous grain size. By performing isolation through a circuit structure including a dielectric and a conductive material The sub-implanted grains formed by splitting the base substrate simplify the thinning process and have fewer changes than the back grinding process. TTV values that can be obtained by ion splitting can be, for example, less than 2%, less than 1.5%, and less than 1.0%. In addition, back grinding applies a large amount of mechanical stress to the semiconductor device, which can damage the structure in the device, causing further alignment and performance issues.

FIG. 21 shows an embodiment of a process 2100 for forming a 3DIC structure with different grain sizes. One of the advantages of process 2100 is its economic advantages of combining wafer-level processing and the flexibility to incorporate smaller area die layers that can be fabricated on a variety of substrate materials and wafer sizes into a composite 3DIC structure.

A substrate device structure is prepared at 2102. FIG. 22 illustrates one embodiment of a substrate device structure 2202 using high-energy hydrogen implantation, in which the peak concentration of high-dose hydrogen implantation is in a region of the substrate that is under a metallization layer, which may be, for example, a CMOS or MEMS device layer in.

After splitting along the approximate location of the hydrogen concentration peak, the residual damage along the split plane is removed and transferred to another wafer-scale device layer as shown in FIG. 23. In the embodiment shown in FIG. 23, the base device structure 2202 includes two wafer-level bonded semiconductor layers 2202A and 2202B by implanting ions through dielectric and conductive structures formed on the semiconductor wafer. form. In some embodiments, the base device structure 2202 may have more than two stacked semiconductor layers or a single stacked semiconductor layer.

FIG. 23 illustrates wafer-level bonding in a device orientation, where bonding occurs along two layers of metallization, where the upper (second) device layer is compared to the upper (lower) device layer 2202A facing up and down. 2202B faces down. Although FIG. 23 illustrates only a single device for each of the first and second device layers, in one embodiment, splitting and bonding operations are performed on a plurality of devices on a wafer.

Before the two device layers 2202A and 2202B are combined, there is an opportunity for deposition and patterning of one or more intermediate layers 2204 insulated by an intermetal dielectric material, which can provide Vertical (device-to-device) and lateral connections for signal, timing, insert, and ground connections. The inter-device metal connection layer 2204 is functionally similar to the redistribution layer (RDL) in modern 2.5D multi-chip packaging solutions.

After the first device layer 2202A is bonded to the second device layer 2202B, the middle connection layer 2204 is included, and the vertical through holes 2206 are etched and filled with metal to provide a connection between the device layer and the top surface array of the bonding signal pad.

In procedure 2104, an interconnect layer 2208 is formed on the exposed upper surface of the base device structure 2202. The interconnect layer 2208 may include appropriate bonding pads on the top layer of the base device structure 2202 for direct pick and place addition of various smaller die components, and lateral to the interface between the contact pads exposed by the base device structure 2202 Wiring connections.

In one embodiment, the top metal layer of the interconnect layer 2208 includes a multi-layer metal network for lateral communication, power, and ground connections for a composite device, where the addition is designed for placement and bonding with a smaller Array of bonding pads for a variety of die types of downward-facing metal connectors.

As illustrated in FIG. 24, in procedure 2106, one or more dies 2210 are placed on the interconnect layer 2208. One or more smaller dies 2210 may be placed using known pick and place techniques to align the terminals of the one or more smaller dies 2210 with the bonding pads exposed on the surface above the interconnect layer 2208. The position of discrete die types on the composite wafer-level bonding structure 2202 and metal-to-metal bonding can be achieved by an automated die picking, placing, and bonding device.

In some embodiments, the smaller grains 2210 have different sizes and thicknesses. The smaller grains 2210 may be a heterogeneous set of devices or a homogeneous set of devices that perform different functions.

Since the die 2210 may have various thicknesses, and in some embodiments may be thicker than the desired substrate thickness (e.g., in the range of 1 μM to 10 μM), so at 2108, in A layer of deposited material with a similar etch rate to the substrate grains of the smaller device added under the CMP process can be formed between and above the grains 2210.

For example, as seen in FIG. 25, in procedure 2108, a dielectric material 2212 may be deposited on an exposed surface of a device structure including grains 2210. The dielectric material 2212 provides electrical isolation of the smaller grains 2210. The dielectric material 2212 may be one or more of a variety of materials commonly used in the semiconductor industry that provide insulation from stray currents, including CVD oxides or other suitable insulating materials.

In some embodiments, at 2110, a filler material 2214 is deposited on the dielectric material 2212. When the grain 2210 is a Si device, the deposited layer may be plasma-deposited poly Si or amorphous Si. The filler material 2214 may be selected to have a similar corrosion rate to the substrate material of the dielectric material 2212 and the smaller grain device 2210 when the structure is planarized (eg, by performing CMP) at 2112.

Although process 2100 and associated drawings describe forming separate dielectric materials 2212 and filler materials 2214, in some embodiments, only a single material or more than two materials are deposited on the grains 2210.

A planarization process is performed at 2112 to planarize the upper surface of the device until the contact pads are exposed. The slurry chemistry used in the CMP process can be selected based on the dielectric material 2212 and the filler material 2214 to achieve a substantially equal corrosion rate between the substrate in the added smaller grain structure 2210 and the material deposited on the upper layer. In one embodiment, the flattening process 2112 thins the added smaller die 2210 substrate to a thickness of about 10 μm or less for later forming vertical metal vias for later added structures and bonding pads. Of interconnection. In one embodiment, the planarization 2112 is performed until a total layer thickness of 10 μm to 30 μm is obtained.

In addition, the flattening process 2112 provides a flat top surface for a newly expanded composite device structure for subsequent addition of multilayer metal interconnects and bonding pads for lateral signal, power, and ground connections. Designed for connection to additional layers added to the composite structure by wafer level or discrete die placement methods. In an embodiment, the planarization process 2112 may be performed on the top surface until the surface roughness has an R _A value of 5 angstroms or less, or 5 angstroms or 3 angstroms, or less than 3 angstroms.

The deposition and planarization elements of the program 2100 can be performed to make the substrate of the smaller grains 2110 thinner to a desired thickness. In addition, the dielectric material 2208 and the filler material 2210 provide mechanical support, and in some embodiments, one or more of the layers formed on the die 2110 facilitate thermal transfer away from the final 3DIC structure.

In some embodiments, no additional layers are placed on the smaller die 2210. In their embodiments, the device can be packaged after planarizing 2112 without placing the upper device structure on the smaller die 2210.

As illustrated in FIG. 26, an interconnect structure 2216 is formed in the process to electrically couple at least one of the one or more smaller dies 2210 to the 3DIC upper device layer 2218. The interconnect structure 2216 may be formed on the exposed surface of the smaller die 2210 and / or on the exposed surface of the upper device structure 2218 before it is placed on the smaller die. In various embodiments, the upper device structure 2218 may be a single substrate, two wafer-level bonded substrates, or more than two substrates as illustrated in FIG. 23.

The embodiment of procedure 2100 provides the addition of discrete die layers to a wafer-level procedure flow for a combination of a multilayer device structure to a composite 3DIC structure. The device made according to the procedure 2100 may have lateral electrical isolation of variously added grains in a multi-wafer layer, and may include a dense high-frequency broadband network for a composite device structure containing wafer-level and discrete die placement And vertical metal connections in lateral metal connection networks. When smaller grains of different thicknesses are provided, the procedure 2100 can adapt to these structures by planarizing and thinning a variety of substrates in the composite device layer.

In a 3DIC manufacturing process using wafer-level transfer of metallized transistors and MEMS device layers, it may be advantageous to locally adjust the depth of hydrogen implantation, which determines the approximate split plane used for layer transfer in the steps of the procedure. Local location.

A major challenge in the operation of dense, high-performance circuit elements with 3DIC stacked arrays, such as microprocessor logic and graphics processors and display drivers for image analysis, is the removal of heat from the active device core.

As described above, by adjusting the local penetration depth of the hydrogen implantation profile (by adding a patterned "range adjustment" layer composed of a material formed to a sufficient thickness) to result in hydrogen depth and subsequent localization in the split surface Offset, the network of channels for the flow of coolant fluid can be formed closest to the heat-generating transistor layer. After the splitting of the device transfer layer that splits the surface along a variable depth, by bonding the transfer device layer to a flat surface (such as a planarized top layer of another device layer, as shown in Figure 1), The network may be formed in the bottom surface.

The range compensation layer may include a patterned layer of CVD silicon oxide of an appropriate thickness in combination with an unpatterned silicon nitride layer, the unpatterned silicon nitride layer serving as an etch stop layer for use in the implantation step The patterned oxide layer is then removed. In another embodiment, the range compensation layer is a patterned layer that is a thick photoresist.

FIG. 27 shows an embodiment of an apparatus including a variety of grains 2710 disposed between lower portions having several features not present in the apparatus of FIG. 26. A variety of dies 2710 are formed on a base device structure 2702, which includes implantable ions through metal and dielectric structures to form a split layer at the wafer level and combining the upper and lower portions to form a lower device Structure 2702 to form upper and lower portions. In addition, the device of FIG. 27 shows a plurality of cooling channels 2720 disposed at the interface between the upper and lower portions of the base device structure 2702 and the lower surface of the substrate of the upper device structure 2718.

Another feature of the device shown in FIG. 27 that is different from the device of FIG. 26 is the vertical Location of straight interconnect structure. Although the embodiment of FIG. 26 has vertical through holes 2206 penetrating the upper device structure 2218 and the filler material 2214, FIG. 27 shows a device that passes through the small grain structure 2710 to provide the lower structure 2702, the small grain 2710, and the upper structure 2718. The electrical communication between the vertical through holes 2722. Those skilled in the art will recognize that many variations beyond the specific features shown in Figures 26 and 27 are possible.

The procedure according to the present disclosure can be applied to a transfer device containing a large variation in the density of the total metal layer in a localized area of the transferred device. When hydrogen ions are implanted through the metal and dielectric structures of a semiconductor device, the depth of the split plane can be affected by the conductivity in the circuit layer and the configuration of the dielectric structure. For example, as seen in FIG. 28, the depth of the peak energy that appears as a split plane may be smaller in the high density region of the device than in the low density or sparse region. In some cases, for the purpose of procedural simplicity in layer transfer integration, it may be necessary to have an implanted hydrogen profile depth at the same flat location below the circuit layer.

The depth of the hydrogen split plane can be varied in different sections of a high-performance microprocessor, where a dense multi-layer metallization layer on the logic core is replaced by memory (e.g., embedded SRAM) and timing and input / output circuits. Surrounded by a sparse metal interconnect network. Other examples include optical sensor (honeycomb phone cameras, etc.) devices in which densely metalized image processing circuits are surrounded by a more sparsely metalized array of light sensors. In addition, MEMS devices often contain multiple layers and open spaces of various material densities. These changes can be converted into different stopping powers of hydrogen ions, which can change the depth of the split plane. In one embodiment including a transfer device containing a MEMS device.

As can be seen in Figure 29, the local hydrogen profile shift can be compensated by the patterned range compensation layer 2902 and hydrogen stop power of appropriate thickness to result in a substantially flat hydrogen peak profile depth and split plane. Therefore, embodiments of the present disclosure may include forming a range compensation layer 2902 on a top surface of a semiconductor device to compensate for changes in density and / or type of material existing between the upper surface of the semiconductor device and the split plane. Of ion penetration depth.

In some embodiments, such as the example illustrated in FIG. 29, the compensation layer 2902 has a uniform thickness and is selectively deposited on a region that would otherwise have a device having a higher ion penetration depth than a region without a compensation layer. In other embodiments, the compensation layer 2902 has a change in thickness to account for multiple changes in ion penetration depth. For example, by performing ion implantation on a device that lacks a compensation layer, the depth change in the split plane can be measured and its thickness can be mirrored by the depth change (for example, a larger depth ion penetration region would Associated with a thicker section of the compensation layer, and vice versa) one of the compensation layers to produce the shape of the compensation layer 2902.

In the variation in the depth of the hydrogen profile, the closely spaced stop power variation is generally not replicated on a lateral scale (approximately 1 or more microns) approximately equal to the lateral divergence of high-energy hydrogen ions. Therefore, the thickness of the range compensation layer 2902 may vary between one functional area and another functional area of the circuit, as opposed to changes based on individual nanoscale structures within one area.

In one embodiment, the heat generated by circuit switches and resistive power loss in a volume 3D composite multi-device layer system is effectively provided by forming a cooling channel formed along a split surface defined by a high-concentration hydrogen profile. Removed. The split surface depth is defined by the thickness, the stopping power, and the location of the patterned layer added to the device surface before hydrogen implantation.

As illustrated in FIG. 2A, an embodiment of the present disclosure includes a cooling channel. In the example of FIG. 2A, a cooling channel is established by modulating the depth distribution of the implanted hydrogen with an over-layer of a patterned CVD oxide that is present when hydrogen is implanted to form a split layer. An associated CVD nitride layer is used to provide an etch stop for CVD oxide layer patterning. Both the CVD nitride and oxide layers are removed in a later process.

FIG. 2 illustrates one embodiment of a cooling channel formed along a split surface by shifting a proton depth with a patterned stop layer photoresist (PR) layer. In other embodiments, the termination layer may be a similar dense material deposited on the surface of the device wafer. The thickness and stopping power of the underlying unpatterned PR layer can be used to modulate the split surface features in the substrate material underneath the transferred device layer Depth. Figure 2 shows the formation of a completed cooling fluid channel by bonding a modulated split surface to a flat top surface of an underlying device or substrate layer.

In one embodiment, the cooling channel is enhanced by applying a surface coating. A surface coating material may be selected to improve the heat transfer from the active device layer to the cooling fluid in the cooling channel, and / or reduce or eliminate the chemical reaction between the heat transfer fluid in the cooling channel and the substrate material. For example, in some embodiments, a cooling channel is disposed in a layer having high thermal conductivity, and the high thermal conductivity material reacts with a heat transfer fluid flowing through the coolant channel. In this embodiment, the exposed surface of the coolant channel may be coated with an inert material, such as an oxide or nitride material, which prevents a chemical reaction between the heat transfer fluid and the high thermal conductivity layer material. For example, the inert material may be SiO ₂ or Si ₃ N ₄ .

Those skilled in the art will recognize that the characteristics of the coating material including material type, thickness, and deposition technology may be selected based on the specific thermal conductivity layer material and heat transfer fluid used in an embodiment. In some embodiments, the coating material assists thermal transfer and has a higher thermal conductivity than the substrate material on which the coating is formed. Other advantageous properties of the coating on the coolant channel include excellent adhesion to the material of the coolant channel wall, good thermal conductivity for the coolant material, and a uniform, conformal coating thickness for free flowing, and for the operating temperature of the device The coolant fluid material is inert.

In one embodiment, the fluid in the coolant channel may be a heat transfer fluid having a relatively high thermal conductivity. In some embodiments, the fluid is an inert substance such as water or a highly diluted solution. In other embodiments, the heat transfer fluid may be a nanofluid comprising nanoparticle that enhances the thermal conductivity of the fluid compared to the liquid phase components. The heat transfer fluid may be circulated via an external heat exchanger to transfer heat away from the device.

The location of the cooling channel can be selected to be at one of the transfer device bonding layers as seen in Figure 2, or for situations where direct bonding of the metal layers of the device is required for high frequency broadband circuit connections, in an alternate position, such as See in Figure 20. In Figure 20, the cooling channel is located Near a flat bonding surface of a subsequently added device layer.

In some embodiments, one or more thermal transfer layers may be included in a 3DIC device. The heat transfer layer may be a material having superior heat transfer characteristics than a material used in an active layer. The heat transfer layer may be disposed adjacent to the cooling channel, so that the heat transfer fluid traveling through the cooling channel transfers heat from the device circuit system to the heat transfer layer. In other embodiments, the cooling channels are formed directly in the high thermal conductivity heat transfer layer.

The multilayer lamination of the device allows the insertion of layers of high thermal conductivity materials and interfaces to improve the vertical heat transfer of heat from the lateral spread of locally active circuit areas and to the network of fluids flowing in the cooling channels. Provisioning to control the local depth of the split surface in the material also allows cooling channels to be formed in the subsequently laminated high thermal conductivity layer in a similar manner as the transferred device layer. For example, FIG. 16 illustrates a high thermal conductivity heat spreading layer having one of the coolant flow channels bonded between two circuit layers by a CVD oxide bonding layer.

As indicated in Table 1 above, the room temperature thermal conductivity of silicon (the main substrate material used in current IC manufacturing) has a relatively high thermal conductivity that is closely matched only by silicon carbide (SiC). In one embodiment, it is necessary to use a material having a higher thermal conductivity than Si as the high thermal conductivity layer.

The considerations for materials used for high thermal conductivity thermal transfer materials are the thermal conductivity properties of the material under the temperature characteristics of the circuit operation in action (which is generally 80C to 120C). For Si at room temperature (25C, 300K) and beyond, the thermal conductivity decreases strongly with increasing temperature, leading to the risk of "thermal runaway" in the local area heated by the active circuit power. As can be seen in Figures 30 and 31, due to phonon dopant scattering, for increased dopant concentrations, the Si thermal conductivity decreases at all temperatures. For commonly used Si substrates, the dopant content is relatively low ( 10 ¹⁵ dopants per cubic centimeter), resulting in a relatively high thermal conductivity compared to the higher concentrations illustrated in FIGS. 30 and 31.

Figure 32 illustrates the thermal conductivity of 6H-SiC at various temperatures and doping concentrations as reported by Morelli et al. (1993). In Figure 32, sample 1 is a very pure or highly compensated sample, and the remaining samples have the following electron concentrations: sample 2- n = 3.5 × 10 ¹⁶ cm ^-3 ; sample 3- n = 2.5 × 10 ¹⁶ cm ^-3 ; Sample 4- n = 8.0 × 10 ¹⁷ cm ^-3 ; Sample 5- n = 2.0 × 10 ¹⁷ cm ^-3 ; and Sample 6- n = 3.0 × 10 ¹⁸ cm ^-3 . The thermal conductivity values of various forms of silicon carbide have been reported to be higher than that of silicon. Among them, the conductivity values of 3C, 4H and 6H polytypes are twice as high as 300K.

As illustrated in Figure 33, some carbon-based materials have much higher thermal conductivity than silicon. In detail, diamond, graphite, graphene, and carbon nanotubes all have thermal conductivity values that are substantially higher than silicon (especially at higher temperatures). Although Figures 30 and 31 show a sharp decrease in the thermal conductivity of silicon above room temperature, the decrease in the thermal conductivity of carbon-based materials is relatively shallow, and in the case of amorphous carbon, the thermal conductivity is Increase above room temperature. In detail, the thermal conductivity reported for diamond and graphene is one order of magnitude larger than the thermal conductivity of silicon at 300K. Another material with a high thermal conductivity comparable to that of diamond is cubic boron arsenide. In embodiments of the present disclosure, one of these materials may be used as a bulk substrate material.

In the present disclosure, the term “plane” is used to describe a split plane, which is generally understood as a position separated from the substrate by the split layer. However, as explained above, a range compensation layer may be applied to a substrate prior to ion implantation, which may result in an original split surface including one or more contours that may define, for example, a cooling channel. Therefore, the use of the term "split plane" in this disclosure should not be construed to limit embodiments of the present disclosure to perfectly flat split surfaces.

In one embodiment, a chemically or mechanically weakly split surface is formed by ion implantation before the formation of any sensitive or reliable interface of the device layer or structure. This embodiment can be used in the formation of a complete device structure (including a complete network of metal interconnects and intermetal dielectrics), followed by a splitting action initiated at a preformed splitting surface for transfer to a 3DIC stacked structure.

This embodiment will reduce concerns about device yield and reliability issues related to the formation of embedded split surfaces. In the case of hydrogen-based split surface formation, this embodiment allows substantially lower proton ion energy to be used for the implantation step for a desired split surface depth.

The benefits of this embodiment include the mechanical, thermal, and chemical conditions that should be performed for the post-split plane-forming device manufacturing and testing procedures to avoid premature initiation of the splitting action. In one embodiment using hydrogen-driven splitting, this involves limiting the post-split surface formation process to below 500C temperature.

Many advanced devices (for example, devices containing high dielectric constants or high-K gate oxides such as HfO ₂ and related forms) have thermal budget constraints in this general region.

Figure 34 illustrates a bonding step for a transfer layer. In one embodiment, the transfer layer is a high-purity crystalline transfer layer that is bonded to a substrate layer containing one of the chemistry of a mechanically weak separation layer, which can be subsequently split after initiating the appropriate split surface formation conditions.

35 and 36 illustrate one embodiment of forming an embedded hydrogen profile having a peak concentration suitable for forming a split surface at a depth below one of a partially completed device layer before forming a sensitive device layer, interface, or structure. . FIG. 36 illustrates a fully completed device structure that includes fully constructed metal interconnects and intermetal dielectric layers before introducing process conditions for initiating a split surface at a buried hydrogen-rich split surface.

A procedure may be performed to form a chemically or mechanically weak layer in a partially completed device substrate before forming a sensitive device layer, interface, or structure. The thermal, mechanical, and chemical treatment of subsequent device fabrication may be limited to conditions that do not initiate a splitting action at the location of the splitting surface. Sensitive structures may include gate dielectric and intermetal dielectric layers. An example of a subsequent process limitation for the case of a split surface formed by hydrogen implantation includes processing at or below 500C. In one embodiment, after the split initiated at the split surface, the completed fully metallized device structure is transferred to a 3DIC stack.

Control of implantation conditions during proton implantation is important for successful layer transfer of electronic devices. One aspect of this control is the radiation damage associated with protons passing through the electronic device material and into the underlying substrate.

As the high-energy ion enters the solid target, it transfers kinetic energy in the slow-down procedure via collision with the target material. The details of this stopping procedure are important because energy transfer from the passing protons results in several forms of material rupture or damage, which play a specific role in the layer transfer procedure and in the performance of the transferred electronic device.

Despite the possible complexity of collisions and other interactions, the stopping of ions is controlled by two major types of collisions: (1) collisions between high-energy implanted atoms and the core electrons and the nucleus of the target atom, called nuclear stopping And (2) the collision between a high-energy atom and a loosely bound electron in the shell of the target atom, which is called an electron self-stop.

The effect of these two forms of ion-target atomic collisions depends on the type of material in the target. In an embodiment of the present disclosure, the types of target materials include electronic devices and surrounding structures. A nuclear stop collision causes a large transfer of kinetic energy to the target atom, often driving the target atom out of its original lattice site and establishing interstitial target atoms and empty lattice sites. These gaps and vacancies can be combined with similar defects to form a stable structure, which can be collectively referred to as implantation damage.

In a one-layer transfer procedure using proton implantation, there is the effect of residual implantation damage. During and shortly after implantation is performed, accumulated recoil damage from the cessation of nuclear protons in the target results in the formation of stable damage structures that provide effective sink sites for protons for implantation. Protons trapped in the implant damage layer near the end of the ion track hold the hydrogen in place, rather than quickly diffuse away, and allow the formation of hydrogen-filled small plates that are used to form layers that allow transfer devices Seeds on a split surface separated from the substrate.

The self-stopping of electrons in electronic materials results in local scattering of electrons, often referred to as "ionization." In conductive materials such as Cu metal wires and doped Si materials, electrons are localized Scattering can be quickly repaired by local motion of electrons in these materials. However, high dielectrics (high k), such as low dielectric constant (low-k) layers used to insulate Cu and Co metal interconnects, are often used as gate dielectrics between CMOS gates and channel regions. ) In oxides and insulating materials of oxide or nitride spacers formed along the sidewalls of the gate electrode, it is not easy to neutralize local electron scattering, resulting in isolated charged areas related to broken atomic bonds in the dielectric material And well sites. This application discloses procedures for repairing this damage.

The key aspects of the proton range and damage effects are illustrated by Monte Carlo modeling, for example, by the Auto-Stop and Range (SRIM) software of ions in matter. An example of a SRIM model of the proton range and damage effects is illustrated in Figure 37.

Figure 37 is a graphical representation of a model calculation of a 1MeV proton in a 3 μm thick multilayer containing Cu metal and SiO ₂ dielectric layer for implantation on a Si substrate, where a CMOS device layer is located at metal / oxide Multiple layers immediately below. The proton orbit shows that 1MeV protons extend more than 10 μm deep below the top metal layer. In addition, FIG. 37 shows that the ions emitted from a single point on the wafer surface are laterally spread over several micrometers near the deepest part of the cross section, which is called lateral divergence. Proton insertion at a point on the surface of the metal / oxide multilayer results in the implanted protons being scattered approximately 15 μm below the surface and several μm in the lateral direction.

FIG. 38A illustrates a 1 MeV proton and target atom recoil profile for high-dose proton implantation through the 3 μm-thick metal and oxide multilayer structure, CMOS transistor region, and silicon substrate illustrated in FIG. 37, and FIG. 38B illustrates the corresponding Ionization profile. In FIG. 38A, the depth profile of the implanted proton has a peak concentration at about 14 μm below the top surface, and the top surface is about 11 μm below the CMOS transistor and the depletion layer.

The proton and Si recoil distributions clearly peaked near the deep part of the implant profile. The Si recoil concentration at the CMOS device layer (which is approximately 3 μm deep) is more than ten times lower than the peak recoil concentration peak at the approximate depth of the layer split surface at 14 μm. At a depth of 14 μm The high level of Si recoil at degrees produces a dense network of accumulated damaged structures used to trap implanted hydrogen in place under appropriate process conditions.

Another effect of the proton passing through the model device layer is the deposited energy from the scattering of high-energy protons by loosely bound target electrons. The deposited energy, commonly referred to as the ionization energy expressed in eV / Angstroms, has strong peaks in Cu metal and deep Si layers, as seen in Figure 38B. These effects are quickly neutralized by the movement of nearby electrons in these two conductive materials. Although the deposited energy from the electron scattering in the oxide layer is relatively small at about 4 eV / angstroms in this example, any scattering collisions that result in displaced electrons are not easily destroyed by the electron movement in the insulating dielectric layer. Combined.

Although this damage may not have a strong effect on highly conductive materials, it may have a large adverse effect on other structures such as dielectric structures. In some relatively large-scale structures such as thin film transistors (TFTs) and some MOSFETs where reduced switching times and leakage currents are less important, the adverse effects may be less significant. However, the inventors of this disclosure have discovered that to the extent that many high-performance devices are rendered inoperable due to ion implantation, damage caused by ion implantation through sensitive structures can affect small-scale and high-performance devices such as , Modern processors and memory devices) have profound effects.

One way to reduce the damaging effects of ion implantation is to choose an appropriate implantation energy. In one embodiment, the proton energy can be set sufficiently high so that the peaks of the proton and recoil damage distribution are greater than the position of the transistor layer of the electronic device and the thickness of the depletion layer formed when the device is under operating potential (for example, 1 μm deep in 10 Ohm-cm Si, which is a common resistivity. Any overlap between the proton damage layer and the empty area of the device can lead to strong leakage currents, carrier recombination, and other adverse effects on device performance.

Since the split surface can then be bonded to another surface to form a 3D stacked structure, the proton depth and associated depletion width below the transistor layer should allow removal of the majority Or all of the split surface damage areas to form one of sufficient flatness and smoothness of the bonding surface for high-strength atomic bonding.

In an embodiment, the implantation conditions are set to be advantageous for forming a dense and stable accumulated damage region at the desired location of the splitting surface, where most of the proton distribution of the sinking peak. In detail, the embodiment may use a high proton ion density beam, a slow beam, and a wafer scanning speed, and maintain the target temperature during implantation below the in-situ annealing start of recoil damage. It is approximately 100C, and lower for other materials of interest, such as III-V compounds. Implant machines suitable for the embodiments of this application include trimmed ion implanters produced before about 2002.

A heat treatment (such as deposition of a CVD layer, heat treatment of an intermediate bonding layer, etc.) may be performed after implantation and before splitting along the hydrogen-rich layer in order to maintain the integrity of the hydrogen sink damage layer. Studies of hydrogen release from implanted Si after thermal annealing and inspection of proton-damaged structures show that the maximum allowable temperature for maintaining proton sinking is approximately 400C. Accordingly, embodiments of the present application may include limiting all thermal processes performed after hydrogen implantation and before splitting to a temperature that may not exceed one of the maximum temperatures, such as 500C, 450C, or 400C.

The inventors of this disclosure have discovered that damage caused by hydrogen implantation can be repaired under specific conditions, including self-stop and recoil damage. Without repair operations, the device may be damaged or completely inoperable. The recovery of damage associated with electronic self-stop in the various layers of electronic devices is important to the success of 3DIC device stacks using proton implantation process technology.

In one embodiment, a thermal process for repairing damage to the dielectric and conductive structures is performed in an environment including hydrogen at a temperature of 350C or more. Conditions in a repair procedure should be sufficient to allow hydrogen to penetrate the surface of the device and bind to molecules damaged by an implantation process. In a specific embodiment, the repair annealing is performed in an atmosphere including from 2% to 5% hydrogen (the rest is one or more inert gases) at a temperature of 400C.

In one embodiment, the repair annealing is performed sufficiently to allow hydrogen diffusion despite A time period of one passivation site in a circuit structure in an arrangement (which may include an interconnection network of metal and one of a low dielectric constant dielectric material) and occupying a damaged dielectric junction. For example, in one embodiment, annealing is performed at a temperature of 400C for one hour to repair implant damage.

Several variables affect the appropriate time and temperature for implant repair. The specific temperature is the amount of time it takes for hydrogen to diffuse through the metal and dielectric interconnect network and the gate stack structure to the area where the damaged bond is located, which can be specific to each device. The diffusion of atoms in the material is proportional to (Dt) ^1/2 , where D is a rate of diffusion that depends on the temperature exponentially, and t is the diffusion time.

For many silicon-based dielectrics and device designs, the use of a 4% hydrogen and 96% nitrogen blend at 400C for one hour is suitable for repairing implant damage. Repair procedures can be performed at temperatures as low as 300C. In another embodiment, a temperature of up to 500C can be used. However, some materials are sensitive to high temperatures. Exposure of the device to high temperatures and longer periods can cause adverse phase changes in high-k dielectric gate oxides such as HfO ₂ , HfSiO _2, etc., lateral direction of dopant diffusion in pair 20nm gate length finFETs Loss of dimensional control and degradation of dopant activation in the laser doped junction contact area. With these principles in mind, those skilled in the art will recognize that appropriate thermal repair procedures can be performed in a gaseous environment containing at least 1% hydrogen at temperatures from 300C to 500C and for at least 30 minutes.

Therefore, those skilled in the art will recognize that in various embodiments, changes in time, temperature, and hydrogen concentration may be different because these variables are related to each other. One combination of lower time, temperature, and concentration may not be sufficient to repair implant damage, while longer time and temperature may cause hydrogen ions accumulated in the split layer to diffuse into the substrate, or have other properties associated with an expanded heat distribution Negative effects. Higher hydrogen concentrations pose an explosion risk. Temperature can also be changed during a repair procedure.

After ion implantation, some embodiments may use synthetic gas for thermal repair procedures. Syngas is a mixture of nitrogen and hydrogen with a hydrogen concentration typically between 3% and 5%. Of course However, other embodiments may use an inert gas other than nitrogen, and different hydrogen concentrations. For example, embodiments may use an inert gas such as argon, and embodiments may use a hydrogen concentration greater than 1%. Lower hydrogen concentrations may require longer exposures, while higher hydrogen concentrations represent an explosion hazard. When performing a thermal repair procedure, hydrogen penetrates the exposed surface of the damaged device and the combination of damage can be terminated in order to repair the damage.

Thermal annealing by synthesis gas or other hydrogen-bearing gas has appropriate time and temperature conditions to allow hydrogen to diffuse into sensitive dielectric layers of electronic devices (including low-k insulators in metal interconnect networks, gate oxides such as SiO ₂ , SiON, high-k dielectrics such as HfO ₂ and oxide and nitride spacer gate sidewall insulators). Materials with higher K values are more sensitive to damage from implants, so thermal repair procedures are more effective for higher K materials. For example, a thermal repair procedure may be performed after implantation through a material having a K value of 10 or greater or a material having a K value of 15, 20, 25, or greater than 25. Specific high-K materials that benefit from thermal repair procedures include hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₂ ), hafnium silicate (HfSiO ₄ ), tantalum oxide (TaO ₅ ), tungsten oxide (WO ₃ ), cerium oxide (CeO ₂ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), strontium titanate (SrTiO ₃ ), lanthanum aluminate (LaAlO ₃ ), niobium pentoxide (NiO ₅ ), zirconium silicate ( ZrSiO ₄ ), zirconia (ZrO ₂ ), barium titanate (BaTiO ₃ ), and lead titanate (PbTiO ₃ ). Experiments have determined that when ions are implanted through a high-K material to form a split layer, a circuit that depends on the high-K properties is non-functional without performing a thermal repair procedure according to one embodiment of the present disclosure.

In one embodiment, the thermal cycling of the repair procedure does not exceed one of the threshold values for the dissolution of the hydrogen sink implant damage structure in the region of the intended split surface. If the temperature exceeds the dissolution threshold, the trapped hydrogen will be dispersed into the substrate, making it impossible to perform a splitting operation. In addition, after repair and before splitting, the temperature to which the substrate is exposed after a repair procedure may be limited to less than a threshold value (eg, 500C, 450C, or 400C) to limit dispersion.

The ambient gas needs to directly access the metal interconnection network and the dielectric layer in the transistor gate stack area to perform a thermal repair process to repair ionic damage. Therefore, on the surface of electronic devices Before sealing, perform a thermal repair procedure. Therefore, it is preferred to perform a thermal repair procedure before performing a deposition process that can limit access to the damaged site. In a 3DIC device, thermal annealing is performed before the layers are bonded.

In an embodiment of the present disclosure, the network of channels for the flow of cooling fluid is adjusted by implanted hydrogen depth by a patterned layer of material at the surface of the device wafer during hydrogen implantation. To define, where the thickness, stopping power, and location are selected to create a non-planar split surface in the transfer device substrate. A similar method for modulating the depth of the split plane can be used to define cooling channels in a selected layer of high thermal conductivity material for subsequent insertion into a laminated multilayer, multi-device 3DIC stack. In one embodiment, the surface area of the cooling fluid flow network is coated with a device layer and substrate selected to increase the thermal conductivity between the heating device layer and the substrate and the flowing cooling fluid and to prevent a chemical reaction between the device substrate and the cooling fluid. Of materials.

The embodiment also has the advantages of a wafer-level combined process, including the incorporation of cooling fluid network channels, and has design flexibility for the incorporation of dies fabricated on different wafer sizes, different wafer thicknesses, and different substrate materials. . Devices formed using the split and stack techniques provided in this disclosure have numerous advantages over conventional techniques. The substrate formed by back grinding is subjected to substantially higher levels of mechanical stress and higher level thickness changes on the surface of the substrate. Ion splitting can be performed with fewer process steps than back grinding, which simplifies the process and reduces the amount of processing required. The layers of the 3DIC structure according to the present disclosure can be interconnected through dense high-frequency vertical and lateral metal connections, which can shift the demand for inserts and solder bump structures, resulting in smaller, more efficient manufacturing Tightly integrated, higher speed device.

Although the foregoing is a full description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. Therefore, the above descriptions and descriptions should not be regarded as limiting the scope of this disclosure.

Claims (40)

A method for forming a three-dimensional integrated circuit (3DIC), the method includes: providing a first substrate having a circuit layer including a plurality of dielectric and conductive structures; and implanting through the circuit layer Ions are implanted into the first substrate to form a split plane; after implanting the ions through the circuit layer, the first substrate is exposed to a hydrogen mixture at a first temperature for a first time to repair Damage caused by the implanted ions; separating a first portion of the first substrate with the plurality of dielectric and conductive structures from a second portion of the first substrate by splitting at the split plane; And bonding the first portion of the substrate to a second substrate. The method of claim 1, further comprising: connecting at least a portion of the conductive structures of the first substrate to the conductive structures of the second substrate. The method according to claim 2, wherein the first substrate and the second substrate are wafer-scale substrates. The method of claim 1, wherein the first substrate is not exposed to any temperature higher than 450C after the plasma is implanted and before the first part is separated from the second part. The method of claim 1, wherein the hydrogen mixture has at least 1% hydrogen and one of the remaining portions of the gas mixture is one or more inert gases. The method of claim 5, wherein the first temperature is from 300C to 500C. The method of claim 6, wherein the first time is at least 30 minutes. The method of claim 1, wherein the conductive and dielectric structures include a high-K dielectric structure including at least one material having a K value of 10 or greater. The method of claim 1, wherein the plasma is at a temperature below 100C and sufficient Most recoil damage and the split plane are placed under proton energy one deeper than the thickness of one depletion layer of an operating transistor. A method for repairing damage caused by implanting ions into a semiconductor substrate through a circuit layer including a conductive and dielectric structure, the method comprising: conducting the conductive and dielectric materials through the semiconductor substrate After the structure is implanted with ions, the semiconductor substrate is exposed to a hydrogen mixture at a first temperature for a first time. The method of claim 10, wherein the dielectric structures include high-K dielectric structures. The method according to claim 11, wherein the high-K dielectric structures include hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₂ ), hafnium silicate (HfSiO ₄ ), tantalum oxide (TaO ₅ ), tungsten oxide (WO ₃ ), cerium oxide (CeO ₂ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), strontium titanate (SrTiO ₃ ), lanthanum aluminate (LaAlO ₃ ), niobium pentoxide (NiO ₅ ), at least one of zirconium silicate (ZrSiO ₄ ) and zirconia (ZrO ₂ ). The method of claim 10, wherein the hydrogen mixture has at least 1% hydrogen and one of the remaining portions of the gas mixture is one or more inert gases. The method according to claim 13, wherein the hydrogen mixture is a synthesis gas. The method of claim 10, wherein the first time is at least half an hour. The method according to claim 15, wherein the first temperature is from 300C to 500C. The method of claim 10, wherein the first temperature is from 350C to 450C. The method according to claim 10, wherein the first time is from half an hour to five hours, and the first temperature is from 350C to 450C. The method of claim 10, wherein the dielectric structures include at least one dielectric material having a K value of 20 or greater, the first temperature is from 300C to 500C, and the hydrogen mixture includes at least 1% hydrogen, And the temperature is at least 30 minutes. The method of claim 10, wherein the implanted ions form a split under the circuit layer flat. A device forming method includes: implanting ions through a dielectric and conductive structure of a first substrate to define a split plane in the first substrate; splitting the first substrate at the split plane to include the first substrate; One of the iso-dielectric and conductive structures is split; the at least one die is bonded to the first substrate, the at least one die has a width smaller than a width of the first substrate; on the at least one die Depositing a planarizing material; planarizing the planarizing material to form a planarized upper surface on the at least one die; and stacking a third substrate on the planarized upper surface. The method of claim 21, wherein the plasma is implanted at a temperature of 100 degrees Celsius or below. The method of claim 21, wherein the plasma is implanted at room temperature. The method according to claim 21, wherein a total thickness change (TTV) of one of the materials split from the substrate is 4% or less. The method according to claim 21, wherein a total thickness change (TTV) of one of the materials split from the substrate is 2% or less. The method according to claim 21, wherein a total thickness change (TTV) of one of the materials split from the substrate is 1% or less. The method according to claim 21, wherein the first substrate, the second substrate, and the third substrate are wafer-scale substrates. The method of claim 21, further comprising: After the first substrate is split, the first substrate is annealed to repair damage to the dielectric and conductive structures caused by the plasma. The method of claim 28, further comprising: after bonding the at least one die to the first substrate and before bonding the third substrate to the at least one die on the at least one die A dielectric material is deposited. The method according to claim 21, further comprising: forming a range compensation layer on the first substrate before implanting the plasma. The method according to claim 28, wherein the first substrate and the third substrate are wafer-scale substrates. The method according to claim 21, further comprising: after splitting the first substrate, bonding the first substrate to a second substrate. The method according to claim 32, wherein the second substrate has a second dielectric and conductive structure, and the second substrate is formed by implanting ions through the second dielectric and conductive structure. The method according to claim 33, wherein the first substrate, the second substrate, and the third substrate are wafers. The method according to claim 21, wherein the at least one die is a device selected from the group consisting of an amplifier, an RF tuner, a radio tuner, a light emitting diode, and an optical sensor. The method of claim 21, wherein the plurality of conductive structures include a plurality of transistors having respective plurality of conductive gates separated from respective channel regions by a gate dielectric. A method for forming a three-dimensional integrated circuit, the method comprises: providing a first semiconductor substrate, the first semiconductor substrate having a first circuit layer including a conductive metal and a dielectric material; Implanting ions with a conductive metal and a dielectric material to establish a first split plane in the first substrate; Splitting the first substrate at the first split plane; providing a second semiconductor substrate having a second circuit layer including a conductive metal and a dielectric material; Conductive metals and dielectric materials implant ions to establish a second split plane in the second substrate; split the second substrate at the second split plane; bond the first substrate to the second substrate; At least one die is stacked on the second substrate, the die has a width smaller than a width of one of the first plurality of circuit structures; a planarizing material is deposited on the at least one die; and the planarizing material is planarized to A planarized upper surface is formed on the at least one die; and a third substrate is stacked on the planarized upper surface. The method according to claim 37, wherein the first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate are wafer-scale substrates. The method according to claim 37, wherein splitting the first substrate and splitting the second substrate are performed at a temperature of 100 degrees Celsius or lower. A method for forming a device, comprising: forming an ion range compensation layer on a surface of a first substrate; implanting ions through the ion range compensation layer and the dielectric and conductive structure of the first substrate to A split plane is defined in a substrate; the first substrate is split at the split plane to obtain a split layer including the dielectric and conductive structures; and at least one crystal grain is bonded to the first substrate. Grains have a ratio One of the plates has a small width; a planarizing material is deposited on the at least one die; the planarizing material is planarized to form a planarized upper surface on the at least one die; and on the planarized surface A third substrate is stacked on the surface.