TW201837725A - Memory controller and data storage device - Google Patents

Abstract

A memory controller coupled to an external memory device for controlling the operations thereof. The memory controller comprises a central processing unit, an interface logic circuit and an arbiter circuit. The central processing unit comprises an internal memory device. The interface logic circuit is coupled to the external memory device and a standard bus. The arbiter circuit is directly coupled to the central processing unit via a static random access memory bus. When the central processing unit has to read predetermined data stored in the external memory device, the central processing unit issues a first request to the interface logic circuit. In response to the first request, the interface logic circuit reads the predetermined data from the external memory device and transmits the predetermined data to the arbiter circuit via the standard bus. The arbiter circuit transfers the predetermined data directly to the central processing unit via the static random access memory bus to write the predetermined data in the internal memory device.

Description

 Memory controller and data storage device  

The present invention relates to a data processing circuit, and more particularly to a data processing circuit that can effectively improve system performance.

As the technology of data storage devices has grown rapidly in recent years, many data storage devices, such as SD/MMC, CF, MS and XD memory cards, solid state drives, embedded memory (embedded) Multi Media Card (abbreviated as eMMC) and Universal Flash Storage (UFS) have been widely used in a variety of applications. Therefore, effective access control has become an important issue on these data storage devices.

In order to improve the access performance of the memory device, the present invention proposes a new memory controller architecture, which not only saves circuit area, but also saves time required for data access, and effectively improves system performance.

The present invention provides a memory controller coupled to an external memory device for controlling the operation of the external memory device, including a central processing unit, an interface logic circuit, and an arbitration circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to the external memory device and a standard bus. The arbitration circuit is coupled to the standard bus and the central processing unit. The arbitration circuit is directly coupled to the central processing unit via a static random access memory bus. When the central processing unit needs to read the predetermined data stored in one of the external memory devices, the central processing unit issues a first request to the interface logic circuit, and the interface logic circuit reads the predetermined data from the external memory device according to the first request, and The predetermined data is transmitted to the arbitration circuit through the standard bus, and the arbitration circuit directly transmits the predetermined data to the central processing unit through the static random access memory bus to write to the internal memory device.

The invention further provides a data storage device comprising a non-volatile memory and a memory controller. The memory controller is coupled to the volatile memory to control the operation of the non-volatile memory. The non-volatile memory includes a central processing unit, an interface logic circuit, and an arbitration circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to the volatile memory and a standard bus. The arbitration circuit is coupled to the standard bus and the central processing unit. The arbitration circuit is directly coupled to the central processing unit via a static random access memory bus. When the central processing unit needs to read the predetermined data stored in one of the non-volatile memory, the central processing unit sends a first request to the interface logic circuit, and the interface logic circuit reads the predetermined request from the non-volatile memory device according to the first request. The data is transmitted to the arbitration circuit through the standard bus, and the arbitration circuit directly transmits the predetermined data to the central processing unit through the static random access memory bus to write to the internal memory device.

100‧‧‧ data storage device

110, 210, 310‧‧‧ memory controller

120, 220, 320‧‧‧ memory devices

230, 330‧‧‧ central processing unit

240‧‧‧Direct memory access device

250, 350‧‧‧ interface logic circuit

260, 360‧‧‧ standard bus

270-1, 270-2, 270-3, 270-N, 370-0, 370-1, 370-2, 370-3, 370-N‧‧‧ arbitration circuit

280-1, 280-2, 280-3, 280-N, 380-2, 380-3, 380-N‧‧‧ dependent memory

231, 331-1, 331-2, ICCM‧‧‧ instructions are tightly coupled to memory

232, 332-1, 332-2, DCCM‧‧‧ data is tightly coupled to the memory

251, 351‧‧‧ error correction code engine

333-1, 333-2, 333-3, 333-4, 343-1, 343-2, 343-3, 343-4‧‧‧ logic circuits

335, 336, 337, 338, 345, 346, 347, 348‧‧ ‧ multiplexers

390, 391, 392, 393‧‧‧ static random access memory bus

1 is a block diagram showing an example of a data storage device according to an embodiment of the invention.

Figure 2 shows the architecture of a memory controller.

Figure 3 is a block diagram showing a memory controller in accordance with an embodiment of the present invention.

Figure 4 is a block diagram showing a memory controller in accordance with another embodiment of the present invention.

In order to make the objects, features and advantages of the present invention more comprehensible, the specific embodiments of the invention are set forth in the accompanying drawings. The intention is to illustrate the spirit of the invention and not to limit the scope of the invention, it being understood that the following embodiments can be implemented by software, hardware, firmware, or any combination of the above.

1 is a block diagram showing an example of a data storage device according to an embodiment of the invention. The data storage device 100 can include a memory controller 110 and a memory device 120. The memory device 120 can be a non-volatile memory such as a NAND Flash. The memory controller 110 is coupled to the memory device 120 for controlling the operation of the memory device 120 and accessing data stored by the memory device 120.

The data storage device 100 can be further coupled to a host (not shown) for transmitting data and instructions to the host or receiving data and instructions from the host. The host can be a mobile phone, a tablet, a laptop, a navigation machine or a car system.

It is to be noted that, for simplicity of explanation, FIG. 1 shows only elements related to the present invention. However, the implementation of the present invention is not limited to the architecture shown in FIG.

Figure 2 shows the architecture of a memory controller. The memory controller 210 can be a controller chip coupled to the external memory device 220. The memory device 220 can include one or more non-volatile memory.

The memory controller 210 can include a central processing unit (CPU) 230, a direct memory access (DMA) device 240, an interface logic circuit 250, a standard bus 260, and a plurality of arbitration circuits. 270-1, 270-2, 270-3...270-N, and a plurality of dependent memories 280-1, 280-2, 280-3...280-N, where N is a positive integer, and The slave memory can be a volatile memory such as a Static Random Access Memory (SRAM).

The direct memory access device 240, the interface logic circuit 250, or other devices (not shown) that access the slave memory can be regarded as the master, and the slave memories 280-1, 280-2. , 280-3...280-N can be considered as a slave/slave. The standard bus 260 is used to provide a transmission interface between the primary device and the secondary device. Arbitration circuits 270-1, 270-2, 270-3, ..., 270-N are coupled to slave memories 280-1, 280-2, 280-3, ..., 280-N, respectively, for respective slave memories. Arbitration. More specifically, the arbitration circuit receives a request or instruction from one or more master devices via standard bus 260, arbitrating the priority of multiple requests or instructions for simultaneously requesting access to the same slave memory by multiple master devices. In the case of the body, it is decided to request which host device to prioritize.

The central processing unit 230 can include a plurality of internal memory devices, for example, an Instruction Closed Coupled Memory (ICCM) 231 and a Data Closed Coupled Memory (DCCM) 232. . Among them, ICCM and DCCM can be static random access memory, ICCM 231 can be used to store code, DCCM 232 can be used to store data.

In the architecture shown in FIG. 2, the direct memory access device 240 is configured to assist the central processing unit 230 to access data stored by the memory device 220. For example, when the central processing unit 230 needs to use the data or code stored in the memory device 220, a read can be sent through a command interface (not shown) coupled to the interface logic circuit 250. Request or read the request instruction. The interface logic circuit 250 reads the data required by the central processing unit 230 from the memory device 220 in response to the request or instruction, and writes the data to the slave memory through the standard bus 260 as indicated by the transmission path indicated as 1 in the figure. 280-1.

The interface logic circuit 250 can include an Error Correction Code (ECC) engine 251. When the error correction code engine 251 detects that the read data has an error, the error data can be read back to the interface logic circuit 250 for error correction as indicated by the transmission path indicated as 2 in the figure, and the correction will be corrected. The correct information is written back to the slave memory 280-1.

After the data required by the central processing unit 230 is transmitted, the interface logic circuit 250 can issue an interrupt signal to the central processing unit 230 (or the central processing unit 230 can also continuously actively request the data status). The central processing unit 230 then issues a request or command through a command interface (not shown) coupled to one of the direct memory access devices 240. In response to the request or instruction, the direct memory access device 240 transfers the data from the slave memory 280-1 to the internal memory device of the central processing unit 230 as indicated by the transmission path indicated as 3 in the figure, for example, the ICCM 231 or DCCM 232.

In the architecture shown in Figure 2, the data transfer required by the central processing unit 230 is required to be performed by the direct memory access device 240, which is inefficient. In order to improve the above defects and improve the access efficiency of the memory device, a new memory controller architecture and data access method are proposed below.

Figure 3 is a block diagram showing a memory controller in accordance with an embodiment of the present invention. The memory controller 310 can be a controller chip of one of the data storage devices shown in FIG. 1 and coupled to the external memory device 320. Memory device 320 can include one or more non-volatile memory.

The memory controller 310 can include a central processing unit 330, an interface logic circuit 350, a standard bus 360, a plurality of arbitration circuits 370-1, 370-2, 370-3...370-N, and a plurality of The slave memories 380-2, 380-3...380-N, where N is a positive integer, and the slave memory can be a volatile memory, such as a static random access memory (SRAM).

The interface logic circuit 350, or other devices (not shown) that access the slave memory can be considered a master, and the slave memories 380-2, 380-3...380-N can be Considered as a slave/slave. The standard bus 360 is used to provide a transmission interface between the primary device and the secondary device. The arbitration circuits 370-2, 370-3, ..., 370-N are coupled to the slave memories 380-2, 380-3, ..., 380-N, respectively, for arbitration of the respective slave memories. More specifically, the arbitration circuit receives a request or instruction from one or more master devices through the standard bus 360, arbitrating the priority of multiple requests or instructions for simultaneously requesting access to the same slave memory by multiple master devices. In the case of the body, it is decided to request which host device to prioritize.

The central processing unit 330 can include a plurality of internal memory devices, such as ICCMs 331-1 and 331-2 for storing code, and DCCM for storing data (for simplicity of illustration, not shown in FIG. 3, Shown in Figure 4), and read-only memory 339. ICCM and DCCM can be static random access memory.

In the architecture shown in FIG. 3, central processing unit 330 does not include a direct memory access device. According to an embodiment of the invention, the arbitration circuit 370-1 is directly coupled to the central processing unit 330 via the static random access memory bus 390, 391. SRAM bus lines 390 and 391 are used to provide a transmission interface to arbitration circuit 370-1 and central processing unit 330.

When the central processing unit 330 needs to use or read the data stored in the memory device 320, for example, the code, a read request or read may be sent through an instruction interface (not shown) coupled to the interface logic circuit 350. Take the request instruction. The interface logic circuit 350 reads the code required by the central processing unit 330 from the memory device 320 in response to the request or instruction, and transmits the data to the arbitration circuit through the standard bus 360 as indicated by the transmission path indicated as 1 in the figure. 370-1. The arbitration circuit 370-1 directly transfers the code to the central processing unit 330 via the static random access memory bus 390 to write to the internal memory device ICCM331-1 or 331-2.

When the interface logic circuit 350 needs to read the data stored in the internal memory device ICCM 331-1 or 331-2, the interface logic circuit 350 issues a read request or a read request command to the arbitration circuit 370-1, and the arbitration circuit 370 -1 receives the read data directly through the SRAM bus 391 in response to the request or the instruction, and transmits the read data to the interface logic circuit 350 through the standard bus 360.

For example, interface logic circuit 350 can include an error correction code engine 351. When the error correction code engine 351 detects that the read code or data has an error, the arbitration circuit 370-1 can directly receive the internal memory device ICCM 331-1 or 331 through the static random access memory bus 391. -2 reading the wrong code or data, and transmitting the data to the interface logic circuit 350 via the standard bus 360 for error correction as indicated by the transmission path indicated as 2 in the figure. The correct code or data corrected will be transmitted to arbitration circuit 370-1 via standard bus 360 following the transmission path labeled 1 in the figure. Arbitration circuit 370-1 then transmits the code directly to central processing unit 330 via static random access memory bus 390 for writing to internal memory device ICCM 331-1 or 331-2.

In accordance with an embodiment of the present invention, central processing unit 330 may include a plurality of multiplexers, such as multiplexers 335, 336, 337, 338 shown in the figures. Multiplexers 335 and 336 can be used to select the source path for writing data. Multiplexers 337 and 338 can be used to select the source path for reading data.

The multiplexers 335 and 336 may respectively include a plurality of input terminals, one of which is connected to one of the internal bus bars of the central processing unit 330, and the other of which is directly connected to the arbitration circuit 370 via the static random access memory bus 390. 1 one output interface. The output of the multiplexer 335 is coupled to the ICCM 331-1, and the output of the multiplexer 336 is coupled to the ICCM 331-2. The multiplexers 335 and 336 respectively multiplex the data from the CPU internal bus bar or the SRAM bus 390 according to a selection signal.

Multiplexers 337 and 338 can each include a complex input, one of which is coupled to ICCM 331-1 and the other of which is coupled to ICCM 331-2. The output of the multiplexer 337 is directly connected to one of the input interfaces of the arbitration circuit 370-1 through the static random access memory bus 391. The output of the multiplexer 338 is coupled to an internal bus of the central processing unit 330. The multiplexers 337 and 338 multiplex the data from the ICCM 331-1 or the ICCM 331-2, respectively, according to a selection signal.

According to an embodiment of the present invention, the central processing unit 330 may further include logic circuits 333-1, 333-2, 333-3, and 333-4. The logic circuits 333-1 and 333-2 respectively generate a selection signal according to an indicator for indicating whether a write operation is performed by an external device (i.e., a device other than the central processing unit 330) and a memory location to be written. For example, when the index of the write operation performed by the external device is set, and the accessed memory location falls within the memory address range of the ICCM 331-1, the value of the selection signal output by the logic circuit 333-1 may be Is 1, for selecting the source path of the written data as an external device, for example, the static random access memory bus 390 and the arbitration circuit 370-1 shown in the figure, so that the external device has the write ICCM 331-1 permission. On the other hand, the value of the selection signal outputted by the logic circuit 333-2 may be 0 to select the source path of the written data as the CPU internal bus, so that the internal device has the right to write to the ICCM 331-2. According to an embodiment of the present invention, the information of the write operation performed by the external device and the information of the accessed memory location may be stored in the central processing unit 330 or the temporary device of the external device.

The logic circuits 333-3 and 333-4 respectively generate a selection signal according to an indicator for indicating whether an external device performs a read operation and a memory position to be read. For example, when the device that wants to read the internal memory of the CPU is an external device, and the accessed memory location falls within the memory address range of the ICCM 331-1, the value of the selection signal output by the logic circuit 333-3 may be It is 0 to select the source path of the read data as ICCM 331-1, so that the external device can read the data of ICCM 331-1. For another example, when the device to read the internal memory of the CPU is the internal device of the CPU, and the accessed memory location falls within the memory address range of the ICCM 331-2, the selection of the output of the logic circuit 333-4 The signal value can be 1, which is used to select the source path of the read data as ICCM 331-2, so that the internal device of the CPU can read the data of ICCM 331-2. According to an embodiment of the present invention, the index of the read operation performed by the external device and the information of the memory location to be read may be stored in the central processing unit 330 or the temporary device of the external device.

It should be noted that although in the above embodiment, the selection signal of the multiplexer is a one-bit signal, the present invention is not limited thereto. It will be readily understood by those skilled in the art that the multiplexers 335, 336, 337, 338 can be expanded to include more than two inputs, so the corresponding selection signal can be a multi-bit signal.

According to an embodiment of the present invention, the internal memory device of the central processing unit 330, for example, one of the ICCMs 331-1 and 331-2 shown in the figure has a data word width set to be one of the data of the standard bus 360. The character width is the same. In addition, the data word width of one of the SRAM bus bars 390 and 391 can also be set to be the same as the data word width of one of the standard bus bars 360. In this way, the data can be directly written into the internal memory device of the central processing unit 330 without being converted by the word width. For example, if one of the data bus widths of the standard bus 360 is X bits, the internal memory device of the central processing unit 330 and the data byte width of one of the static random access memory bus bars 390 and 391 are configured. The data can be set to X bits, and the data depth of the internal memory device of the central processing unit 330 can be set to (M/X) storage units, where M is the internal memory device of the central processing unit 330. The memory capacity, and the data character width X represents the data of the X bit that is accessed for each access of the internal memory device. In addition, the arbitration circuit 370-1 coupled to the standard bus 360 and the SRAM bus can convert data between the standard bus interface protocol and the static random access memory bus interface protocol.

In addition, according to an embodiment of the present invention, in addition to setting the data character width of the internal memory device of the central processing unit 330 and the static random access memory bus, the other control static random access memory bus 390 and 391 The data character width of the circuit and the encoding/decoding method of the memory address must also be set according to the data character width of one of the standard bus bars 360.

It is to be noted that, in order to simplify the description, FIG. 3 shows only the components related to the present invention. However, the implementation of the present invention is not limited to the architecture shown in FIG. For example, the memory controller may further include other host devices not shown in the figures.

Figure 4 is a block diagram showing a memory controller in accordance with another embodiment of the present invention. The structure shown in FIG. 4 is similar to that of FIG. 3, except that FIG. 4 shows DCCMs 332-1 and 332-2 included in the central processing unit 330 for storing data. Therefore, the description of the same components can be referred to the description of FIG. 3, and details are not described herein again. Furthermore, it is worth noting that the elements shown in Figures 3 and 4 can be integrated into the same memory controller.

In the architecture shown in FIG. 4, central processing unit 330 does not include a direct memory access device. In accordance with an embodiment of the present invention, arbitration circuit 370-0 is coupled directly to central processing unit 330 via static random access memory bus 392, 393. SRAM bus lines 392 and 393 are used to provide a transmission interface to arbitration circuit 370-0 and central processing unit 330.

When the central processing unit 330 needs to use or read the data stored in the memory device 320, a read request or a read request command can be issued through an instruction interface (not shown) coupled to the interface logic circuit 350. The interface logic circuit 350 reads the data required by the central processing unit 330 from the memory device 320 in response to the request or instruction, and transmits the data to the arbitration circuit 370 through the standard bus 360 as indicated by the transmission path labeled 1 in the figure. -0. Arbitration circuit 370-0 transmits the code directly to central processing unit 330 via static random access memory bus 392 for writing to internal memory device DCCM 332-1 or 332-2.

When the interface logic circuit 350 needs to read the data stored in the internal memory device DCCM 332-1 or 332-2, the interface logic circuit 350 issues a read request or a read request command to the arbitration circuit 370-0, and the arbitration circuit 370 The -0 receives the read data directly through the SRAM bus 393 in response to the request or the instruction, and transmits the read data to the interface logic circuit 350 through the standard bus 360.

For example, when the error correction code engine 351 of the interface logic circuit 350 detects that the read data has an error, the arbitration circuit 370-0 can directly receive the internal memory device through the static random access memory bus 393. The erroneous data read by the DCCM 332-1 or 332-2 is transmitted to the interface logic circuit 350 via the standard bus 360 for error correction as indicated by the transmission path indicated as 2 in the figure. The correct code or data corrected will be transmitted to arbitration circuit 370-0 via standard bus 360 following the transmission path labeled 1 in the figure. Arbitration circuit 370-0 then transmits the code directly to central processing unit 330 via static random access memory bus 392 for writing to internal memory device DCCM 332-1 or 332-2.

In accordance with an embodiment of the present invention, central processing unit 330 may include a plurality of multiplexers, such as multiplexers 345, 346, 347, and 348 shown in the figures. Multiplexers 345 and 346 can be used to select the source path for writing data. Multiplexers 347 and 348 can be used to select the source path for reading data.

The multiplexers 345 and 346 may respectively include a plurality of input terminals, one of which is connected to one of the internal bus bars of the central processing unit 330, and the other of which is directly connected to the arbitration circuit 370 via the static random access memory bus 392. 0 one output interface. The output of the multiplexer 345 is coupled to the DCCM 332-1, and the output of the multiplexer 346 is coupled to the DCCM 332-2. The multiplexers 345 and 346 respectively multiplex the data from the CPU internal bus bar or the SRAM bus 392 according to a selection signal.

Multiplexers 347 and 348 can each include a complex input, one of which is coupled to DCCM 332-1 and the other of which is coupled to DCCM 332-2. The output of the multiplexer 347 is directly connected to one of the input terminals of the arbitration circuit 370-0 through the static random access memory bus 393. The output of the multiplexer 348 is coupled to an internal bus of the central processing unit 330. Multiplexers 347 and 348 multiplex the data from DCCM 332-1 or DCCM 332-2, respectively, based on a selection signal.

According to an embodiment of the present invention, the central processing unit 330 may further include logic circuits 343-1, 343-2, 343-3, and 343-4. The logic circuits 343-1 and 343-2 respectively generate a selection signal in accordance with an indicator for indicating whether or not an external device (i.e., a device other than the central processing unit 330) performs a write operation and a memory location to be written. For example, when the index of the write operation performed by the external device is set, and the accessed memory location falls within the memory address range of the DCCM 332-1, the value of the selection signal output by the logic circuit 343-1 may be Is 1, for selecting the source path of the written data as an external device, for example, the static random access memory bus 392 and the arbitration circuit 370-0 shown in the figure, so that the external device has the write DCCM 332-1 permission. On the other hand, the value of the selection signal outputted by the logic circuit 343-2 may be 0 to select the source path of the written data as the CPU internal bus, so that the internal device has the right to write to the DCCM 332-2. According to an embodiment of the present invention, the information of the write operation performed by the external device and the information of the accessed memory location may be stored in the central processing unit 330 or the temporary device of the external device.

The logic circuits 343-3 and 343-4 respectively generate a selection signal in accordance with an indicator for indicating whether or not an external device performs a read operation and a memory position to be read. For example, when the device that wants to read the internal memory of the CPU is an external device, and the accessed memory location falls within the memory address range of the DCCM 332-1, the value of the selection signal output by the logic circuit 343-3 may be It is 0, and the source path of the read data is selected as DCCM 332-1, so that the external device can read the data of the DCCM 332-1. For another example, when the device to read the internal memory of the CPU is the internal device of the CPU, and the accessed memory location falls within the memory address range of the DCCM 332-2, the selection signal output by the logic circuit 343-4 The value can be 1, which is used to select the source path of the read data as DCCM 332-2, so that the CPU internal device can read the data of the DCCM 332-2. According to an embodiment of the present invention, the index of the read operation performed by the external device and the information of the memory location to be read may be stored in the central processing unit 330 or the temporary device of the external device.

It should be noted that although in the above embodiment, the selection signal of the multiplexer is a one-bit signal, the present invention is not limited thereto. It will be readily understood by those skilled in the art that the multiplexers 345, 346, 347, 348 can be expanded to include more than two inputs, so the corresponding selection signal can be a multi-bit signal.

According to an embodiment of the present invention, the internal memory device of the central processing unit 330, for example, one of the DCCMs 332-1 and 332-2 shown in the figure has a data word width set to be one of the data of the standard bus 360. The character width is the same. In addition, the data word width of one of the SRAM bus bars 392 and 393 can also be set to be the same as the data word width of one of the standard bus bars 360. In this way, the data can be directly written into the internal memory device of the central processing unit 330 without being converted by the word width. For example, if one of the data bus widths of the standard bus 360 is X bits, the internal memory device of the central processing unit 330 and one of the static random access memory bus bars 392 and 393 have a data word width configured. The data can be set to X bits, and the data depth of the internal memory device of the central processing unit 330 can be set to (M/X) storage units, where M is the internal memory device of the central processing unit 330. The memory capacity, and the data character width X represents the data of the X bit that is accessed for each access of the internal memory device. In addition, the arbitration circuit 370-0 coupled to the standard bus 360 and the SRAM bus can convert the data between the standard bus interface protocol and the static random access memory bus interface protocol.

In addition, according to an embodiment of the present invention, in addition to setting the data character width of the internal memory device of the central processing unit 330 and the static random access memory bus, the other control static random access memory bus 392 and 393 The data character width of the circuit and the encoding/decoding method of the memory address must also be set according to the data character width of one of the standard bus bars 360.

It is to be noted that, in order to simplify the description, FIG. 4 shows only the components related to the present invention. However, the implementation of the present invention is not limited to the architecture shown in FIG. For example, the memory controller may further include other host devices not shown in the figures.

As described above, in the architecture of FIGS. 3 and 4, the use of the direct memory access device and the at least one slave memory is omitted in comparison with the architecture shown in FIG. In this way, not only the circuit area can be saved, but also the movement of the data to the slave memory can be reduced, the time required for data access can be saved, and the system performance can be effectively improved. In addition, since the architectures of Figures 3 and 4 are simpler than the architecture shown in Figure 2, the complexity of the circuit can be reduced, effectively reducing hardware costs.

The term "coupled" in this specification refers to a variety of direct or indirect electrical connections. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Claims (12)

 A memory controller coupled to an external memory device for controlling operation of the external memory device includes: a central processing unit including an internal memory device; and an interface logic circuit coupled to the external The memory device and a standard bus bar; and an arbitration circuit coupled to the standard bus bar and the central processing unit, wherein the arbitration circuit is directly coupled to the central processing unit via a static random access memory bus.    The memory controller of claim 1, wherein the interface logic circuit reads a predetermined data from the external memory device, and transmits the predetermined data to the arbitration circuit through the standard bus, the arbitration The circuit directly transmits the predetermined data to the central processing unit through the static random access memory bus to write to the internal memory device.    The memory controller of claim 1, wherein the arbitration circuit directly reads a predetermined data stored in the internal memory device through the static random access memory bus, and then transmits the standard bus. The predetermined data is transmitted to the interface logic circuit.    The memory controller of claim 1, wherein the central processing unit further includes a multiplexer coupled to the internal memory device, an internal bus bar, and the static random access memory bus And multiplexing data from the internal bus or the static random access memory bus according to a selection signal.    The memory controller of claim 4, wherein the arbitration circuit is directly connected to one of the inputs of the multiplexer through the static random access memory bus.    The memory controller of claim 1, wherein the data word width of one of the internal memory devices is set to be the same as the data word width of one of the standard bus bars.    A data storage device comprising: a non-volatile memory; and a memory controller coupled to the volatile memory for controlling operation of the non-volatile memory, wherein the memory controller comprises: The central processing unit includes an internal memory device; an interface logic circuit coupled to the volatile memory and a standard bus; and an arbitration circuit coupled to the standard bus and the central processing unit, wherein the The arbitration circuit is directly coupled to the central processing unit via a static random access memory bus.    The data storage device of claim 7, wherein the interface logic circuit reads a predetermined data from the non-volatile memory device, and transmits the predetermined data to the arbitration circuit through the standard bus bar, the arbitration The circuit directly transmits the predetermined data to the central processing unit through the static random access memory bus to write to the internal memory device.    The data storage device of claim 7, wherein the arbitration circuit directly reads a predetermined data stored in the internal memory device through the static random access memory bus, and then transmits the standard bus through the standard bus. The predetermined data is transmitted to the interface logic circuit.    The data storage device of claim 7, wherein the central processing unit further includes a multiplexer coupled to the internal memory device, an internal bus bar, and the static random access memory bus. The method is configured to multiplex data from the internal bus or the static random access memory bus according to a selection signal.    The data storage device of claim 10, wherein the arbitration circuit is directly connected to one of the inputs of the multiplexer through the static random access memory bus.    The data storage device of claim 7, wherein the data word width of one of the internal memory devices is set to be the same as the data word width of one of the standard bus bars.