TW201824227A - Display device and electronic device having a signal generating circuit with a function of outputting a signal to the second gate driver for stopping the output of the second scanning signal that controls the second pixel circuit in an arbitrary row - Google Patents

Abstract

The present invention provides a novel display device and electronic device. The display device includes a signal generation circuit, a first gate driver, a second gate driver, and a display panel having pixels. The configuration of pixel includes a liquid crystal element, a light-emitting element, a first pixel circuit which controls the display of the liquid crystal element, and a second pixel circuit which controls the display of the light-emitting element. The first gate driver has a function of outputting a first scanning signal to the first pixel circuit. The second gate driver has a function of outputting the second scanning signal to the second pixel circuit. The signal generating circuit has a function of outputting a signal to the second gate driver, the signal is for stopping the output of the second scanning signal that controls the second pixel circuit in an arbitrary row.

Description

 Display device and electronic device  

One embodiment of the present invention relates to a display device and an electronic device.

Electronic devices equipped with display devices have become popular. When the electronic device is used in a portable manner, a secondary battery is used as a power source. In order to extend the time during which the secondary battery can supply power, the power consumption of the display device is effective.

In order to achieve a reduction in power consumption of the display device, Patent Document 1 proposes a display device in which a reflective element and an illuminating element are combined (Patent Document 1). By using a reflective element in a bright environment and using an illuminating element in a dim environment, it is possible to provide a display device that achieves good display quality and low power consumption without depending on the external light environment.

A technique of using an oxide semiconductor transistor (Oxide Semiconductor transistor, hereinafter referred to as "OS transistor") for a display device such as a liquid crystal display device or an organic EL (electroluminescence) display device has been proposed. Since the off-state current of the OS transistor is very small, a technique using the feature is disclosed in which the power consumption of the liquid crystal display device and the organic EL display device is reduced by reducing the update frequency when the still image is displayed ( Patent Document 2 and Patent Document 3). Note that in the present specification, the above-described technique of reducing the power consumption of the display device is referred to as "Idling stop" or "IDS drive".

[Patent Document 1] Japanese Patent Application Publication No. 2003-157026

[Patent Document 2] Japanese Patent Application Laid-Open No. 2011-141522

[Patent Document 3] Japanese Patent Application Laid-Open No. 2011-141524

Since the IDS driver intermittently updates the data, it is effective in achieving low power consumption. However, the frequency of data updates is reduced, so the convenience may not be high. In order to improve convenience, it is important to update the structure of the display of the portion where the data needs to be updated.

One of the objects of one embodiment of the present invention is to provide a display device and an electronic device which are low in power consumption and excellent in convenience. One of the objects of one embodiment of the present invention is to provide a display device and an electronic device which are excellent in visibility even when used outdoors or indoors.

The above description of the purpose does not prevent the existence of other purposes. One embodiment of the present invention does not need to achieve all of the above objects. Further, objects other than the above can be known from the descriptions of the specification, the drawings, the scope of the patent application, and the like.

One embodiment of the present invention is a display device including a signal generation circuit, a first gate driver, a second gate driver, and a display panel having pixels, wherein the pixel includes a liquid crystal element, a light emitting element, and a control liquid crystal element a first pixel circuit for displaying and a second pixel circuit for controlling display of the light emitting element, the first gate driver having a function of outputting a first scan signal to the first pixel circuit, and the second gate driver having a second pixel circuit output The function of the second scan signal, the signal generating circuit has a function of outputting a signal to the second gate driver that is a signal that stops outputting the second scan signal that controls the second pixel circuit of an arbitrary row.

One embodiment of the present invention is a display device including a signal generation circuit, a first gate driver, a second gate driver, and a display panel having pixels, wherein the pixel includes a liquid crystal element, a light emitting element, and a control liquid crystal element a first pixel circuit for displaying and a second pixel circuit for controlling display of the light emitting element, the first gate driver having a function of outputting a first scan signal to the first pixel circuit, and the second gate driver having a second pixel circuit output a function of the second scan signal, the signal generating circuit having a function of outputting a signal of the second gate driver outputting the output of the second scan signal for controlling the second pixel circuit of the arbitrary row and having the output of the first gate driver stopped The function of the signal of the output of the first scan signal that controls the first pixel circuit of each row.

One embodiment of the present invention is a display device, wherein preferably, the first pixel circuit and the second pixel circuit include a transistor having a metal oxide in the semiconductor layer.

One embodiment of the present invention is a display device in which it is preferable that a transistor included in the first pixel circuit is disposed in the same layer as a transistor included in the second pixel circuit.

One embodiment of the present invention is a display device, wherein preferably, the liquid crystal element includes a reflective electrode provided with an opening, and has a function of reflecting external light for reflection by the reflective electrode, and the light emitting element has a function of emitting light through the opening for display. The function.

One embodiment of the present invention is an electronic device including the display device, the housing, and the power button of one embodiment of the present invention described above. The display device has a function of switching between a first display mode and a second display mode, wherein the first display mode is a mode for outputting a first pixel circuit and a second pixel circuit for controlling each row. a scan signal and a second scan signal are output to a display mode of the first gate driver and the second gate driver, and the second display mode is a mode: a second pixel circuit for stopping control of an arbitrary row The output signal of the two scan signals is output to the display mode of the second gate driver, and the control of the first display mode and the control of the second display mode can be switched by the operation of the power button.

Note that other embodiments of the present invention are described in the description and drawings of the embodiments described below.

According to an embodiment of the present invention, it is possible to provide a display device and an electronic device which are low in power consumption and excellent in convenience. According to an embodiment of the present invention, it is possible to provide a display device and an electronic device which are excellent in visibility even when used outdoors or indoors.

A1‧‧‧ black spots

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CLK1‧‧‧ clock signal

CLK2‧‧‧ clock signal

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PWC1‧‧‧ pulse width control signal

PWC2‧‧‧ pulse width control signal

PWC3‧‧‧ pulse width control signal

PWC4‧‧‧ pulse width control signal

10‧‧‧ display device

10A‧‧‧ display device

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15‧‧‧pixel circuit

16‧‧‧Light

17‧‧‧Pixel circuit

18‧‧‧Display Department

19‧‧ ‧ pixels

20‧‧‧gate driver

21‧‧‧ openings

22‧‧‧ gate driver

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24‧‧‧Source Driver

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26‧‧‧Signal generation circuit

28‧‧‧Signal generation circuit

30‧‧‧ Frame memory

31‧‧‧Source Driver IC

31A‧‧‧Source Driver IC

32‧‧‧ Frame memory

34‧‧‧Control circuit

35‧‧‧Timing controller

36‧‧‧ interface

40‧‧‧Electronic devices

42‧‧‧Shell

44‧‧‧Light sensor

46‧‧‧Power button

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48‧‧‧Background

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50‧‧‧ Watch display department

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52‧‧‧Long, short and second hands

53‧‧‧ dial

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99‧‧‧Application Processor

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203‧‧‧Lighting elements

204‧‧‧Liquid Crystal Components

205‧‧‧Optoelectronics

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207‧‧‧pixel electrode

208‧‧‧Common electrode

209‧‧‧Liquid layer

210‧‧‧ layers

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210b‧‧ layer

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251‧‧‧Substrate

252‧‧‧Adhesive layer

300‧‧ ‧ pixels

301‧‧‧Liquid crystal components

302‧‧‧Lighting elements

303‧‧‧Optoelectronics

304‧‧‧ capacitor

305‧‧‧Optoelectronics

306‧‧‧Optoelectronics

307‧‧‧ capacitor

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311‧‧‧ Conductive layer

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313‧‧‧Semiconductor layer

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315‧‧‧ Conductive layer

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331‧‧‧EL layer

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334‧‧‧Color layer

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351‧‧ ‧ pixels

351a‧‧ pixels

351b‧‧ ‧ pixels

351c‧‧ ‧ pixels

351d‧‧‧ pixels

360‧‧‧Insulation

361‧‧‧ Conductive layer

362‧‧‧Adhesive layer

363‧‧‧Insulation

364‧‧‧Alignment film

365‧‧‧ alignment film

366‧‧‧Liquid layer

406‧‧‧ display device

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6000‧‧‧Display Module

6001‧‧‧Upper cover

6002‧‧‧Undercover

6005‧‧‧FPC

6006‧‧‧ display panel

6009‧‧‧Frame

6010‧‧‧Printed circuit board

6011‧‧‧Battery

6015‧‧‧Lighting Department

6016‧‧‧Receiving Department

6017a‧‧‧Light Guide

6017b‧‧‧Light Guide

6018‧‧‧Light

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5003‧‧‧ display device

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5005‧‧‧ microphone

5006‧‧‧Speakers

5007‧‧‧ operation keys

5008‧‧‧ stylus

5201‧‧‧Shell

5202‧‧‧Display device

5203‧‧‧ watch band

5204‧‧‧Light sensor

5205‧‧‧Switch

5301‧‧‧Shell

5302‧‧‧Shell

5303‧‧‧Display device

5304‧‧‧Photosensor

5305‧‧‧Photosensor

5306‧‧‧Switch

5307‧‧‧Hinges

5701‧‧‧Shell

5702‧‧‧Display device

5801‧‧‧Shell

5802‧‧‧Shell

5803‧‧‧Display device

5804‧‧‧ operation keys

5805‧‧‧ lens

5806‧‧‧Connecting Department

5901‧‧‧Shell

5902‧‧‧Display device

5903‧‧‧ camera

5904‧‧‧Speakers

5905‧‧‧ button

5906‧‧‧External connection

5907‧‧‧Microphone

6200‧‧‧Portable Terminal

6201‧‧‧Portable terminal

6221‧‧‧Shell

6222‧‧‧Display device

6223‧‧‧ operation button

6224‧‧‧Speakers

6225X‧‧‧Light sensor

6225Y‧‧‧Photosensor

In the drawings: FIG. 1 is a view showing a structural example of a display device: FIGS. 2A and 2B are diagrams showing a structural example of a display device: FIG. 3 is a view showing a structural example of the display device: FIG. 4A and 4B is a diagram showing a structural example of a pixel of a display device: FIGS. 5A and 5B are diagrams showing an operation example of the display device: FIG. 6 is a diagram showing an operation example of the display device: FIGS. 7A and 7B are diagrams A diagram showing a working example of the display device: FIGS. 8A and 8B are diagrams showing an operation example of the display device: FIGS. 9A to 9D are diagrams showing an operation example of the display device: FIG. 10 is a view showing a display device FIG. 11A and FIG. 11B are diagrams showing an operation example of the display device: FIGS. 12A and 12B are diagrams showing an operation example of the display device: FIGS. 13A to 13E are diagrams showing a working example of the display device 14A to 14C are diagrams showing a configuration example of a driving circuit of a display device: FIGS. 15A and 15B are diagrams showing a configuration example of a driving circuit of the display device: FIG. 16 is a diagram showing driving of the display device A diagram of a working example of the circuit; FIGS. 17A to 17C are diagrams showing a display device FIG. 18A and FIG. 18B are diagrams showing a structural example of a pixel of a display device; FIGS. 19A and 19B are diagrams showing a structural example of a pixel of the display device; FIG. 20 is a view showing a display; FIG. 21 is a diagram showing a structural example of a pixel of a display device; FIG. 22 is a view showing an example of a cross-sectional structure of the display device; and FIG. 23 is a cross-sectional structure showing the display device. FIG. 24 is a view showing an example of a cross-sectional structure of a display device; FIG. 25 is a view for explaining a measurement result of an XRD spectrum of a sample; and FIGS. 26A to 26L are diagrams illustrating a TEM image and electron winding of a sample; FIG. 27A to FIG. 27C are diagrams illustrating an EDX surface analysis image of a sample; FIGS. 28A and 28B are diagrams showing an example of an appearance of a display module; and FIGS. 29A and 29B are diagrams showing an electronic device. FIG. 30A to FIG. 30F are diagrams showing an example of an electronic device.

Embodiments of the present invention will be described in detail below with reference to the drawings. It is to be noted that the present invention is not limited to the following description, and one of ordinary skill in the art can easily understand the fact that the manner and details can be changed into various kinds without departing from the spirit and scope of the present invention. form. Therefore, the present invention should not be construed as being limited to the contents described in the embodiments shown below.

 Embodiment 1    <Structure of display device>  

Fig. 1 is a block diagram showing the structure of a display device. The display device 10 includes a source driver IC 31, a gate driver 20, a gate driver 22, a display portion 14, and a display portion 18.

The display unit 14 includes a liquid crystal element LC of a reflective display element and a light-emitting element EL of the light-emitting display element. The display unit 14 has a region that is superposed on the display unit 18. Further, in the overlapped region, the light emitted from the light-emitting element EL having the display portion 18 passes through the display portion 14. The light-emitting element EL and the liquid crystal element LC are provided in each of the pixels (or each sub-pixel) included in the display unit 14 and the display unit 18.

In the present specification and the like, a pixel refers to, for example, one unit capable of controlling brightness. Thus, as an example, a pixel refers to a color unit and uses that one color unit to display brightness. Therefore, in the case of using a color display device composed of color units such as R (red), G (green), and B (blue), the minimum unit of the pixel is the pixel of R, the pixel of G, and the pixel of B. Pixel composition. In this case, each pixel of RGB is referred to as a sub-pixel, and sub-pixels of RGB are collectively referred to as a pixel.

The source driver IC 31 includes a source driver 24, a signal generating circuit 26, a signal generating circuit 28, a frame memory 30, a frame memory 32, a control circuit 34, and an interface 36.

The source driver IC 31 receives a signal (image material) or the like for displaying an image from the application processor 99. The application processor 99 has a function of converting image data into a predetermined format and outputting it to the interface 36. The interface 36 is a circuit that is converted into a signal suitable for LVDS (Low Voltage Differential Signaling), MIPI (Mobile Industry Processor Interface), or the like.

The frame memory 30 and the frame memory 32 are circuits for temporarily storing image data of one frame input from the control circuit 34 via the interface 36. Fig. 1 shows a plurality of frame memories, but may also be a frame memory. In addition, line memory can also be used. The memory unit of the frame memory can use SRAM (Static RAM: Static Random Access Memory) or DRAM (Dynamic RAM: Dynamic Random Access Memory). By using a transistor having a small off-state current as a transistor of a DRAM, the update frequency can be reduced, which is preferable in achieving low power consumption.

The signal generating circuit 26 is a circuit that generates a signal for controlling a scan signal output from the gate driver 20. The signal generating circuit 28 is a circuit that generates a signal for controlling the scanning signal output from the gate driver 22. The signal generating circuit 26 and the signal generating circuit 28 output signals such as the clock signal CLK, the pulse width control signal PWC, the reset signal RES, and the start pulse to the gate driver 20 and the gate driver 22, and control the output of the scan signal.

For example, in the signal generating circuit 26 or the signal generating circuit 28, the scan signal output from the gate driver 20 or the gate driver 22 can be set by fixing the pulse width control signal PWC and the pulse signal CLK to the L level. The period of the L level can reduce the update rate of the image data written to the pixel. Further, in the gate driver 20 or the gate driver 22, the signal for setting the pulse signal output as the scan signal to the L level also means "stopping the output of the scan signal".

Further, in the signal generating circuit 26 or the signal generating circuit 28, by fixing the pulse width control signal PWC corresponding to an arbitrary line to the L level, it is possible to set an arbitrary line output from the gate driver 20 or the gate driver 22. While the scan signal is set to the L level, the scan signal can be output to a part of the line, and the scan signal output to the other line can be set to the L level signal. Further, in the gate driver 20 or the gate driver 22, a signal in which a pulse signal output as an arbitrary signal to a scanning signal is set to an L level is also referred to as "output of a scanning signal that stops outputting to a pixel of an arbitrary line".

The source driver 24 is a circuit for supplying a voltage (video voltage) based on image data to the source lines of the respective columns. The gate driver 20 is a circuit for supplying a liquid crystal element LC in a pixel of the selected row to a scanning signal based on a gray scale of a video voltage applied to the source line. The gate driver 22 is a circuit for supplying a scanning signal based on the gray scale of the video voltage applied to the source line to the light-emitting element EL in the pixels of the selected row. The display unit 14 can display an image by controlling the gray scale of the liquid crystal element LC. Further, by controlling the gray scale of the light-emitting element EL, the display portion 18 can display an image.

In the display device 10 shown in FIG. 1, the display unit 14 and the display unit 14 in the display unit 18 can display only images. Since the liquid crystal element LC of the reflective display element is used in the display unit 14, external light can be used as a light source when displaying an image. When external light is used, power consumption of the display device 10 can be suppressed by displaying an image only on the display unit 14. Further, by using the light-emitting element EL of the light-emitting display element in the display unit 18, it is possible to display an image without using external light. Thereby, by displaying the image only on the display unit 14 of the display unit 14 and the display unit 18, the display quality of the image can be improved even if the intensity of the external light is low. That is to say, high display quality can be ensured even if the display device 10 is used.

Further, in the display device 10 according to an embodiment of the present invention, it is also possible to display an image using both the display unit 14 and the display unit 18. By adopting the above configuration, the number of gray scales of the image that can be displayed on the display device 10 can be increased. Alternatively, the range of the color gamut of the image that can be displayed on the display device 10 can be expanded.

Further, in the display device 10 according to the embodiment of the present invention, when the image is displayed using both the display portion 14 and the display portion 18, the signal generating circuit 28 has the following structure corresponding to the displayed image: the gate driver 22 The structure of the signal that stops the output of the scan signal for writing the video voltage to the pixel in any row is output. Thereby, it is possible to suppress the light emission of the light-emitting element EL in the pixel which does not require updating of the material when the intensity of the external light is low. In other words, when the intensity of the external light is low, the light-emitting element EL can be illuminated only in the area where the data needs to be updated while improving the display quality of the image. Thereby, it is possible to realize a display device which is low in power consumption and excellent in convenience.

Further, in the display device 10 according to an embodiment of the present invention, when the image is displayed using both the display portion 14 and the display portion 18, the signal generating circuit 26 corresponds to the displayed image in the following configuration: the gate driver 22 The structure of the signal that stops the output of the scan signal for writing the video voltage to the pixel in all the lines is output. Thereby, when the intensity of the external light is low, the display of the liquid crystal element LC in the pixel which does not require updating of the material can be displayed intermittently, that is, at a low update rate. Thereby, it is possible to realize a display device which is low in power consumption and excellent in convenience.

Note that the above information refers to data displayed on each display portion of the pixel. That is, it corresponds to the image data input to each display unit. Further, the data update means updating the data displayed on each display unit of the pixel. In other words, it corresponds to the rewriting (update) frequency of the video material input to each display unit.

In addition, the structure of the display device is not limited to the structure of the display device 10 shown in FIG. For example, as in the display device 10A shown in FIG. 2A, the signal generating circuit 26, the signal generating circuit 28, the frame memory 30, and the frame memory 32 in the source driver IC 31A may be omitted. In this configuration, the source driver IC 31A includes a source driver 24 and an interface 36.

In the source driver IC 31A shown in FIG. 2A, an external timing controller or the like has functions of the signal generation circuit 26, the signal generation circuit 28, the frame memory 30, the frame memory 32, and the like. Further, a signal for control is transmitted to the source driver 24 and the gate driver (not shown) via the interface 36. In order to communicate with an external timing controller at a high speed, the interface 36 preferably selects DVI (Digital Visual Interface), EPI (External Presentation Interface), and SPI (Serial Peripheral Interface). Column peripheral interface) and so on. By adopting the above configuration, the size of the source driver IC 31A can be reduced, which is suitable for the case where the display device is mounted to a small electronic device.

Further, as in the display device 10A shown in FIG. 2B, a configuration in which a plurality of source driver ICs 31A are used may be employed. By adopting this configuration, the miniaturization of the source driver IC 31A can be achieved, and this is suitable for the case where the display device is mounted to a large electronic device. In addition, the configuration of the plurality of source driver ICs 31A may be controlled by the external timing controller 35.

 <Structure of display unit>  

3 is a block diagram showing the structure of a display portion of a display device. The display unit 13 corresponds to a region in which the display unit 14 and the display unit 18 shown in FIG. 1 are combined. The display section 13 includes a plurality of pixels 19. The pixel 19 includes a pixel circuit 15 and a pixel circuit 17. In addition, FIG. 3 shows the source driver 24, the gate driver 20, and the gate driver 22 shown in FIG.

The pixel circuit 15 is a circuit that controls the gray scale of the liquid crystal element LC (not shown) by being written into a video voltage. The pixel circuit 15 includes a transistor and a capacitor. The video voltage written to the pixel circuit 15 is supplied by the source line SL _LC . A scan signal for writing a video voltage to the pixel circuit 15 is supplied from the gate driver 20 via the gate line GL _LC .

The pixel circuit 17 is a circuit that controls the gray scale of the light-emitting element EL (not shown) by being written into a video voltage. The pixel circuit 17 includes a transistor and a capacitor. The video voltage written to the pixel circuit 17 is supplied by the source line SL _EL . A scan signal for writing a video voltage to the pixel circuit 17 is supplied from the gate driver 22 via the gate line GL _EL .

Further, in the drawing or the like, the source line SL _EL [1] and the source line SL _LC [1] are shown as the source line SL _EL , the source line SL _LC , the gate line GL _{LC ,} and the gate line GL _{EL .} ], the gate line GL _LC [1] and the gate line GL _EL [1], these wirings represent the first row or the first column. Further, when the pixel 19 is represented by m rows and n columns (m and n are natural numbers), the pixels included in the display portion 13 are connected to any one of the source lines SL _EL [1] to [n], the source. Any one of the lines SL _LC [1] to [n], any of the gate lines GL _LC [1] to [m], and any one of the gate lines GL _EL [1] to [m].

Next, the pixel 19 will be described. FIG. 4A is an example of a circuit diagram of the pixel 19. The pixel 19 includes a pixel circuit 15, a pixel circuit 17, a liquid crystal element LC, and a light-emitting element EL.

In FIG. 4A, the pixel circuit 15 includes a transistor M1 and a capacitor Cs _LC . The pixel circuit 17 includes transistors M2, M3 and a capacitor Cs _EL . As shown in FIG. 4A, the elements included in the pixel 19 are connected to the gate line GL _LC [1], the gate line GL _EL [1], the signal line SL _LC [1], the signal line SL _EL [1], and the capacitor. Line L _CS , current supply line L _{ano ,} and common potential line L _cas .

Further, the capacitor Cs _EL is provided to store the gray scale voltage for driving the light emitting element EL in the gate of the transistor M3. By adopting this configuration, the gray scale voltage for driving the light emitting element EL can be more surely maintained.

In addition, the transistor M3 is a transistor having a back gate. By adopting this structure, the amount of current flowing through the transistor can be increased. In addition, the voltage applied to the back gate can also be supplied from other wiring. By adopting this structure, the threshold voltage of the transistor can be controlled.

The gray scale voltage for driving the liquid crystal element LC is supplied to the capacitor Cs _LC by controlling the on state of the transistor M1. The gray scale voltage for driving the light emitting element EL is supplied to the gate of the transistor M3 by controlling the conduction state of the transistor M2. The transistor M3 causes a current to flow between the current supply line _Lan and the common potential line L _cas according to the gate voltage to drive the light-emitting element EL.

The transistors M1 to M3 can use an n-channel type transistor. Instead of the n-channel type transistor, a p-channel type transistor can also be used by changing the magnitude relationship of the voltages of the respective wirings. The semiconductor material of the transistors M1 to M3 may use germanium. As the ruthenium, a single crystal germanium, a polycrystalline germanium, a microcrystalline germanium or an amorphous germanium can be appropriately selected.

Alternatively, the semiconductor material of the transistors M1 to M3 may use a metal oxide. As the metal oxide, a metal oxide containing indium or a metal oxide containing indium, gallium, and zinc can be used.

Further, the transistors M1 to M3 of the pixel 19 can be fabricated using various types of transistors such as a bottom gate type transistor or a top gate type transistor.

In addition, the transistors M1 to M3 of the pixel 19 may also be a transistor having a back gate. The voltage supplied to the back gate can also be supplied from other wirings different from the gate line GL _LC [j] or the gate line GL _EL [j]. Alternatively, only the transistor M3 may have a back gate. By adopting this structure, it is possible to control the threshold voltage of the transistor or to increase the amount of current flowing through the transistor.

In addition, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) : Axisymmetric array of microcells), OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, and AFLC (Anti Ferroelectric Liquid Crystal) mode The method drives the liquid crystal element LC. Alternatively, the liquid crystal element can be driven by a vertical alignment (VA) mode such as MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ECB (Electrically Controlledled mode). Birefringence: electronically controlled birefringence mode, CPA (Continuous Pinwheel Alignment) mode, ASV (Advanced Super-View) mode.

As the liquid crystal material of the liquid crystal element, for example, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. Alternatively, a liquid crystal material exhibiting a cholesterol phase, a smectic phase, a cubic phase, a chiral nematic phase, and an isotropic phase may be used. Alternatively, a liquid crystal material exhibiting a blue phase can be used.

As the light-emitting element EL, an EL element such as an organic electroluminescence element or an inorganic electroluminescence element, a light-emitting diode, or the like can be used.

The EL element can use a laminate in which white light is emitted to be laminated. Specifically, a layer laminated with a light-emitting organic compound containing a fluorescent material emitting blue light and a layer using a material other than a fluorescent material emitting green light and red light or a fluorescent light containing yellow-emitting light may be used. A laminate of layers of material other than the material.

Next, a schematic diagram of the layer structure of the pixel 19 will be described. In the pixel 19 shown in FIG. 4B, the arrangement of the pixel circuit 15, the pixel circuit 17, the liquid crystal element LC, and the light-emitting element EL is shown. The liquid crystal element LC shown in FIG. 4B has an opening 21. This opening 21 represents an opening provided in the reflective electrode. The light-emitting element EL shown in FIG. 4B is provided to overlap the opening 21 of the liquid crystal element LC. The pixel circuit 15 and the pixel circuit 17 shown in FIG. 4B are disposed between a layer in which the liquid crystal element LC is provided and a layer in which the light emitting element EL is provided. In addition, the pixel circuit 15 and the pixel circuit 17 shown in FIG. 4B may be disposed in different layers.

By employing the structure shown in FIG. 4B, the gray scale of the pixel 19 can be controlled by controlling the intensity of the reflected light 12 of the liquid crystal element LC and the intensity of the light 16 emitted by the light emitting element EL of the opening 21. Further, the direction in which the reflected light 12 is emitted and the direction in which the light 16 emitted from the light-emitting element EL is emitted become the display surface of the display device 10.

In the configuration shown in FIG. 4B, a circuit for driving a pixel such as the pixel circuit 15 and the pixel circuit 17 can be disposed under the reflective electrode included in the liquid crystal element LC. Thereby, it is possible to suppress a decrease in the aperture ratio due to an increase in the pixel circuit 17 for driving the light emitting element EL.

Further, the structure shown in FIG. 4B includes a pixel circuit 15 capable of controlling the liquid crystal element LC by the pixel 19 and a pixel circuit 17 capable of controlling the light-emitting element EL by the pixel 19. That is, the gray scale display of the liquid crystal element LC and the light emitting element EL can be controlled by the pixels 19, respectively. In the above configuration, unlike the control of the backlight that causes all of the plurality of pixels to emit light, the light emission of the light-emitting element EL corresponding to the displayed image can be controlled in the minimum unit of the pixel, so that the remaining light emission can be suppressed. Thereby, the display device including the pixel shown in FIG. 4B can achieve low power consumption.

In addition, the pixel circuit 15 and the pixel circuit 17 each include a transistor for controlling gray scale display. As the transistor, a transistor having a metal oxide in a channel formation region is preferably used. A metal oxide is used as an oxide semiconductor, and an off-state current of an OS transistor having the oxide semiconductor in a channel formation region is extremely small. Thereby, when a still image is displayed using the display device, the electric charge corresponding to the video voltage can be held for a long time in the pixel circuit. By adopting a configuration in which the charge corresponding to the video voltage is held for a long time in the pixel circuit, the rewriting frequency (update rate) of the pixel can be reduced (for example, the frame frequency is 30 Hz or less), so that power consumption can be reduced.

 <Working example of display device>  

Next, the operation of the display device shown in FIG. 1 will be described with respect to the operation of the electronic device including the display device. FIG. 5A shows an electronic device 40 including the display device shown in FIG. 1.

The electronic device 40 shown in FIG. 5A is a portable electronic device having a display unit, and the display device is provided in the casing 42, and the photo sensor 44 and the power button 46 are also shown as other components. The background portion 48 and the timepiece display portion 50 are shown on the display portion of the display device. The timepiece display unit 50 shows components such as a dial, a long needle, a short needle, and a second hand.

When the gate driver output scan signal is disposed in the long axis direction of the casing 42, the area where only the pixel of the background portion 48 is connected to the gate line can be set as shown by the still image display portions 47, 51 of FIG. 5A. The area where you do not need to update the data. On the other hand, an area in which the pixel on which the timepiece display unit 50 is displayed is connected to the gate line can be set as an area in which the data needs to be updated as shown by the moving image display unit 49 of FIG. 5A.

FIG. 5B is a block diagram showing the display unit 13 including the moving image display unit 49 and the still image display units 47 and 51 of FIG. 5A and the drive circuit in the periphery. The display portion 13 shown in FIG. 5B includes a plurality of pixels 19. The pixel 19 includes a pixel circuit 15 and a pixel circuit 17. In addition, FIG. 5A and FIG. 5B show the source driver 24, the gate driver 20, and the gate driver 22.

In addition, as in FIG. 3, FIG. 5B shows the source line SL _EL [1] and the source line SL _LC [1] of the first column, and the gate line GL _LC [1] of the first row and the gate line GL. _EL [1]. 5B shows the gate line GL _LC [2] and the gate line GL _EL [2] and the jth row in the second row (j is 3 or more and (m-1) or less (m is 5 or more in nature) The gate line GL _LC [j] of the number) and the gate line GL _EL [j], the gate line GL _LC [j+1] of the j+1th row, and the gate line GL _EL [j+ 1], the gate line GL _LC [m-1] of the m-1th row and the gate line GL _EL [m-1], the gate line GL _LC [m] of the mth row, and the gate line GL _EL [ m].

In addition, the gate line GL _LC [1] and the gate line GL _EL [1] of the first row and the gate line GL _LC [2] of the second row and the gate line GL _EL [2] of the first row shown in FIG. 5B A gate line for supplying a scan signal is supplied to the pixels of the still image display portion 47 of FIG. 5A. In addition, the gate line GL _LC [j] and the gate line GL _EL [j] of the jth row shown in FIG. 5B and the gate line GL _LC [j+1] of the j+1th row and the gate line GL _EL [j+1] is a gate line that supplies a scan signal to the pixels of the motion picture display unit 49 of FIG. 5A. Further, FIG. 5B first gate line m-1 line GL _LC shown in [m-1] and the gate line GL _EL [m-1] and the m-th gate line GL _LC row [m] and gate The line GL _EL [m] is a gate line that supplies a scan signal to the pixels of the still image display portion 51 of FIG. 5A.

FIG. 6 again shows the electronic device 40 shown in FIG. 5A. The motion picture display unit 49 in the electronic device 40 may be an area in which data needs to be updated. The still image display units 47 and 51 in the electronic device 40 may be areas where the data need not be updated as described above. As a result, in the still image display units 47 and 51, the display using the liquid crystal element LC is intermittently updated, that is, when the update rate is reduced. On the other hand, in the moving image display unit 49, display using the light emission of the light-emitting element EL is performed in accordance with the display using the liquid crystal element LC. In other words, as shown in FIG. 6, the still image display units 47 and 51 display by the reflected light 12 using the liquid crystal element LC, and the moving image display unit 49 uses the reflected light 12 of the liquid crystal element LC and the light-emitting element. The light 16 of the EL is displayed.

In Figs. 7A and 7B, the operation of the display device of Fig. 1 when the operation shown in Fig. 6 is performed will be described using the block diagram shown in Fig. 5B.

In FIG. 7A, the dotted arrow 23 is an arrow that visualizes the scanning direction in which the gate driver 20 sequentially outputs the scanning signal. In addition, in FIG. 7A, the dotted arrow 25 is an arrow which visualizes the scanning direction which the gate driver 22 sequentially outputs a scanning signal.

The display device according to an embodiment of the present invention operates as follows: as shown in FIG. 7A, in the operation shown in FIG. 6, in the area where the material needs to be updated, the video written to the light-emitting element EL is performed. The scan signal is output in a manner that the voltage is updated. That is, when the gate driver 20 sequentially outputs the scan signals as indicated by the broken line arrow 23, the gate lines GL _EL [1] and the gate lines of the second row are not in the gate driver 22. GL _EL [2] outputs a scan signal, and outputs a scan signal from the gate line GL _EL [j] of the jth row and the gate line GL _EL [j+1] of the j+1th row, not from the m-1th line The gate line GL _EL [m-1] and the gate line GL _EL [m] of the mth row operate in a manner of outputting a scan signal. The switching of the scanning signal is realized by switching the respective control signals generated by the signal generating circuit 26 shown in FIG. 1 in such a manner that the scanning signal is output from the gate driver 22.

Thereby, when the intensity of the external light is low, it is possible to suppress the light emission of the light-emitting element EL in the pixel which does not require updating of the material. That is, the light emission of the light-emitting element EL is performed only in the area where the data update is required. Thereby, it is possible to realize a display device which is low in power consumption and excellent in convenience.

In addition, FIG. 7B is a view for explaining the operation of the display device of one embodiment of the present invention which is different from FIG. 7A. As shown in FIG. 7A, the operation shown in FIG. 7B is such that the interval at which the scan signal is outputted by the gate driver 20 is large and the display of the scan signal is intermittently updated, so that the gate driver 20 is periodically stopped. The output of the scan signal. In FIG. 7B, the periodic stop of the output of the scan signal is shown because the dotted arrow 23 shown in FIG. 7A is not shown. In the state where the output of the scan signal by the gate driver 20 is stopped, the gate line GL _EL [1] of the first row and the gate line GL _{EL of the} second row are not in the gate driver 22 The output scan signal outputs a scan signal from the gate line GL _EL [j] of the jth row and the gate line GL _EL [j+1] of the j+1th row, not from the gate line of the m-1th row GL _EL [m-1], the m-th gate line GL _EL [m] outputs a scan signal to operate. The switching of the scanning signal is realized by switching the respective control signals generated by the signal generating circuit 26 shown in FIG. 1 in such a manner that the scanning signal is output from the gate driver 22. Further, the stop of the output of the scan signal is realized by each control signal generated by the signal generating circuit 28 shown in Fig. 1 .

Thereby, when the intensity of the external light is low, it is possible to suppress the light emission of the light-emitting element EL in the pixel which does not require updating of the material, and intermittently, that is, to perform the liquid crystal element LC in the pixel which does not require updating of the material at a low update rate. The display of the update is displayed. Thereby, it is possible to realize a display device which is low in power consumption and excellent in convenience.

Further, in the display device 10 according to an embodiment of the present invention, when the image is displayed using both the display portion 14 and the display portion 18, the signal generating circuit 26 corresponds to the displayed image in the following configuration: the gate driver 22 The structure of the signal that stops the output of the scan signal for writing the video voltage to the pixel in all the lines is output. Thereby, when the intensity of the external light is low, the display of the liquid crystal element LC in the pixel which does not require updating of the material is intermittently displayed, that is, at a low update rate. Thereby, it is possible to realize a display device which is low in power consumption and excellent in convenience.

In addition, in the description of FIG. 6 to FIG. 8B, as an example of the display of the display unit, a scanning signal for causing a pixel circuit having display elements corresponding to the respective areas between the moving image display unit and the still image display unit will be described. The output differs in structure, but other structures can be used.

For example, as shown in FIG. 8A, the dial 53 of the timepiece is displayed on the display unit 14 that drives the liquid crystal element LC to display at a low update rate, and the long needle, the short needle, and the second hand 52 are displayed in the display unit 18 that drives the light-emitting element EL to display. . Further, the update rate of the display unit 18 that drives the light-emitting element EL to display is one time per second, that is, 1 Hz or less. Further, the update rate of the display unit 14 for driving the liquid crystal element LC to display is preferably smaller than that of the display unit 18.

As another example, as shown in Fig. 8B, the map 55 is displayed on the display unit 14 that drives the liquid crystal element LC to display at a low update rate, and the image 54 is displayed on the display unit 14 that drives the light-emitting element EL to display. Further, the update rate of the display unit 18 that drives the light-emitting element EL to display is one time per second, that is, 1 Hz or less. Further, the update rate of the display unit 14 for driving the liquid crystal element LC to display is preferably smaller than that of the display unit 18.

 <Display mode of display device>  

The display mode for reducing the update rate explained in the operation example of the above display device will be described with reference to FIGS. 9A to 9D. In addition, switching of the display mode using the power button 46 illustrated in FIG. 5A will be described using FIG. 10 to FIG. 12B. In addition, switching of the display mode of the photo sensor 44 explained using FIG. 5A will be described using FIGS. 13A to 13E.

Hereinafter, the display mode in which the update rate is reduced as described in the operation example of the display device will be referred to as an idle stop (IDS) drive mode. Further, as a display mode that the display device 10 may perform, a normal drive mode (Normal mode) and an idle stop (IDS) drive mode that operate at a normal frame frequency will be described.

Further, the IDS drive is a drive method for stopping the rewriting of the image data after the execution of the writing process of the image data. By extending the interval from the writing of the image data to the next writing of the image data, the power consumption required for writing the image data during the interval can be reduced.

An example of the above-described normal drive mode and IDS drive will be described with reference to an example in FIGS. 9A to 9D. Further, although the normal driving mode and the IDS driving are applied to the liquid crystal element LC and the pixel circuit 15 in Figs. 9A to 9D, the normal driving mode and the IDS driving may be applied to the light emitting element EL and the pixel circuit 17.

FIG. 9A shows a circuit diagram of a pixel composed of the liquid crystal element LC and the pixel circuit 15. FIG. 9A shows a transistor M1, a capacitor Cs _LC, and a liquid crystal element LC connected to the source line SL and the gate line GL. The source line SL and the gate line GL correspond to the source line SL _LC and the gate line GL _LC shown in FIG. 3 and the like.

FIG. 9B is a timing chart showing waveforms of signals supplied to the source line SL and the gate line GL in the normal driving mode, respectively. It operates at the normal frame frequency (for example, 60 Hz) in the normal drive mode. During one frame period T ₁ to T ₃ to represent, a scan signal is supplied to the gate line and the source line is written into the video voltage D ₁ during the operation of the pixel in each block of FIG. This operation is the same when the same video voltage D ₁ is written in the period T ₁ to T ₃ or when a different video voltage is written.

On the other hand, FIG. 9C is a timing chart showing waveforms of signals supplied to the source line SL and the gate line GL driven by the IDS, respectively. It operates at a low frame frequency (eg 1 Hz) in the IDS drive. One frame period is represented by a period T ₁ in which a period in which a video voltage is written is expressed as a period T _W , and a period in which a video voltage is held is represented as a period T _RET . In the IDS driving, a scan signal is supplied to the gate line during the period T _W , the video voltage D _{1 of the} source line is written to the pixel, and the gate line is fixed to the L level voltage during the period T _RET . The transistor M1 is rendered non-conductive and the video voltage D ₁ temporarily written is held in the pixel.

Fig. 9D shows a state transition diagram when the above-described normal driving mode and IDS driving are switched. State C1 represents the IDS drive mode and state C2 represents the normal drive mode.

The states C1 and C2 differ depending on the display content. For example, when the display of the timepiece shown in FIGS. 5A and 5B is performed, it is effective to perform IDS driving in both of the liquid crystal element LC and the light-emitting element EL. Further, for example, when the liquid crystal element LC and the light-emitting element EL are driven to display a moving image on the entire screen, it is effective to perform the normal driving mode.

In addition, switching of the display mode of the display device in the electronic device 40 using the power button 46 illustrated in FIG. 5A will be described using FIGS. 10 to 12B.

In the electronic device 40, when the power source is turned on, it is determined whether or not the standby mode (sleep mode) is determined (step S11). The standby mode refers to a state in which the power of the electronic device is turned on and the display on the display unit is not performed.

In the standby mode, a determination is made as to whether or not the power button 46 is pressed (first time) (step S12). Next, a determination is made as to whether or not the power button 46 is pressed (second time) (step S13). That is, switching between the display mode A or the display mode B is performed depending on whether or not the power button 46 is continuously pressed twice.

11A and 11B are flowcharts for explaining the operation of the display mode A and the display mode B when the small electronic device illustrated in Fig. 2A is assumed.

Fig. 11A is a flow chart showing the operation in mode A, that is, when the power button 46 is pressed twice. The display mode A is a mode in which normal display is performed.

First, when the power button 46 is pressed twice, in order to perform normal display, the setting data is transmitted from the application processor to the source driver IC via the SPI or the like (step S21). Next, setting of a signal generating circuit for driving the source driver and the gate driver is performed in a normal driving mode (step S22). Next, the video data of the motion image is transmitted to the source driver IC via MIPI or the like (step S23). Next, various control signals and video voltages for driving the source driver and the gate driver are output from the signal generating circuit (step S24). Then, a scan signal is output from the gate driver, and a video voltage is output from the source driver for normal display (step S25).

Fig. 11B is a flow chart showing the operation in mode B, that is, when the power button 46 is pressed once. The display mode B is a mode in which the timepiece display is performed.

First, when the power button 46 is pressed once, in order to perform normal display, the setting data is transmitted from the application processor to the source driver IC via the SPI or the like (step S31). Next, the setting of the signal generation circuit for driving the source driver and the gate driver is performed in the IDS driving mode (step S32). Next, a still image, that is, image data during one frame period, is transmitted to the source driver IC via MIPI or the like (step S33). Next, the image data during one frame period is stored in the frame memory (step S34). Next, various control signals and video voltages for driving the source driver and the gate driver are output from the signal generating circuit (step S35). Then, a scan signal is output from the gate driver, and a video voltage is output from the source driver for clock display (step S36).

By judging the number of times the power button 46 is pressed, the display mode can be switched, and the power consumption when the watch is displayed is reduced.

12A and 12B are flowcharts for explaining the operation of the display mode A and the display mode B when the large-sized electronic device illustrated in FIG. 2B is assumed.

Fig. 12A is a flow chart showing the operation in mode A, that is, when the power button 46 is pressed twice. The display mode A is a mode in which normal display is performed.

First, when the power button 46 is pressed twice, the setting data is transmitted from the timing controller to the source driver IC for the normal display (step S41). Next, the signal generation circuit is set in such a manner as to perform the normal drive mode (step S42). Next, the image data of the motion image is transmitted to the source driver IC via the EPI or the like (step S43). Next, various control signals and video voltages for driving the gate driver are output from the timing controller and the source driver (step S44). Then, the normal display is performed (step S45).

Fig. 12B is a flow chart showing the operation in mode B, that is, when the power button 46 is pressed once. The display mode B is a mode in which the timepiece display is performed.

First, when the power button 46 is pressed once, in order to perform normal display, the setting data is transmitted from the application processor to the source driver IC via the SPI or the like (step S51). Next, the source driver and the gate driver are set such that the IDS driving mode is performed (step S52). Next, the image data synchronized with the update rate is intermittently transmitted to the source driver IC via the EPI or the like (step S53). Next, various control signals and video voltages for driving the gate driver are output from the timing controller and the source driver (step S54). Then, the timepiece display is performed (step S55).

By judging the number of times the power button 46 is pressed, the display mode can be switched, and the power consumption when the watch is displayed can be reduced.

In addition, the switching of the display mode of the display device in the electronic device 40 using the photo sensor 44 illustrated in FIG. 5A will be described using FIGS. 13A to 13E.

The electronic device 40 can switch the operating mode according to a signal including the illuminance information obtained by the photo sensor 44. Photosensor 44 and application processor 99 are shown in the block diagram of FIG. 13A.

In FIG. 13A, the photo sensor 44 has, for example, a function of generating a signal S _ILL corresponding to illuminance. The application processor 99 has a function of switching the display mode in accordance with the signal S _ILL .

In addition, FIGS. 13B to 13D are schematic views for explaining pixels of a display mode that the display device may adopt according to illuminance. 13B to 13D, similarly to FIG. 4B, the pixel circuit 15, the pixel circuit 17, the liquid crystal element LC, the light-emitting element EL, the opening 21, and the reflected light 12 reflected by the reflective electrode of the liquid crystal element LC are shown. The light 16 emitted from the light-emitting element EL emitted from the opening 21.

The display mode that can be taken as the display device 10 will be described with reference to the reflective display mode (R mode), the reflective + light-emitting display mode (ER mode), and the light-emitting display mode (E mode) shown in FIGS. 13B to 13D.

The reflective display mode refers to a display mode in which the gray scale is controlled by adjusting the intensity of the reflected light by the liquid crystal element of the driving pixel. Specifically, as shown in the schematic diagram of the pixel shown in FIG. 13B, the intensity of the reflected light 12 is adjusted by the reflective electrode included in the liquid crystal element LC to control the gray scale.

The ER mode refers to a display mode in which the gray scale is controlled by both the driving of the liquid crystal element and the driving of the light emitting element to adjust the intensity of the reflected light and the light of the light emitting element. Specifically, as shown in the schematic diagram of the pixel shown in FIG. 13C, the intensity of the reflected light 12 is adjusted by the reflective electrode of the liquid crystal element LC, and the intensity of the light 16 emitted from the opening 21 by the light-emitting element EL is adjusted to control the gray scale. . By applying the operation of the display device shown in FIG. 6 described above to the operation in the reflection + illumination display mode of FIG. 13C, it is possible to achieve an improvement in display quality and a reduction in power consumption.

Note that in the present specification, the display of the combined light-emitting element EL (first display element) and the liquid crystal element LC (second display element) such as the above-described reflection + light-emitting display mode (ER mode) is referred to as a hybrid display method. In addition, the hybrid display method refers to a method of displaying a plurality of lights in the same pixel or the same sub-pixel and displaying characters and/or images. Further, the hybrid display is an aggregate in which a plurality of lights are displayed on the same pixel or the same sub-pixel included in the display unit, and characters and/or images are displayed.

As an example of the hybrid display method, there is a method of displaying the first light and the second light at different display timings in the same pixel or the same sub-pixel. At this time, in the same pixel or the same sub-pixel, the same color tone (any one of red, green, and blue or any of cyan, magenta, and yellow) may be simultaneously displayed. The first light and the second light display characters and/or images on the display unit.

Further, as an example of the hybrid display method, there is a method of displaying reflected light and self-luminous light in the same pixel or the same sub-pixel. In the same pixel or the same sub-pixel, reflected light of the same color tone and self-luminescence (for example, light emission of an organic EL, light emission of a light-emitting diode, or the like) can be simultaneously displayed.

Further, the hybrid display is an aggregate having a plurality of display elements in the same pixel or the same sub-pixel and displaying each of the plurality of display elements in the same period. In addition, the hybrid display has a plurality of display elements and active elements for driving the display elements in the same pixel or the same sub-pixel. As the active element, there are switches, transistors, thin film transistors, and the like. Since each of the plurality of display elements is connected to the active element, the display of each of the plurality of display elements can be independently controlled.

The light mode (E mode) is a display mode in which the light-emitting element is driven to adjust the intensity of light to control the gray scale. Specifically, as in the schematic diagram of the pixel shown in FIG. 13D, the light-emitting element EL adjusts the intensity of the light 16 emitted from the opening 21 to control the gray scale. By applying the operation of the display device shown in Fig. 6 described above to the operation in the light-emitting display mode of Fig. 13D, power consumption can be reduced.

Fig. 13E shows a state transition diagram of the above three modes (reflective display mode, reflective + light emitting display mode, and light emitting display mode). State C3 shows a reflective display mode, state C4 shows a reflective + illuminated display mode, and state C5 shows a lighted display mode.

As shown in FIG. 13E, a display mode in any of the states C3 to C5 can be taken according to the illuminance. For example, in the case where the illuminance such as outdoor is high, the state C3 is preferable. Further, when the illuminance is low when moving from the outdoor to the indoor, the state transitions from the state C3 to the state C5. Further, even when the indoor illuminance is high and the gray scale display using the reflected light can be performed, the state transitions from the state C5 to the state C4.

As described above, by adopting a configuration in which the display mode is switched in accordance with the illuminance, the frequency of the gray scale display using the intensity of the light of the light-emitting element can be reduced, and the power consumption of the light-emitting element is large. Thereby, the power consumption of the display device can be reduced.

 <Structural example of gate driver>  

Next, a specific example of a shift register which can be used for the gate drivers 20 and 22 described above with reference to FIG. 1 and the like will be described.

Fig. 14A shows an example of a circuit configuration of a shift register which can output m+2 stage pulses. The shift register of FIG. 14A can output pulses to the output terminals OUT_1 to OUT_m+2 by the start pulse SP, the clock signals CLK1 to CLK4, the pulse width control signals PWC1 to PWC4, and the reset signal RES from the outside. Although not shown, the reset signal RES, the control signal Φ, and the control signal ΦB are signals respectively supplied to different wirings. Further, the output terminals OUT_1 to OUT_m correspond to the above-described gate lines GL _EL [1] to [m], GL _LC [1] to [m], and the pulses correspond to scan signals.

The circuit SR is supplied with the respective signals shown in Fig. 14B. The circuit SR _DUM is supplied with the signals shown in Fig. 14C. The clock signals CLK1 to CLK4 supplied to the circuit SR and the circuit SR _DUM and the pulse width control signals PWC1 to PWC4 differ depending on the stages. LIN is a signal supplied from the upper side of the shift direction of the shift register. RIN is a signal supplied from the lower side of the shift register of the shift register. SROUT is the signal supplied to the next stage shift register. OUT is the signal supplied to the gate line that becomes the load.

Fig. 15A shows an example of the circuit configuration of the circuit SR. The circuit 700 shown in FIG. 15A includes a transistor 701 to a transistor 709. The circuit 710 shown in FIG. 15A includes a transistor 711 to a transistor 713. The circuit 720 shown in FIG. 15A includes a transistor 721 to a transistor 723. In the drawings, the transistors 701 to 709, the transistors 711 to 713, and the transistors 721 to 723 are single gate transistors, but may also be double gate transistors having back gates. Similarly, Fig. 15B shows an example of the circuit configuration of the circuit SR _DUM .

16 is a timing chart showing waveforms of the pulse width control signals PWC1 to PWC4, the clock signals CLK1 to CLK4, the start pulse SP, and the output terminals OUT_1 to OUT_m. In the timing chart shown in Fig. 16, the upper half period corresponds to the period P1 in which the scanning signals are sequentially output to the respective lines indicated by the broken line arrow 23 shown in Fig. 7A. Further, the lower half period corresponds to the period P2 in which the scanning signal is output only to the predetermined line indicated by the broken line arrow 25 shown in FIG. 7A.

In the period P1, pulses are sequentially output in accordance with the start pulse SP, the pulse width control signals PWC1 to PWC4, and the clock signals CLK1 to CLK4.

On the other hand, in the second period P2, in order to output a pulse only to a predetermined line, the pulse width control signals PWC1 to PWC4 are fixed to the L level for a certain period of time. For example, in FIG. 16, pulses are output to the output terminal OUT_1, the output terminal OUT_2, the output terminals OUT_m-1, and OUT_m, and the output terminals OUT_j and OUT_j+1 are not output. In this case, the trigger operation using the pulse width control signals PWC1 to PWC4 is performed in the period Pa and the period Pc in the same manner as the period P1, and the pulse width control signals PWC1 to PWC4 are fixed to the L level during the period Pb. . By fixing the pulse width control signals PWC1 to PWC4 to the L level, the output terminals OUT_j and OUT_j+1 become the L level, and therefore no pulse is output.

As described above, the output of the scan signal for the prescribed line can be stopped without dividing the gate driver by the area.

Note that a part or the whole of the present embodiment can be freely combined with a part or the whole of other embodiments.

 Embodiment 2  

In the present embodiment, a configuration example of a display device using a reflective display element and an illuminating display element described in the first embodiment will be described. In the present embodiment, a configuration example of a display device will be described by way of an example in which a liquid crystal element is used as a reflective display element and a light-emitting element using an EL material is used as an emission-type display element.

FIG. 17A shows a cross-sectional structure of a display device 406 according to an embodiment of the present invention as an example. The display device 406 shown in FIG. 17A includes a light-emitting element 203, a liquid crystal element 204, a transistor 205 having a function of controlling supply of current to the light-emitting element 203, and a transistor 206 having a function of controlling supply of a voltage to the liquid crystal element 204. . Further, the light-emitting element 203, the liquid crystal element 204, the transistor 205, and the transistor 206 are located between the substrate 201 and the substrate 202.

Further, in the display device 406, the liquid crystal element 204 includes a pixel electrode 207, a common electrode 208, and a liquid crystal layer 209. The pixel electrode 207 is electrically connected to the transistor 206. Further, the alignment of the liquid crystal layer 209 is controlled by the voltage applied between the pixel electrode 207 and the common electrode 208. In addition, in FIG. 17A, the pixel electrode 207 has a function of reflecting visible light and the common electrode 208 has a function of transmitting visible light, and light incident from the substrate 202 side is emitted by the pixel electrode 207 as indicated by a contour arrow, again. It is emitted from the side of the substrate 202.

Further, the light emitting element 203 is electrically connected to the transistor 205. Light emitted from the light emitting element 203 is emitted toward the side of the substrate 202. In addition, in FIG. 17A, the pixel electrode 207 has a function of reflecting visible light and the common electrode 208 has a function of transmitting visible light, and therefore, light emitted from the light-emitting element 203 passes through as shown by the outline arrow without overlapping with the pixel. The region of the electrode 207 and the region where the common electrode 208 is present are emitted from the substrate 202 side.

In the display device 406 shown in FIG. 17A, the transistor 205 and the transistor 206 are located in the same layer 210, and the layer 210 including the transistor 205 and the transistor 206 has a region between the liquid crystal element 204 and the light-emitting element 203. In addition, in the case where the semiconductor layer included in the transistor 205 and the semiconductor layer included in the transistor 206 are located on at least the same insulating surface, it can be said that the transistor 205 and the transistor 206 are included in the same layer 210.

By employing the above structure, the transistor 205 and the transistor 206 can be formed in a common process.

Next, Fig. 17B shows a cross-sectional structure of another structure of the display device 406 according to an embodiment of the present invention as an example. The display device 406 shown in FIG. 17B is different from the display device 406 shown in FIG. 17A in that the transistor 205 and the transistor 206 are respectively included in different layers.

Specifically, the display device 406 illustrated in FIG. 17B has a layer 210a including a transistor 205 and a layer 210b including a transistor 206 having a region between the liquid crystal element 204 and the light emitting element 203. Further, in the display device 406 shown in FIG. 17B, the layer 210a is disposed closer to the side of the light-emitting element 203 than the layer 210b. Further, in the case where the semiconductor layer included in the transistor 205 and the semiconductor layer included in the transistor 206 are located on at least different insulating surfaces, it can be said that the transistor 205 and the transistor 206 are included in different layers.

By adopting the above configuration, the various wirings of the transistor 205, the electrical connection to the transistor 205, and the various wirings electrically connected to the transistor 206 can be partially overlapped, so that the size of the pixel can be suppressed small, and The high resolution of the display device 406 is achieved.

Next, Fig. 17C shows a cross-sectional structure of another structure of the display device 406 according to an embodiment of the present invention as an example. The display device 406 shown in FIG. 17C is different from the display device 406 shown in FIG. 17A in that the transistor 205 and the transistor 206 are respectively included in different layers. In addition, the display device 406 shown in FIG. 17C is different from the display device 406 shown in FIG. 17B in that the layer 210a including the transistor 205 is disposed closer to the substrate 201 than the light-emitting element 203.

Specifically, the display device 406 shown in FIG. 17C has a layer 210a including a transistor 205 and a layer 210b including a transistor 206. Also, the layer 210a has a region between the light emitting element 203 and the substrate 201. In addition, the layer 210b has a region between the liquid crystal element 204 and the light-emitting element 203.

By adopting the above configuration, the area in which the transistor 205, the various wirings electrically connected to the transistor 205 and the transistor 206, and the various wirings electrically connected to the transistor 206 overlap can be further increased as compared with the case shown in Fig. 17B. Therefore, the size of the pixel can be suppressed to be small, and high resolution of the display device 406 can be achieved.

In addition, FIGS. 17A to 17C illustrate a cross-sectional structure of one light-emitting element 203 corresponding to two liquid crystal elements 204, but the display device according to an embodiment of the present invention may have a cross section of one light-emitting element 203 corresponding to one liquid crystal element 204. The structure may have a cross-sectional structure in which a plurality of light-emitting elements 203 correspond to one liquid crystal element 204.

17A to 17C illustrate a case where the pixel electrode 207 included in the liquid crystal element 204 has a function of reflecting visible light, but the pixel electrode 207 may have a function of transmitting visible light. In this case, a light source such as a backlight or a front light source may be provided in the display device 406, or the light-emitting element 203 may be used as a light source when displaying an image using the liquid crystal element 204.

The present embodiment corresponds to a method of changing, applying, super-conceptualizing, or sub-conceptualizing a part of other embodiments. Therefore, some or all of the embodiments may be combined or replaced with other embodiments.

 Embodiment 3  

In the present embodiment, a configuration example of a pixel included in a display device using a reflective display element and a light-emitting display element will be described. In the present embodiment, a configuration example of the pixel 300 according to an embodiment of the present invention will be described by taking a case where a liquid crystal element is used as a reflective display element and a light-emitting element using an EL material as an emission-type display element.

The pixel 300 shown in FIG. 18A includes a pixel 350 and a pixel 351. The pixel 350 includes a liquid crystal element 301, and the pixel 351 includes a light emitting element 302.

Specifically, the pixel 350 includes a liquid crystal element 301, a transistor 303 having a function of controlling a voltage applied to the liquid crystal element 301, and a capacitor 304. The gate of the transistor 303 is electrically connected to the wiring GL, one of the source and the drain is electrically connected to the wiring SL, and the other of the source and the drain is electrically connected to the pixel electrode of the liquid crystal element 301. Further, the common electrode of the liquid crystal element 301 is electrically connected to a wiring or an electrode to which a predetermined potential is supplied. Further, one electrode of the capacitor 304 is electrically connected to the pixel electrode of the liquid crystal element 301, and the other electrode is electrically connected to a wiring or electrode to which a specified potential is supplied.

Specifically, the pixel 351 includes a light-emitting element 302, a transistor 305 having a function of controlling a current supplied to the light-emitting element 302, a transistor 306 having a function of controlling a potential supply to the gate of the transistor 305, and a capacitor 307. The gate of the transistor 306 is electrically connected to the wiring GE, one of the source and the drain is electrically connected to the wiring DL, and the other of the source and the drain is electrically connected to the gate of the transistor 305. One of the source and the drain of the transistor 305 is electrically connected to the wiring AL, and the other of the source and the drain is electrically connected to the light-emitting element 302. One electrode of the capacitor 307 is electrically connected to the wiring AL, and the other electrode is electrically connected to the gate of the transistor 305.

In the pixel 300 shown in FIG. 18A, the image signal corresponding to the light-emitting element 302 is supplied to the wiring DL by supplying the image signal corresponding to the liquid crystal element 301 to the wiring SL, whereby the liquid crystal element 301 can be independently controlled. The gray scale expressed and the gray scale expressed by the light-emitting element 302.

Note that FIG. 18A shows a structural example of a pixel 300 including a pixel 350 including a liquid crystal element 301 and a pixel 351 including a light-emitting element 302, but the pixel 300 may also include a plurality of pixels 350 or a plurality of pixels 351.

FIG. 18B shows a structural example of a pixel 300 including one pixel 350 and four pixels 351.

Specifically, the pixel 300 illustrated in FIG. 18B includes a pixel 350 including a liquid crystal element 301 and pixels 351a to 351d each including a light emitting element 302.

Regarding the structure of the pixel 350 shown in FIG. 18B, the structure of the pixel 350 shown in FIG. 18A can be referred to.

The pixel 351a to the pixel 351d shown in FIG. 18B respectively include a light-emitting element 302, a transistor 305 having a function of controlling a current supplied to the light-emitting element 302, and a gate having a control pair of the transistor 305, similarly to the pixel 351 shown in FIG. 18A. A transistor 306 and a capacitor 307 that supply the function of the potential. The color image can be displayed on the display device by causing the light emitted from the light-emitting elements 302 included in each of the pixels 351a to 351d to have wavelengths of different regions.

In the pixel 351a to the pixel 351d shown in FIG. 18B, the gate of the transistor 306 included in the pixel 351a and the gate of the transistor 306 included in the pixel 351c are electrically connected to the wiring GEb. Further, the gate of the transistor 306 included in the pixel 351b and the gate of the transistor 306 included in the pixel 351d are electrically connected to the wiring GEa.

In addition, in the pixel 351a to the pixel 351d illustrated in FIG. 18B, one of the source and the drain of the transistor 306 included in the pixel 351a and one of the source and the drain of the transistor 306 included in the pixel 351b Electrically connected to the wiring DLa. Further, one of the source and the drain of the transistor 306 included in the pixel 351c and one of the source and the drain of the transistor 306 included in the pixel 351d are electrically connected to the wiring DLb.

In the pixel 351a to the pixel 351d shown in FIG. 18B, one of the source and the drain of all the transistors 305 is electrically connected to the wiring AL.

As described above, in the pixel 351a to the pixel 351d shown in FIG. 18B, the pixel 351a and the pixel 351c use the wiring GEb in common, and the pixel 351b and the pixel 351d use the wiring GEa in common, but the pixel 351a to the pixel 351d may also use one wiring GE in common. . In this case, the pixels 351a to 351d are preferably electrically connected to four wirings DL different from each other.

Next, Fig. 19A shows a structural example of a pixel 300 different from Fig. 18A. The pixel 300 shown in FIG. 19A is different from the pixel 300 shown in FIG. 18A in that the transistor 305 included in the pixel 351 includes a back channel.

Specifically, in the pixel 300 shown in FIG. 19A, the back gate of the transistor 305 is electrically connected to the gate (front gate). Since the pixel 300 shown in FIG. 19A has the above structure, the drift of the threshold voltage of the transistor 305 can be suppressed, and the reliability of the transistor 305 can be improved. In addition, since the pixel 300 shown in Fig. 19A has the above structure, the size of the transistor 305 can be reduced, and the on-state current of the transistor 305 can be increased.

In the display device of one embodiment of the present invention, the pixel 300 may also include a plurality of pixels 350 shown in FIG. 19A or pixels 351 shown in FIG. 19A. Specifically, as with the pixel 300 shown in FIG. 18B, one pixel 350 and four pixels 351 shown in FIG. 19A may be included. In this case, regarding the connection relationship of the various wirings to the four pixels 351, reference may be made to the pixel 300 shown in FIG. 18B.

Next, Fig. 19B shows a structural example of a pixel 300 different from Fig. 18A. The pixel 300 shown in FIG. 19B is different from the pixel 300 shown in FIG. 18A in that the transistor 305 included in the pixel 351 includes a back gate. The pixel 300 shown in FIG. 19B is different from the pixel 300 shown in FIG. 19A in that the back gate of the transistor 305 is electrically connected to the light-emitting element 302 without being electrically connected to the gate.

Since the pixel 300 shown in FIG. 19B has the above structure, the drift of the threshold voltage of the transistor 305 can be suppressed, and the reliability of the transistor 305 can be improved.

In the display device of one embodiment of the present invention, the pixel 300 may also include a plurality of pixels 350 shown in FIG. 19B or pixels 351 shown in FIG. 19B. Specifically, as with the pixel 300 shown in FIG. 18B, one pixel 350 and four pixels 351 shown in FIG. 19B may be included. In this case, regarding the connection relationship of the various wirings to the four pixels 351, reference may be made to the pixel 300 shown in FIG. 18B.

Next, Fig. 20 shows a structural example of a pixel 300 different from Fig. 18A. The pixel 300 shown in Fig. 20 includes a pixel 350 and a pixel 351, and the structure of the pixel 351 is different from that of Fig. 18A.

Specifically, the pixel 351 shown in FIG. 20 includes a light-emitting element 302, a transistor 305 having a function of controlling a current supplied to the light-emitting element 302, and a transistor 306 having a function of controlling a potential supply to the gate of the transistor 305, The transistor 308 and the capacitor 307 have a function of supplying a predetermined potential to the pixel electrode of the light-emitting element 302. Additionally, transistor 305, transistor 306, and transistor 308 all include a back gate.

The gate (front gate) of the transistor 306 is electrically connected to the wiring ML, the back gate is electrically connected to the wiring GE, and one of the source and the drain is electrically connected to the wiring DL, and the other of the source and the drain The gate and back gate of transistor 305 are electrically connected. One of the source and the drain of the transistor 305 is electrically connected to the wiring AL, and the other of the source and the drain is electrically connected to the light-emitting element 302.

The gate (front gate) of the transistor 308 is electrically connected to the wiring ML, the back gate is electrically connected to the wiring GE, and one of the source and the drain is electrically connected to the wiring ML, and the other of the source and the drain The light emitting elements 302 are electrically connected. One electrode of the capacitor 307 is electrically connected to the wiring AL, and the other electrode is electrically connected to the gate of the transistor 305.

Note that FIG. 20 shows a structural example of a pixel 300 including a pixel 350 including a liquid crystal element 301 and a pixel 351 including a light-emitting element 302, but the pixel 300 may also include a plurality of pixels 350 or a plurality of pixels 351.

FIG. 21 shows a structural example of a pixel 300 including one pixel 351 and four pixels 351.

Specifically, the pixel 300 illustrated in FIG. 21 includes a pixel 350 including a liquid crystal element 301 and pixels 351a to 351d each including a light emitting element 302.

Regarding the configuration of the pixel 350 shown in FIG. 21, the structure of the pixel 350 shown in FIG. 20 can be referred to.

The pixels 351a to 351d shown in FIG. 21 respectively include a light-emitting element 302, a transistor 305 having a function of controlling a current supplied to the light-emitting element 302, and a gate having a control pair of the transistor 305, similarly to the pixel 351 shown in FIG. A transistor 306 that supplies a function of a potential, a transistor 308 having a function of supplying a predetermined potential to a pixel electrode of the light-emitting element 302, and a capacitor 307. The color image can be displayed on the display device by causing the light emitted from the light-emitting elements 302 included in each of the pixels 351a to 351d to have wavelengths of different regions.

In the pixel 351a to the pixel 351d shown in FIG. 21, the gate of the transistor 306 included in the pixel 351a and the gate of the transistor 306 included in the pixel 351b are electrically connected to the wiring MLa. Further, the gate of the transistor 306 included in the pixel 351c and the gate of the transistor 306 included in the pixel 351d are electrically connected to the wiring MLb.

In the pixel 351a to the pixel 351d shown in FIG. 21, the back gate of the transistor 306 included in the pixel 351a and the back gate of the transistor 306 included in the pixel 351c are electrically connected to the wiring GEb. In addition, the back gate of the transistor 306 included in the pixel 351b and the back gate of the transistor 306 included in the pixel 351d are electrically connected to the wiring GEa.

Further, in the pixel 351a to the pixel 351d shown in FIG. 21, one of the source and the drain of the transistor 306 included in the pixel 351a and one of the source and the drain of the transistor 306 included in the pixel 351b Electrically connected to the wiring DLa. Further, one of the source and the drain of the transistor 306 included in the pixel 351c and one of the source and the drain of the transistor 306 included in the pixel 351d are electrically connected to the wiring DLb.

In the pixel 351a to the pixel 351d shown in FIG. 21, the back gate of the transistor 308 included in the pixel 351a and the back gate of the transistor 308 included in the pixel 351c are electrically connected to the wiring GEb. In addition, the back gate of the transistor 308 included in the pixel 351b and the back gate of the transistor 308 included in the pixel 351d are electrically connected to the wiring GEa.

In the pixel 351a to the pixel 351d shown in FIG. 21, the gate of the transistor 308 included in the pixel 351a and one of the source and the drain are electrically connected to the wiring MLa, and the gate of the transistor 308 included in the pixel 351b And one of the source and the drain is electrically connected to the wiring MLa. In addition, the gate of the transistor 308 included in the pixel 351c and one of the source and the drain are electrically connected to the wiring MLb, and the gate and the source and the drain of the transistor 308 included in the pixel 351b are wired. MLb is electrically connected.

In the pixel 351a to the pixel 351d shown in FIG. 21, one of the source and the drain of all the transistors 305 is electrically connected to the wiring AL.

As described above, in the pixel 351a to the pixel 351d shown in FIG. 21, the pixel 351a and the pixel 351c use the wiring GEb in common, and the pixel 351b and the pixel 351d use the wiring GEa in common, but the pixel 351a to the pixel 351d may also use one wiring GE in common. . In this case, the pixels 351a to 351d are preferably electrically connected to four wirings DL different from each other.

By using a transistor having a low off-state current in the pixel 350, it is possible to temporarily stop the driving circuit when it is not necessary to rewrite the display screen (in other words, a case where a still image is displayed) (hereinafter, referred to as "idling stop" "Or "IDS driver"). By performing IDS driving, the power consumption of the display device 406 can be reduced.

The present embodiment corresponds to a method of changing, applying, super-conceptualizing, or sub-conceptualizing a part of other embodiments. Therefore, some or all of the embodiments may be combined or replaced with other embodiments.

 Embodiment 4  

In the embodiment, a specific configuration example of the display device 406 using the reflective display element and the light-emitting display element will be described with reference to FIG. 22, taking the display device 406 shown in FIG. 17C as an example. 17 and FIG. 24 show a cross-sectional structure of a specific configuration example of the display device 406 using the reflective display element and the light-emitting display element, but detailed description thereof will be omitted. Note that the same components as those of FIG. 22 are attached with the same reference numerals in FIGS. 23 and 24.

FIG. 22 shows an example of a cross-sectional structure of the display device 406.

The display device 406 shown in FIG. 22 has a configuration in which a display portion 102 and a display portion 104 are laminated between a substrate 250 and a substrate 251. Specifically, in Fig. 22, the display portion 102 and the display portion 104 are bonded using the adhesive layer 252.

22 shows a light-emitting element 302, a transistor 305, a capacitor 307, and a transistor 309 of a driving circuit of the display unit 102, which are included in the pixels of the display unit 102. In addition, FIG. 22 shows the transistor 310 of the liquid crystal element 301, the transistor 303, the capacitor 304, and the drive circuit of the display unit 104 which the pixel of the display unit 104 has.

The transistor 305 includes a conductive layer 311 used as a back gate, an insulating layer 312 on the conductive layer 311, a semiconductor layer 313 on the insulating layer 312 and overlapping the conductive layer 311, and an insulating layer 316 on the semiconductor layer 313. A conductive layer 317 on the insulating layer 316 and used as a gate, a conductive layer 314 on the insulating layer 318 on the conductive layer 317 and electrically connected to the semiconductor layer 313, and a conductive layer 315.

The conductive layer 315 is electrically connected to the conductive layer 319, and the conductive layer 319 is electrically connected to the conductive layer 320. The conductive layer 319 and the conductive layer 317 are formed in the same layer, and the conductive layer 320 and the conductive layer 311 are formed in the same layer.

The conductive layer 321 of the transistor 306 (not shown) used as the back gate is located in the same layer as the conductive layer 311 and the conductive layer 320. The insulating layer 312 is located on the conductive layer 321, and the semiconductor layer 322 having a region overlapping the conductive layer 321 is located on the insulating layer 312. The semiconductor layer 322 includes a channel formation region of a transistor 306 (not shown). The insulating layer 318 is on the semiconductor layer 322, and the conductive layer 323 is on the insulating layer 318. The conductive layer 323 is electrically connected to the semiconductor layer 322, and the conductive layer 323 is used as a source electrode or a drain of the transistor 306 (not shown).

Since the transistor 309 has the same structure as the transistor 305, detailed description is omitted.

The insulating layer 324 is located on the transistor 305, the conductive layer 323, and the transistor 309, and the insulating layer 325 is located on the insulating layer 324. The conductive layer 326 and the conductive layer 327 are located on the insulating layer 325. The conductive layer 326 is electrically connected to the conductive layer 314, and the conductive layer 327 is electrically connected to the conductive layer 323. The insulating layer 328 is located on the conductive layer 326 and the conductive layer 327, and the conductive layer 329 is located on the insulating layer 328. The conductive layer 329 is electrically connected to the conductive layer 326 and is used as a pixel electrode of the light-emitting element 302.

A region where the conductive layer 327, the insulating layer 328, and the conductive layer 329 overlap each other is used as the capacitor 307.

The insulating layer 330 is on the conductive layer 329, the EL layer 331 is on the insulating layer 330, and the conductive layer 332 serving as the opposite electrode is on the EL layer 331. The conductive layer 329, the EL layer 331, and the conductive layer 332 are electrically connected to each other in the opening portion of the insulating layer 330, and a region where the conductive layer 329, the EL layer 331, and the conductive layer 332 are electrically connected to each other is used as the light-emitting element 302. The light-emitting element 302 has a top emission structure that emits light from the side of the conductive layer 332 toward the direction indicated by the arrow of the broken line.

One of the conductive layer 329 and the conductive layer 332 is used as an anode, and the other is used as a cathode. When a voltage higher than the threshold voltage of the light-emitting element 302 is applied between the conductive layer 329 and the conductive layer 332, the hole is injected into the EL layer 331 from the anode side, and electrons are injected into the EL layer 331 from the cathode side. The injected electrons and holes are recombined in the EL layer 331, and the luminescent substance contained in the EL layer 331 is caused to emit light.

When a metal oxide is used as the semiconductor layers 313 and 322, in order to improve the reliability of the display device, it is preferable to use an insulating material containing oxygen as the insulating layer 318, and it is not easy to diffuse water or hydrogen or the like as the insulating layer 324. s material.

In the case where an organic material is used as the insulating layer 325 or the insulating layer 330, if the insulating layer 325 or the insulating layer 330 is exposed in the end portion of the display device, impurities such as moisture may pass through the insulating layer 325 or the insulating layer from the outside of the display. 330 enters the light-emitting element 302 and the like. If the intrusion of impurities causes the light-emitting element 302 to deteriorate, deterioration of the display device is caused. Therefore, as shown in FIG. 22, the insulating layer 325 and the insulating layer 330 are preferably not located at the end of the display device.

The light emitting element 302 overlaps the color layer 334 via the adhesive layer 333. The spacer 335 overlaps the light shielding layer 336 via the adhesive layer 333. Fig. 22 shows a case where there is a space between the conductive layer 332 and the light shielding layer 336, but they may also be in contact.

The color layer 334 is a colored layer that transmits light of a specific wavelength region. For example, a color filter or the like that transmits light in a wavelength range of red, green, blue, or yellow can be used.

Further, an embodiment of the present invention is not limited to the color filter method, and a coating method, a color conversion method, a quantum dot method, or the like may be employed.

In the display portion 104, the transistor 303 includes a conductive layer 340 used as a back gate, an insulating layer 341 on the conductive layer 340, a semiconductor layer 342 on the insulating layer 341 and overlapping the conductive layer 340, and a semiconductor layer 342. The insulating layer 343, the conductive layer 344 on the insulating layer 343 and used as a gate, the conductive layer 346 on the insulating layer 345 on the conductive layer 344 and electrically connected to the semiconductor layer 342, and the conductive layer 347.

Conductive layer 340 and conductive layer 348 are located in the same layer. The insulating layer 341 is on the conductive layer 348, and the conductive layer 347 is located on the insulating layer 341 in a region overlapping the conductive layer 348. A region where the conductive layer 347, the insulating layer 341, and the conductive layer 348 overlap each other is used as the capacitor 304.

Since the transistor 310 has the same structure as the transistor 303, detailed description is omitted.

The insulating layer 360 is located on the transistor 303, the capacitor 304, and the transistor 310, and the conductive layer 349 is located on the insulating layer 360. The conductive layer 349 is electrically connected to the conductive layer 347, and is used as a pixel electrode of the liquid crystal element 301. The alignment film 364 is on the conductive layer 349.

The substrate 251 is provided with a conductive layer 361 which is used as a common electrode. Specifically, in FIG. 22, the insulating layer 363 is bonded to the substrate 251 using the adhesive layer 362, and the conductive layer 361 is positioned on the insulating layer 363. The alignment film 365 is located on the conductive layer 361, and the liquid crystal layer 366 is located between the alignment film 364 and the alignment film 365.

In FIG. 22, since the conductive layer 349 has a function of reflecting visible light, the conductive layer 361 has a function of transmitting visible light, so that light incident from the side of the substrate 251 can be reflected by the conductive layer 349 and reflected from the substrate as indicated by a broken arrow. 251 side shot.

As the conductive material that transmits visible light, for example, a material containing one selected from the group consisting of indium (In), zinc (Zn), and tin (Sn) is preferably used. Specifically, indium oxide, indium tin oxide (ITO: Indium Tin Oxide), indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, and indium oxidation containing titanium oxide may be mentioned. An indium tin oxide containing titanium oxide, indium tin oxide containing cerium oxide (ITSO), zinc oxide, zinc oxide containing gallium, or the like. Further, a film containing graphene may also be used. The film containing graphene can be formed, for example, by reducing graphene oxide formed into a film shape.

Examples of the conductive material that reflects visible light include aluminum, silver, and an alloy containing these metal materials. Further, a metal material such as gold, platinum, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper or palladium or an alloy containing these metal materials may be used. Further, ruthenium, osmium or iridium may be added to the above metal material or alloy. In addition, alloys of aluminum and titanium, alloys of aluminum and nickel, alloys of aluminum and niobium, alloys of aluminum, nickel and niobium (Al-Ni-La), alloys containing aluminum (aluminum alloy), silver and copper may also be used. An alloy containing silver, such as an alloy of alloy, silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC) or an alloy of silver and magnesium.

22 to 24 illustrate a structure of a display device using a top gate type transistor including a back gate, but the display device of one embodiment of the present invention may also use a transistor not including a back gate, and may also be used. Top gate type transistor.

The crystallinity of the semiconductor material used for the transistor is also not particularly limited, and an amorphous semiconductor or a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor having a crystal region in a part thereof) can be used. It is preferable to use a semiconductor having crystallinity to suppress deterioration of characteristics of the crystal.

Further, as the semiconductor material for the transistor, a metal oxide can be used. Typically, a metal oxide containing indium or the like can be used. In particular, when a semiconductor material having a band gap wider than that of 矽 and having a small carrier density is used, it is preferable to reduce the current in the closed state of the transistor.

When a metal oxide is used, as the semiconductor layer, for example, "In-M" including indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, antimony, zirconium, hafnium, tantalum, tin, antimony, or antimony) may be used. a film represented by a -Zn-based oxide.

When the metal oxide constituting the semiconductor layer is an In-M-Zn-based oxide, it is preferred that the atomic ratio of the metal element of the sputtering target for forming the In-M-Zn oxide film satisfies In M and Zn M. The atomic number of the metal element of the sputtering target is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2 , In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In :M:Zn=5:1:8 and so on. Note that the atomic ratio of the formed semiconductor layer may vary within a range of ±40% of the atomic ratio of the metal elements in the sputtering target.

The transistor of the bottom gate structure shown in this embodiment is preferable because it can reduce the number of processes. Further, at this time, by using a metal oxide, a metal oxide can be formed at a temperature lower than that of the polycrystalline silicon, and a material having low heat resistance can be used as a material of the wiring or the electrode under the semiconductor layer and the substrate material, thereby being able to be expanded The range of materials to choose from. For example, a glass substrate or the like having a very large area can be suitably used.

As the semiconductor layer, a metal oxide film having a low carrier density can be used. For example, as the semiconductor layer, a carrier density of 1 × 10 ¹⁷ /cm ³ or less, preferably 1 × 10 ¹⁵ /cm ³ or less, more preferably 1 × 10 ¹³ /cm ³ or less, further preferably 1 × can be used. Further, 10 ¹¹ /cm ³ or less is more preferably a metal oxide of less than 1 × 10 ¹⁰ /cm ³ and 1 × 10 ^-9 /cm ³ or more. Such metal oxides are referred to as metal oxides of high purity nature or substantially high purity nature. Thus, since the impurity concentration and the defect energy level density are low, it can be said that it is a metal oxide having stable characteristics.

Note that the present invention is not limited to the above description, and a material having an appropriate composition can be used depending on semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, and the like) of a desired transistor. Further, it is preferable to appropriately set the carrier density, the impurity concentration, the defect density, the atomic ratio of the metal element to oxygen, the interatomic distance, the density, and the like of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

When the metal oxide constituting the semiconductor layer contains tantalum or carbon of one of the Group 14 elements, an increase in oxygen defects in the semiconductor layer causes the semiconductor layer to become n-type. Therefore, the concentration of ruthenium or carbon (concentration measured by secondary ion mass spectrometry) in the semiconductor layer is set to 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less. .

Further, when an alkali metal and an alkaline earth metal are bonded to a metal oxide, a carrier is sometimes generated to increase an off-state current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal of the semiconductor layer measured by secondary ion mass spectrometry is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, when the metal oxide constituting the semiconductor layer contains nitrogen, electrons as carriers are generated, and the carrier density is increased to facilitate n-type formation. As a result, the use of a transistor having a metal oxide containing nitrogen tends to become a normally-on property. Therefore, the nitrogen concentration of the semiconductor layer measured by secondary ion mass spectrometry is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

Further, the semiconductor layer may have a non-single crystal structure, for example. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor or C-Axis Aligned and AB-plane Anchored Crystalline Oxide Semiconductor) having a c-axis alignment, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. . In the non-single crystal structure, the amorphous structure has the highest defect state density, while the CAAC-OS has the lowest defect state density.

The metal oxide film of an amorphous structure has, for example, an disordered atomic arrangement and does not have a crystalline component. Alternatively, the oxide film of the amorphous structure is, for example, a completely amorphous structure and does not have a crystal portion.

Further, the semiconductor layer may be a mixed film of a region having an amorphous structure, a region of a microcrystalline structure, a region of a polycrystalline structure, a region of a CAAC-OS, and a region of a single crystal structure. The mixed film sometimes has, for example, a single layer structure or a laminated structure including two or more regions in the above regions.

In the present embodiment, a configuration of a display device using a liquid crystal element as a reflective display element is exemplified. However, as a reflective display element, a MEMS (Micro Electro Mechanical Systems) element and a light interference can be used. A display element such as a MEMS element, a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic powder fluid (registered trademark in Japan).

Further, as the light-emitting display element, for example, an OLED (Organic Light Emitting Diode), an LED (Light Emitting Diode), or a QLED (Quantum-dot Light Emitting Diode) can be used. Self-luminous light-emitting elements such as polar bodies).

As the liquid crystal element, an element using a VA (Vertical Alignment) mode can be used. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

Further, as the liquid crystal element, a liquid crystal element using various modes can be employed. For example, in addition to the VA mode, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, and ASM (Axially Symmetric Aligned) can be used. Micro-cell: axisymmetric array of microcells) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. Liquid crystal element.

As the liquid crystal used for the liquid crystal element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesterol phase, a smectic phase, a cubic phase, a nematic phase, and an isotropic phase according to conditions.

Further, as the liquid crystal material, any of a positive liquid crystal and a negative liquid crystal may be used, and an appropriate liquid crystal material may be used depending on the mode or design to be used.

Further, in order to control the alignment of the liquid crystal, an alignment film may be provided. In the case of the transverse electric field method, a liquid crystal exhibiting a blue phase without using an alignment film can also be used. The blue phase is a kind of liquid crystal phase, and refers to a phase which occurs immediately before the temperature of the cholesteric liquid crystal rises from the transition of the cholesterol phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which several wt% or more of a chiral agent is mixed is used for the liquid crystal layer to expand the temperature range. A liquid crystal composition comprising a liquid crystal exhibiting a blue phase and a chiral agent has a fast response speed and is optically isotropic. Further, the liquid crystal composition containing the liquid crystal exhibiting a blue phase and a chiral agent does not require an alignment treatment, and the viewing angle dependency is small. Further, since it is not necessary to provide the alignment film without the need of the rubbing treatment, it is possible to prevent electrostatic breakdown due to the rubbing treatment, and it is possible to reduce the defects and breakage of the liquid crystal display device in the process.

The present embodiment corresponds to a method of changing, applying, super-conceptualizing, or sub-conceptualizing a part of other embodiments. Therefore, some or all of the embodiments may be combined or replaced with other embodiments.

 Embodiment 5  

In the present embodiment, a configuration of a CAC (Cloud-Aligned Composite)-OS that can be used in the transistor disclosed in one embodiment of the present invention will be described.

 <Composition of CAC-OS>  

In the present specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also abbreviated as OS). For example, when a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, the OS FET can be referred to as a transistor including a metal oxide or an oxide semiconductor.

In the present specification, the following metal oxide is defined as CAC (Cloud Aligned Composite)-OS (Oxide Semiconductor) or CAC-metal oxide: a region of a metal oxide having a function of a conductor and a region having a function of a dielectric are mixed The metal oxide has a semiconductor function as a whole.

In other words, CAC-OS is, for example, a configuration in which elements contained in an oxide semiconductor are unevenly distributed, and a material including an element which is unevenly distributed has a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more. Below 3 nm or approximate size. Note that a state in which one or more elements in the oxide semiconductor are unevenly distributed and a region including the element is mixed is also referred to as a mosaic or patch shape, and the size of the region is 0.5 nm. The above and 10 nm or less are preferably 0.5 nm or more and 3 nm or less or approximately the same size.

The physical characteristics of a region containing a specific element that is unevenly distributed are determined by the properties possessed by the element. For example, a region including an element which is unevenly distributed and contains an element which is more likely to be an insulator among the elements in the metal oxide becomes a dielectric region. On the other hand, a region including an element which is unevenly distributed and contained in the metal oxide and which tends to become an element of the conductor becomes a conductor region. The material has a semiconductor function by mixing the conductor region and the dielectric region in a mosaic form.

In other words, the metal oxide of one embodiment of the present invention is one of a matrix composite or a metal matrix composite in which materials having different physical properties are mixed.

The oxide semiconductor preferably contains at least indium. It is especially preferred to include indium and zinc. In addition, it may further comprise an element M (M is selected from the group consisting of gallium, aluminum, lanthanum, boron, lanthanum, copper, vanadium, niobium, titanium, iron, nickel, cerium, zirconium, molybdenum, niobium, tantalum, niobium, tantalum, niobium One or more of bismuth, antimony, tungsten and magnesium).

For example, CAC-OS in In-Ga-Zn oxide (in the case of CAC-OS, in particular, In-Ga-Zn oxide is referred to as CAC-IGZO) means that the material is divided into indium oxide (hereinafter, referred to as InO) _X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter, referred to as In _X2 Zn _Y2 O _Z2 (X2, Y2 and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter, referred to as GaO _X3) (X3 is a real number greater than 0) or gallium zinc oxide (hereinafter, referred to as Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers greater than 0)), and is mosaic-like, and mosaic-like InO _X1 Or a composition in which In _X2 Zn _Y2 O _{Z2 is} uniformly distributed in the film (hereinafter, also referred to as a cloud shape).

In other words, CAC-OS is a composite oxide semiconductor having a structure in which a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are mixed. In the present specification, for example, when the atomic ratio of the In to element M of the first region is larger than the atomic ratio of the In to the element M of the second region, the In concentration of the first region is higher than that of the second region.

Note that IGZO is a generic term and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _(1+x0) Ga _(1-x0) O ₃ (ZnO) _m0 (-1) X0 1, m0 is an arbitrary number of crystalline compounds.

The above crystalline compound has a single crystal structure, a polycrystalline structure or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of nanocrystals of IGZO have c-axis alignment and are connected in an unaligned manner on the a-b plane.

On the other hand, CAC-OS is related to the material composition of an oxide semiconductor. CAC-OS is a structure in which a nanoparticle-like region containing Ga as a main component is observed in a part of a material composition containing In, Ga, Zn, and O, and a portion containing In as a main component is observed in a part. Particle-like regions, and these regions are irregularly dispersed in a mosaic shape. Therefore, in CAC-OS, the crystal structure is a secondary factor.

The CAC-OS does not include a laminated structure of two or more different compositions. For example, a structure composed of two layers of a film containing In as a main component and a film containing Ga as a main component is not included.

Note that a clear boundary between a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component may not be observed.

Included in CAC-OS is selected from the group consisting of aluminum, lanthanum, boron, lanthanum, copper, vanadium, niobium, titanium, iron, nickel, cerium, zirconium, molybdenum, niobium, tantalum, niobium, tantalum, niobium, tungsten and magnesium. In the case of replacing one or more of gallium, CAC-OS refers to a structure in which a nanoparticle-like region containing the element as a main component is observed in a part, and a nanoparticle-like region containing In as a main component is observed in a part thereof. And, these areas are scattered irregularly in a mosaic shape.

 <Analysis of CAC-OS>  

Next, the results of measurement of the oxide semiconductor formed on the substrate using various measurement methods will be described.

 <The structure and manufacturing method of the sample>  

Hereinafter, nine samples of one embodiment of the present invention will be described. Each sample differs in substrate temperature and oxygen gas flow ratio at the time of forming an oxide semiconductor. Each sample includes a substrate and an oxide semiconductor on the substrate.

A method of manufacturing each sample will be described.

A glass substrate is used as the substrate. An In-Ga-Zn oxide having a thickness of 100 nm was formed as an oxide semiconductor on a glass substrate using a sputtering apparatus. The film formation conditions were as follows: the pressure in the chamber was set to 0.6 Pa, and an oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) was used as a target. In addition, an AC power of 2500 W was supplied to the oxide target provided in the sputtering apparatus.

In the formation of an oxide, nine samples were produced under the following conditions: the substrate temperature was set to a temperature at which the intended heating was not performed (hereinafter, also referred to as room temperature or R.T.), 130 ° C or 170 ° C. Further, the flow ratio of the oxygen gas to the mixed gas of Ar and oxygen (hereinafter also referred to as the oxygen gas flow ratio) is set to 10%, 30% or 100%.

 <X-ray diffraction analysis>  

In this section, the results of X-ray diffraction (XRD) measurement of nine samples are described. As the XRD apparatus, D8 ADVANCE manufactured by Bruker Corporation was used. The conditions were as follows: θ/2θ scanning was performed by the Out-of-plane method, the scanning range was 15 deg. to 50 deg., the step width was 0.02 deg., and the scanning speed was 3.0 deg. / min.

Fig. 25 shows the results of measuring the XRD spectrum by the Out-of-plane method. In Fig. 25, the measurement results of the sample having a substrate temperature of 170 ° C at the time of film formation are shown in the uppermost row, and the measurement results of the sample having a substrate temperature of 130 ° C at the time of film formation are shown in the middle row, and the film formation is shown in the lowermost row. The substrate temperature is the measurement result of the sample of RT. Further, the leftmost column shows the measurement results of the sample having an oxygen gas flow rate ratio of 10%, the middle column shows the measurement results of the sample having the oxygen gas flow rate ratio of 30%, and the rightmost column shows that the oxygen gas flow ratio is 100%. The measurement result of the sample.

The XRD spectrum shown in FIG. 25 shows that the higher the substrate temperature at the time of film formation or the higher the oxygen gas flow rate ratio at the time of film formation, the higher the peak intensity in the vicinity of 2θ=31°. Further, it is known that a peak near 2θ=31° is derived from a crystalline IGZO compound having a c-axis alignment in a direction substantially perpendicular to a surface to be formed or a top surface (also referred to as CAAC (c-axis aligned crystalline)-IGZO ).

Further, as shown by the XRD spectrum of FIG. 25, the lower the substrate temperature at the time of film formation or the lower the oxygen gas flow rate ratio, the less the peak value is. Therefore, it was found that in the samples in which the substrate temperature at the time of film formation was low or the oxygen gas flow rate ratio was low, the alignment of the measurement region in the a-b plane direction and the c-axis direction was not observed.

 <Electron Microscope Analysis>  

In this section, the HAADF-STEM (High-Angle Annular Dark Field Scanning Transmission Electron Microscope) is used for the sample manufactured under the condition that the substrate temperature at the time of film formation is RT and the oxygen gas flow ratio is 10%. - Scanning electron microscope) The results of observation and analysis (hereinafter, images obtained by HAADF-STEM are also referred to as TEM images).

The results of image analysis are performed on a planar image (hereinafter also referred to as a planar TEM image) and a cross-sectional image (hereinafter also referred to as a cross-sectional TEM image) obtained by HAADF-STEM. The TEM image is observed using the spherical aberration correction function. In the case of obtaining the HAADF-STEM image, an electron beam JEM-ARM200F manufactured by JEOL Ltd. was used, and an acceleration voltage was set to 200 kV, and an electron beam having a beam diameter of approximately 0.1 nm Φ was irradiated.

Fig. 26A is a plan TEM image of a sample produced under the conditions that the substrate temperature at the time of film formation is R.T. and the oxygen gas flow rate ratio is 10%. Fig. 26B is a cross-sectional TEM image of a sample produced under the conditions that the substrate temperature at the time of film formation is R.T. and the oxygen gas flow rate ratio is 10%.

 <Analysis of Electronic Diffraction Patterns>  

In this section, an electron beam (also referred to as a nanobeam) having a beam diameter of 1 nm is irradiated to a sample produced under the condition that the substrate temperature at the time of film formation is RT and the oxygen gas flow rate ratio is 10%. The result of the electronic diffraction pattern.

The black dot a1, the black dot a2, the black dot a3, and the black dot a4 in the planar TEM image of the sample prepared under the condition that the substrate temperature at the time of film formation is RT and the oxygen gas flow ratio is 10% as shown in FIG. 26A are observed. And an electronic diffraction pattern of black dots a5. The observation of the electronic diffraction pattern was performed by irradiating the electron beam at a fixed speed for 35 seconds. 26C shows the result of the black dot a1, FIG. 26D shows the result of the black dot a2, FIG. 26E shows the result of the black dot a3, FIG. 26F shows the result of the black dot a4, and FIG. 26G shows the result of the black dot a5.

In FIGS. 26C, 26D, 26E, 26F, and 26G, a region having a high (bright) brightness such as a circle is observed. In addition, a plurality of spots were observed in the annular region.

The black spot b1, the black dot b2, the black dot b3, and the black dot b4 in the cross-sectional TEM image of the sample prepared under the condition that the substrate temperature at the time of film formation is RT and the oxygen gas flow ratio is 10% as shown in FIG. 26B is observed. And the electronic diffraction pattern of the black point b5. 26H shows the result of the black dot b1, FIG. 26I shows the result of the black dot b2, FIG. 26J shows the result of the black dot b3, FIG. 26K shows the result of the black dot b4, and FIG. 26L shows the result of the black dot b5.

In FIGS. 26H, 26I, 26J, 26K, and 26L, a region having a high luminance of a ring shape was observed. In addition, a plurality of spots were observed in the annular region.

For example, when an electron beam having a beam diameter of 300 nm is incident on a CAAC-OS containing InGaZnO ₄ crystal in a direction parallel to the sample surface, a diffraction pattern containing spots derived from the (009) plane of the InGaZnO ₄ crystal is obtained. In other words, the CAAC-OS has a c-axis orientation, and the c-axis faces a direction substantially perpendicular to the surface to be formed or the top surface. On the other hand, when an electron beam having a beam diameter of 300 nm was incident on the same sample in a direction perpendicular to the sample surface, an annular diffraction pattern was confirmed. In other words, CAAC-OS does not have a-axis alignment and b-axis alignment.

When an electron beam having a large beam diameter (for example, 50 nm or more) is used for electron diffraction of a nanocrystalline oxide semiconductor (hereinafter referred to as nc-OS), a diffraction pattern similar to a halo pattern is observed. . Further, when electron beam of a small beam diameter (for example, less than 50 nm) is used to perform nanobeam electron diffraction on the nc-OS, bright spots (spots) are observed. Further, in the nanobeam electron diffraction pattern of the nc-OS, a region having a high (bright) brightness such as a circle may be observed. Moreover, a plurality of bright spots are sometimes observed in the annular region.

The electron diffraction pattern of the sample produced under the condition that the substrate temperature at the time of film formation was R.T. and the oxygen gas flow rate ratio was 10% had a region having a high ring-shaped luminance and a plurality of bright spots appeared in the annular region. Therefore, the sample produced under the condition that the substrate temperature at the time of film formation was R.T. and the oxygen gas flow rate ratio was 10% exhibited an electron diffraction pattern similar to that of nc-OS, and had no alignment in the planar direction and the cross-sectional direction.

As described above, the properties of the oxide semiconductor having a low substrate temperature or a low oxygen gas flow rate at the time of film formation are significantly different from those of the oxide semiconductor film of the amorphous structure and the oxide semiconductor film of the single crystal structure.

 <<Elemental analysis>>  

In this section, an EDX surface analysis image is obtained by EDS (Energy Dispersive X-ray spectroscopy) and evaluated, whereby the substrate temperature at the time of film formation is RT and the oxygen gas flow ratio is The results of elemental analysis of samples made under 10% conditions. In the EDX measurement, an energy dispersive X-ray analyzer JED-2300T manufactured by JEOL Ltd. was used as the elemental analysis device. A chirped drift detector is used when detecting X-rays emitted from the sample.

In the EDX measurement, an electron beam is irradiated to each point of the analysis target region of the sample, and the energy and the number of occurrences of the characteristic X-ray of the sample occurring at this time are measured, and an EDX spectrum corresponding to each point is obtained. In the present embodiment, the peak of the EDX spectrum at each point is attributed to the electron transition to the L shell in the In atom, the electron transition to the K shell in the Ga atom, and the electronic transition to the K shell in the Zn atom. And the electron transition to the K shell in the O atom, and the ratio of each atom at each point is calculated. By performing the above steps in the analysis target region of the sample, an EDX surface analysis image showing the ratio distribution of each atom can be obtained.

27A to 27C show an EDX surface analysis image of a cross section of a sample produced under the condition that the substrate temperature at the time of film formation is R.T. and the oxygen gas flow rate ratio is 10%. Fig. 27A shows an EDX surface analysis image of Ga atoms (the ratio of Ga atoms in all atoms is 1.18 to 18.64 [atomic%]). Fig. 27B shows an EDX surface analysis image of In atoms (the ratio of In atoms in all atoms is 9.28 to 33.74 [atomic%]). Fig. 27C shows an EDX surface analysis image of Zn atoms (the ratio of Zn atoms in all atoms is 6.69 to 24.99 [atomic%]). 27A, 27B, and 27C show the same region in the cross section of the sample produced under the condition that the substrate temperature at the time of film formation is R.T. and the oxygen gas flow rate ratio is 10%. In the EDX surface analysis image, the ratio of elements is indicated by light and dark: the more the measurement elements in the area, the brighter the area, and the less the measurement element, the darker the area. The magnification of the EDX surface analysis image shown in Figs. 27A to 27C is 7.2 million times.

In the EDX surface analysis image shown in FIG. 27A, FIG. 27B, and FIG. 27C, the relative distribution of light and dark was confirmed, and it was confirmed in the sample manufactured under the condition that the substrate temperature at the time of film formation was RT and the oxygen gas flow rate ratio was 10%. There is a distribution to each atom. Here, attention is paid to the area surrounded by the solid line and the area surrounded by the broken line shown in FIGS. 27A, 27B, and 27C.

In Fig. 27A, relatively dark areas are more in the area surrounded by the solid lines, and relatively bright areas are more in the area surrounded by the broken lines. In addition, in FIG. 27B, a relatively bright region is more in a region surrounded by a solid line, and a relatively dark region is more in a region surrounded by a broken line.

In other words, the area surrounded by the solid line is a relatively large area of In atoms, and the area surrounded by the dotted line is a relatively small area of In atoms. In Fig. 27C, in the area surrounded by the solid line, the right side is a relatively bright area, and the left side is a relatively dark area. Therefore, the region surrounded by the solid line is a region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 or the like.

In addition, a region surrounded by a solid line is a region in which Ga atoms are relatively small, and a region surrounded by a broken line is a region in which Ga atoms are relatively large. In FIG. 27C, in the area surrounded by the broken line, the upper left area is a relatively bright area, and the lower right area is a relatively dark area. Therefore, the region surrounded by the broken line is a region mainly composed of GaO _X3 or Ga _X4 Zn _Y4 O _Z4 or the like.

As shown in FIG. 27A, FIG. 27B, and FIG. 27C, the distribution of In atoms is more uniform than that of Ga atoms, and the region containing InO _X1 as a main component appears to be composed of In _X2 Zn _Y2 O _Z2 as a main component. The areas are interconnected. In this way, a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is formed in a cloud shape.

In this way, an In-Ga-Zn oxide having a composition mainly composed of GaO _X3 or the like and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component may be unevenly distributed and referred to as CAC- OS.

The crystal structure of CAC-OS has an nc structure. In the electronic diffraction pattern of CAC-OS having the nc structure, in addition to the bright spots (spots) of IGZO containing a single crystal, polycrystalline or CAAC structure, a plurality of bright spots (spots) appear. Alternatively, the crystal structure is defined as a region in which a ring-shaped luminance is high in addition to a plurality of bright spots (spots).

In addition, as shown in FIG. 27A, FIG. 27B and FIG. 27C, the region containing GaO _X3 or the like as a main component and the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component have a size of 0.5 nm or more and 10 nm or less or 1 nm. Above and below 3 nm. In the EDX surface analysis image, the diameter of a region containing each element as a main component is preferably 1 nm or more and 2 nm or less.

As described above, the structure of CAC-OS is different from the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of IGZO compounds. In other words, CAC-OS has a structure in which a region containing GaO _X3 or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are separated from each other, and a region containing each element as a main component is a mosaic.

Here, the conductivity of a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is higher than a region containing GaO _X3 or the like as a main component. In other words, when the carrier flows through a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component, the conductivity of the oxide semiconductor is exhibited. Therefore, when a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is distributed in a cloud shape in an oxide semiconductor, a high field effect mobility (μ) can be achieved.

On the other hand, the region containing GaO _X3 or the like as a main component has higher insulation than the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component. In other words, when a region containing GaO _X3 or the like as a main component is distributed in the oxide semiconductor, a leakage current can be suppressed to achieve a good switching operation.

Therefore, when CAC-OS is used for a semiconductor element, high on-state current (I _on ) and high can be achieved due to insulation of GaO _X3 or the like and complementation of conductivity due to In _X2 Zn _Y2 O _Z2 or InO _X1 . Field effect mobility (μ).

In addition, semiconductor elements using CAC-OS have high reliability. Therefore, the CAC-OS is suitable for various semiconductor devices such as displays.

Since the field effect mobility is high and the driving energy is high in a transistor having a CAC-OS in a semiconductor layer, by using the transistor for a driving circuit, typically a scanning line driving circuit that generates a gate signal, A display device with a narrow border width (also called a narrow bezel) is provided. In addition, a signal line driving circuit for supplying a signal from a signal line included in a display device by the transistor (in particular, a solution connected to an output terminal of a shift register included in the signal line driving circuit) The device can provide a display device with a small number of wires connected to the display device.

In addition, the transistor having a semiconductor layer having a CAC-OS does not require a laser crystallization process like the use of a low-temperature multi-turn transistor. Thereby, even if it is a display device using a large-area substrate, the manufacturing cost can be reduced. Also, high resolution such as Ultra HD (also called "4K resolution", "4K2K" or "4K"), Ultra HD (also called "8K resolution", "8K4K" or "8K") In the large display device, it is preferable to use a transistor having a CAC-OS in a semiconductor layer for a driving circuit and a display portion, thereby enabling writing in a short time and reducing display defects.

In addition, germanium can be used for the channel-forming semiconductor of the transistor. As the germanium, an amorphous germanium can be used, and it is particularly preferable to use a germanium having crystallinity. For example, microcrystalline germanium, polycrystalline germanium, single crystal germanium or the like is preferably used. In particular, polycrystalline germanium can be formed at a low temperature as compared with single crystal germanium, and its field effect mobility is higher than that of amorphous germanium, so that the reliability of polycrystalline germanium is high.

The transistor of the bottom gate structure shown in this embodiment is preferable because it can reduce the number of processes. Further, at this time, by using an amorphous germanium, an oxide semiconductor can be formed at a temperature lower than that of the polycrystalline germanium, and a material having low heat resistance can be used as a material of the wiring or the electrode under the semiconductor layer and the substrate material, thereby being able to expand The range of materials to choose from. For example, a glass substrate or the like having a very large area can be suitably used. On the other hand, the top gate type transistor is easy to form an impurity region in a self-aligned manner, so that unevenness in characteristics and the like can be reduced, which is preferable. At this time, it is particularly preferable to use polycrystalline germanium or single crystal germanium or the like.

The present embodiment corresponds to a method of changing, applying, super-conceptualizing, or sub-conceptualizing a part of other embodiments. Therefore, some or all of the embodiments may be combined or replaced with other embodiments.

 Embodiment 6  

In the present embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

The display module 6000 shown in FIG. 28A includes a display panel 6006, a frame 6009, a printed circuit board 6010, and a battery 6011 connected to the FPC 6005 between the upper cover 6001 and the lower cover 6002.

For example, the display device manufactured using one embodiment of the present invention described above can be used for the display panel 6006. Thereby, the display module can be manufactured with high yield.

The upper cover 6001 and the lower cover 6002 may be appropriately changed in shape or size according to the size of the display panel 6006.

The touch panel may be disposed to overlap the display panel 6006. The touch panel may be a resistive touch panel or a capacitive touch panel, and may be disposed to overlap the display panel 6006. In addition, the display panel 6006 can also have a touch panel function without providing a touch panel.

The frame 6009 has a function of protecting the display panel 6006, and also has a function of blocking electromagnetic shielding of electromagnetic waves generated by the operation of the printed circuit board 6010. In addition, the frame 6009 can also have the function of a heat sink.

The printed circuit board 6010 includes a power supply circuit and a signal generating circuit for outputting a video signal and a pulse signal. As the power source for supplying power to the power supply circuit, an external commercial power source may be used, or a power source using a separately provided battery 6011 may be used. The battery 6011 can be omitted when a commercial power source is used.

In addition, members such as a polarizing plate, a phase difference plate, and a cymbal sheet may be disposed in the display module 6000.

28B is a schematic cross-sectional view of a display module 6000 having an optical touch sensor.

The display module 6000 includes a light emitting portion 6015 and a light receiving portion 6016 which are disposed on the printed circuit board 6010. Further, a pair of light guiding portions (the light guiding portion 6017a and the light guiding portion 6017b) are provided in a region surrounded by the upper cover 6001 and the lower cover 6002.

As the upper cover 6001 and the lower cover 6002, for example, plastic can be used. The thickness of the upper cover 6001 and the lower cover 6002 may be thin (for example, 0.5 mm or more and 5 mm or less). Therefore, the weight of the display module 6000 can be made extremely light. In addition, the upper cover 6001 and the lower cover 6002 can be manufactured with a small amount of material, so that the manufacturing cost can be reduced.

The display panel 6006 overlaps the printed circuit board 6010 and the battery 6011 via the frame 6009. The display panel 6006 and the frame 6009 are fixed to the light guiding portion 6017a and the light guiding portion 6017b.

The light 6018 emitted from the light-emitting portion 6015 passes through the light guiding portion 6017a, the top of the display panel 6006, and the light guiding portion 6017b to reach the light receiving portion 6016. For example, when the light 6018 is blocked by a subject such as a finger or a stylus, a touch operation can be detected.

For example, the plurality of light emitting portions 6015 are disposed along adjacent two sides of the display panel 6006. The plurality of light receiving units 6016 are disposed at positions facing the light emitting unit 6015 via the display panel 6006. Thereby, information on the position of the touch operation can be obtained.

As the light-emitting portion 6015, for example, a light source such as an LED element can be used. In particular, as the light-emitting portion 6015, it is preferable to use a light source that emits infrared rays that are not seen by the user and are harmless to the user.

As the light receiving portion 6016, a photoelectric element that receives the light emitted from the light emitting portion 6015 and converts it into an electrical signal can be used. It is preferable to use a photodiode capable of receiving infrared rays.

As the light guiding portion 6017a and the light guiding portion 6017b, a member that transmits at least the light 6018 can be used. By using the light guiding portion 6017a and the light guiding portion 6017b, the light emitting portion 6015 and the light receiving portion 6016 can be disposed on the lower side of the display panel 6006, and the external light can be prevented from reaching the light receiving portion 6016, resulting in malfunction of the touch sensor. . It is particularly preferable to use a resin which absorbs visible light and transmits infrared rays. Thereby, the erroneous operation of the touch sensor is more effectively suppressed.

The present embodiment corresponds to a method of changing, applying, super-conceptualizing, or sub-conceptualizing a part of other embodiments. Therefore, some or all of the embodiments may be combined or replaced with other embodiments.

 Embodiment 7  

An example of an electronic device using a display device or a display module according to an embodiment of the present invention is shown in the present embodiment.

29A is a tablet type portable terminal 6200 including a housing 6221, a display device 6222, an operation button 6223, and a speaker 6224. A position input function can be added to the display device 6222 of one embodiment of the present invention. In addition, the position input function can be added by providing a touch panel in the display device. Alternatively, the position input function may be added by providing a photoelectric conversion element called a photo sensor in the pixel portion of the display device. In addition, the operation button 6223 can be used as a power switch for turning on the portable terminal 6200, a button for operating an application of the portable terminal 6200, a volume adjustment button, a switch for turning on/off the display device 6222, and the like. In addition, FIG. 29A shows an example in which the portable terminal 6200 includes four operation buttons 6223, but the number and configuration of the operation buttons that the portable terminal 6200 has are not limited thereto.

In addition, the portable terminal 6200 includes a photo sensor 6225X and a photo sensor 6225Y that detect the illuminance of the external light. The photo sensor 6225X and the photo sensor 6225Y are disposed on a bezel of the housing 6221. In particular, the photo sensor 6225X is disposed in one of the two short sides of the frame of the housing 6221, and the photo sensor 6225Y is disposed in one of the two long sides of the frame of the housing 6221. In one embodiment of the present invention, the illuminance of the external light can be detected using the photo sensor 6225X and the photo sensor 6225Y, and the switching of the display elements displayed on the display device 6222 can be adjusted based on the illuminance data.

In addition, the position at which the photo sensor 6225X and the photo sensor 6225Y are disposed is not limited to the portable terminal 6200 shown in FIG. 29A. For example, as in the portable terminal 6201 shown in FIG. 29B, the photo sensor 6225X may be disposed on both of the short sides of the frame of the housing 6221, and the photo sensor 6225Y is disposed in the frame of the housing 6221. Both of the long sides.

In addition, although not shown, the portable terminal 6200 shown in FIG. 29A may be provided with a sensor inside the housing 6221 (the sensor has functions of measuring factors such as force, displacement, position, speed, acceleration, Angular velocity, rotational speed, distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor, or infrared. In particular, by providing a measuring device having a sensor for measuring the inclination such as a gyro sensor or an acceleration sensor, the direction of the portable terminal 6200 shown in FIG. 29A can be determined (the portable terminal is opposite to the portable terminal) The screen display of the display device 6222 is automatically switched according to the direction of the portable terminal 6200 in which direction the vertical direction is directed.

The present embodiment corresponds to a method of changing, applying, super-conceptualizing, or sub-conceptualizing a part of other embodiments. Therefore, some or all of the embodiments may be combined or replaced with other embodiments.

 Embodiment 8  

30A to 30F illustrate specific examples of an electronic device that can be used for a portable terminal having a display device according to an embodiment of the present invention.

FIG. 30A illustrates a portable game machine including a housing 5001, a housing 5002, a display device 5003 according to an embodiment of the present invention, a display device 5004, a microphone 5005, a speaker 5006, and an operation according to an embodiment of the present invention. Key 5007, stylus pen 5008, and the like. Although the portable game machine shown in Fig. 30A includes two display devices, that is, the display device 5003 and the display device 5004, the number of display devices possessed by the portable game machine is not limited to two. By using the display device 5003 and the display device 5004 according to an embodiment of the present invention for a portable game machine, it is possible to display an image with high display quality on the display device 5003 regardless of the intensity of the external light in the use environment. And on the display device 5004, and power consumption can be suppressed.

FIG. 30B is a watch type portable terminal including a housing 5201, a display device 5202, a wristwatch strap 5203, a photo sensor 5204, a switch 5205, and the like according to an embodiment of the present invention. By using the display device 5202 according to an embodiment of the present invention for a watch type portable terminal, an image with high display quality can be displayed on the display device 5202 regardless of the intensity of external light in the use environment, and Power consumption can be suppressed.

30C is a tablet type personal computer including a housing 5301, a housing 5302, a display device 5303 according to an embodiment of the present invention, a photo sensor 5304, a photo sensor 5305, a switch 5306, and the like. The display device 5303 is supported by the housing 5301 and the housing 5302. Since the display device 5303 is formed using a substrate having flexibility, it can be bent. By changing the angle between the outer casing 5301 and the outer casing 5302 by means of the hinges 5307 and 5308, the display device 5303 can be folded in such a manner that the outer casing 5301 overlaps the outer casing 5302. Although not shown, an open/close sensor may be incorporated to use the above-described change in angle for information on the use condition of the display device 5303. By using the display device 5303 according to an embodiment of the present invention for a tablet type personal computer, an image with high display quality can be displayed on the display device 5303 regardless of the intensity of the external light in the use environment. Suppress power consumption.

FIG. 30D is a video camera including a housing 5801, a housing 5802, a display device 5803 according to an embodiment of the present invention, an operation key 5804, a lens 5805, a connecting portion 5806, and the like. The operation key 5804 and the lens 5805 are disposed in the housing 5801, and the display device 5803 is disposed in the housing 5802. Also, the outer casing 5801 and the outer casing 5802 are connected by a connecting portion 5806, and the angle between the outer casing 5801 and the outer casing 5802 can be changed by the connecting portion 5806. The image of the display device 5803 can also be switched according to the angle between the outer casing 5801 and the outer casing 5802 formed by the connecting portion 5806. By using the display device 5803 according to an embodiment of the present invention for a video camera, it is possible to display an image with high display quality on the display device 5803 regardless of the intensity of the external light in the use environment, and it is possible to suppress power consumption. .

Figure 30E is a watch type portable terminal including a housing 5701 having a curved surface and a display device 5702 according to an embodiment of the present invention. By using the flexible substrate for the display device 5702 according to an embodiment of the present invention, the outer casing 5701 having a curved surface can support the display device 5702, thereby providing a flexible, lightweight, and convenient watch type portable. Terminal. Further, by using the display device 5702 according to an embodiment of the present invention for a watch type portable terminal, an image with high display quality can be displayed on the display device 5702 regardless of the intensity of external light in the use environment. And can suppress power consumption.

Fig. 30F is a mobile phone in which a display device 5902, a microphone 5907, a speaker 5904, a camera 5903, an external connection portion 5906, and an operation button 5905 according to an embodiment of the present invention are disposed in a housing 5901 having a curved surface. By using the display device 5902 according to an embodiment of the present invention for a mobile phone, it is possible to display an image with high display quality on the display device 5902 regardless of the intensity of the external light in the use environment, and it is possible to suppress power consumption. .

The present embodiment corresponds to a method of changing, applying, super-conceptualizing, or sub-conceptualizing a part of other embodiments. Therefore, some or all of the embodiments may be combined or replaced with other embodiments.

 <Notes on the description of this manual, etc.>  

In the present specification and the like, ordinal numbers such as "first", "second", and "third" are added in order to avoid confusion of components. Therefore, the ordinal does not limit the number of components. Moreover, the ordinal does not limit the order of the components.

In this specification and the like, components are classified according to functions in block diagrams and are represented by blocks independent of each other. However, it is difficult to classify components according to functions in actual circuits and the like, and sometimes one circuit is related to a plurality of functions or a plurality of circuits related to one function. Therefore, the division of the blocks in the block diagram is not limited to the components described in the specification, but may be appropriately different depending on the situation.

In the drawings, the same component symbols are sometimes used to denote the same component, a component having the same function, a component formed of the same material, or a component formed at the same time, and the like, and the repeated description is sometimes omitted.

In the present specification and the like, when describing the connection relationship of the transistors, it is described as "one of the source and the drain" (or the first electrode or the first terminal) and "the other of the source and the drain" ( Or a second electrode or a second terminal). This is because the source and the drain of the transistor are changed depending on the structure or operating conditions of the transistor. Note that the source and drain of the transistor may be appropriately referred to as a source (drain) terminal or a source (drain) electrode or the like as the case may be.

Further, in the present specification and the like, the voltage and the potential can be appropriately changed. The voltage refers to the potential difference from the reference potential. For example, when the reference potential is the ground potential (ground potential), the voltage can be referred to as the potential. The ground potential does not necessarily mean 0V. Note that the potentials are relative, and the potential supplied to the wiring or the like sometimes varies depending on the reference potential.

In the present specification and the like, the switch refers to an element having a function of controlling whether or not a current flows by changing to an on state (on state) or a non-conduction state (off state). Alternatively, a switch refers to an element having the function of selecting and switching a current path.

For example, an electric switch or a mechanical switch or the like can be used. In other words, the switch is not limited to a specific component as long as it can control the current.

When a transistor is used as a switch, the "on state" of the transistor means a state in which the source and the NMOS of the transistor are extremely electrically short-circuited. In addition, the "non-conducting state" of the transistor means a state in which the source of the transistor is extremely electrically disconnected from the crucible. When the transistor is used only as a switch, there is no particular limitation on the polarity (conductivity type) of the transistor.

In the present specification and the like, a pixel refers to, for example, one unit capable of controlling brightness. Thus, as an example, a pixel refers to a color unit and the color unit is used to display brightness. Therefore, in the case of using a color display device composed of color units such as R (red), G (green), and B (blue), the minimum unit of the pixel is set to be a pixel of R, a pixel of G, and B. A pixel composed of three pixels of pixels. Sometimes, each pixel of RGB is referred to as a sub-pixel, and sub-pixels of RGB are collectively referred to as a pixel.

Furthermore, the color unit is not limited to three colors, and three or more colors may be used, for example, RGBW (W is white) or yellow (yellow), cyan (myan), magenta (magenta), etc. for RGB. .

In the present specification and the like, "A and B are connected" include a case where A and B are electrically connected in addition to the case where A and B are directly connected. Here, "A and B are electrically connected" means a case where an electrical signal can be exchanged between A and B when an object having a certain electrical action exists between A and B.

Claims (6)

 A display device comprising: a signal generating circuit; a first gate driver; a second gate driver; and a display panel having pixels, wherein the pixel comprises a liquid crystal element, a light emitting element, and a first pixel that controls display of the liquid crystal element a circuit and a second pixel circuit for controlling display of the light emitting element, the first gate driver having a function of outputting a first scan signal to the first pixel circuit, the second gate driver having a second output of the second pixel circuit a function of the scan signal, and the signal generating circuit has a function of outputting a signal to the second gate driver that stops outputting the second scan signal for controlling the second pixel circuit of an arbitrary row signal.    A display device comprising: a signal generating circuit; a first gate driver; a second gate driver; and a display panel having pixels, wherein the pixel comprises a liquid crystal element, a light emitting element, and a first pixel that controls display of the liquid crystal element a circuit and a second pixel circuit for controlling display of the light emitting element, the first gate driver having a function of outputting a first scan signal to the first pixel circuit, the second gate driver having a second output of the second pixel circuit a function of the second scan signal, and the signal generating circuit has a function of outputting a signal for stopping output of the second scan signal for controlling the second pixel circuit of an arbitrary row of the second gate driver and having the same A gate driver outputs a function of stopping a signal outputting the first scan signal for controlling the first pixel circuit of each row.    A display device according to claim 1 or 2, wherein the first pixel circuit and the second pixel circuit comprise a transistor, and the transistor has a metal oxide in the semiconductor layer.    The display device of claim 3, wherein the transistor included in the first pixel circuit is disposed in the same layer as the transistor included in the second pixel circuit.    The display device according to any one of claims 1 to 4, wherein the liquid crystal element includes a reflective electrode provided with an opening, having a function of reflecting external light for display by the reflective electrode, and the light emitting element has a through-opening The function of emitting light for display.    An electronic device comprising: the display device according to any one of claims 1 to 5; a casing; and a power button, wherein the display device has a function of switching between the first display mode and the second display mode as follows The first display mode outputs a signal for outputting the first pixel circuit and the second scan signal of the first pixel circuit and the second pixel circuit for controlling each row to the first gate driver and the first a display mode of the two gate driver, the second display mode is a display mode of outputting a signal for stopping output of the second scan signal of the second pixel circuit of an arbitrary row to the second gate driver, and The control of the first display mode and the control of the second display mode can be switched by operation corresponding to the power button.