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TW201732930A - 半導體裝置之形成方法 - Google Patents

半導體裝置之形成方法 Download PDF

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Publication number
TW201732930A
TW201732930A TW105136103A TW105136103A TW201732930A TW 201732930 A TW201732930 A TW 201732930A TW 105136103 A TW105136103 A TW 105136103A TW 105136103 A TW105136103 A TW 105136103A TW 201732930 A TW201732930 A TW 201732930A
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Taiwan
Prior art keywords
metal
interlayer dielectric
dielectric layer
layer
trench
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TW105136103A
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English (en)
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張世明
賴志明
劉如淦
高蔡勝
李忠儒
包天一
眭曉林
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台灣積體電路製造股份有限公司
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Publication of TW201732930A publication Critical patent/TW201732930A/zh

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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

一種半導體裝置之形成方法,其包括形成由第一金屬材料部分填充之溝槽,上述溝槽形成於第一層間介電層之中。上述方法亦包括以犧牲材料填充上述溝槽之剩餘部分、沉積緩衝層於第一層間介電層之上、圖案化緩衝層以於緩衝層中形成孔洞而露出犧牲材料、以及移除犧牲材料。

Description

半導體裝置之形成方法
本揭露係有關於一種半導體裝置之形成方法,且特別有關於形成導孔之方法。
在半導體積體電路(IC)工業中,積體電路材料及設計之技術進步產生了許多積體電路世代,其中每一世代具有比上一世代更小及更複雜的電路。在積體電路進展的過程中,功能密度(亦即,每一晶片面積之互連裝置的數量)普遍地增加,同時幾何尺寸(亦即,製程上可產生之最小之元件或線)亦縮小。通常上述尺寸縮小的製程可增加生產效率及降低相關成本而帶來好處。上述之尺寸縮小也增加了積體電路製程及製造的複雜性。
形成積體電路其中之一個層面係為形成尺寸小且垂直之金屬線以連接一水平金屬線層至不同之水平金屬線層。這樣的垂直金屬線通常稱作導孔(via)。因為積體電路之小尺寸的性質,將導孔圖案與前一個形成之膜層對準並不容易。例如,在形成導孔的時候,將形成導孔所使用之圖案正確地對準以使導孔連接適當之金屬線是很重要的。即使導孔與其下方適當之金屬線接觸,些微的錯位(misalignment)將可能造成導孔過於接近相鄰之金屬線。為了避免此問題,需使用製程方法 以形成對準(align)較佳且不會過於接近不欲接觸之金屬線之導孔。
本揭露包括一種半導體裝置之形成方法,其包括:形成由第一金屬材料部分填充之溝槽,上述溝槽係形成於第一層間介電層之中;以犧牲材料填充上述溝槽之剩餘部分;沉積緩衝層於第一層間介電層之上;圖案化緩衝層以於緩衝層中形成孔洞而露出犧牲材料;移除犧牲材料。
本揭露亦包括一種半導體裝置之形成方法,其包括:形成由第一金屬材料部分填充之溝槽,上述溝槽係形成於第一層間介電層之中;以犧牲材料填充上述溝槽之剩餘部分;沉積第二層間介電層於第一層間介電層之上;圖案化第二層間介電層以於第二層間介電層中形成孔洞而露出犧牲材料;以及移除犧牲材料以形成溝槽凹口(trench recess)。
本揭露亦包括一種半導體裝置,其包括:第一金屬特徵,形成於第一介電層中;第二金屬特徵,形成於第二介電層中,其中第二介電層設置於第一介電層之上;以及導孔,連接第一金屬特徵至第二金屬特徵,其中上述導孔之上部從上述導孔之下部偏移。
100‧‧‧積體電路結構
102‧‧‧第一層間介電層
104‧‧‧第一溝槽
105‧‧‧第二溝槽
106‧‧‧第一金屬線
107‧‧‧第二金屬線
108‧‧‧犧牲材料
109‧‧‧平面
110‧‧‧化學機械研磨製程
112‧‧‧緩衝層
114‧‧‧光阻
115‧‧‧蝕刻製程
116‧‧‧開口
118‧‧‧孔洞
120‧‧‧金屬導孔
138、140‧‧‧距離
122‧‧‧第二層間介電層
123‧‧‧溝槽
124‧‧‧金屬線
126‧‧‧介面
128‧‧‧蝕刻停止層
202‧‧‧第二層間介電層
204、206‧‧‧孔洞
205‧‧‧溝槽
208‧‧‧金屬線
210‧‧‧導電導孔
300、400‧‧‧方法
302、304、306、308、310、312、314、316、402、404、406、408、410、412、414‧‧‧步驟
以下將配合所附圖式詳述本揭露之各面向。應注意的是,依據在業界的標準做法,各種特徵並未按照比例繪製且僅用以說明例示。事實上,可能任意地放大或縮小元件的尺寸,以清楚地表現出本揭露的特徵。
第1A至1L圖係根據此處所描述之原理的實施例,繪示出形成導孔之方法,上述導孔連接至部分填充之溝槽中之金屬線。
第2A至2E圖係根據此處所描述之原理的實施例,繪示出使用雙鑲嵌製程形成導孔之方法,上述導孔連接至部分填充之溝槽中之金屬線。
第3圖係為根據於此描述之原理的實施例所繪示之經由使用緩衝層而形成導孔之方法的流程圖,上述導孔連接至部分填充之溝槽中之金屬線。
第4圖係為根據於此描述之原理的實施例所繪示之經由使用雙鑲嵌製程而形成導孔之方法的流程圖,上述導孔連接至部分填充之溝槽中之金屬線。
以下公開許多不同的實施方法或是實施例來實行所提供之標的之不同特徵,以下描述具體的元件及其排列的實施例以闡述本揭露。當然這些實施例僅用以例示,且不該以此限定本揭露的範圍。例如,在說明書中提到第一特徵形成於第二特徵之上,其包括第一特徵與第二特徵是直接接觸的實施例,另外也包括於第一特徵與第二特徵之間另外有其他特徵的實施例,亦即,第一特徵與第二特徵並非直接接觸。此外,在不同實施例中可能使用重複的標號或標示,這些重複僅為了簡單清楚地敘述本揭露,不代表所討論的不同實施例及/或結構之間有特定的關係。
此外,其中可能用到與空間相關用詞,例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及 類似的用詞,這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係,這些空間相關用詞包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。
如前文所述,需形成與適當之金屬線接觸良好之導孔,且其不會過於接近不欲接觸之相鄰金屬線。根據於此描述之原理,填充部分之溝槽以形成下方金屬層之金屬線。換句話說,上述溝槽僅部分以例如金屬材料之導電材料填充。因此,若導孔與金屬線之間存在有錯位,仍有額外的垂直距離以分隔導孔及相鄰之金屬線。
第1A至1L圖繪示出形成積體電路結構100之製程,積體電路結構100包括形成於半導體基板(未繪示)上且設計來連接各種裝置以形成積體電路之互連結構。在一些實施例中,半導體基板係為矽基板。在一些實施例中,半導體基板可替代地或額外地包括其他半導體材料,例如鍺、矽鍺、砷化鎵、或其他適當之半導體材料。在一些實施例中,半導體基板可額外地包括埋置(embedded)介電材料層以提供適當之隔離功能。互連結構包括以導孔特徵垂直連接之複數個金屬層中之金屬線。在所描述之本實施例中,積體電路結構100包括連接至導線(例如:部分填充之溝槽中的金屬線)之導孔。
第1A圖為兩導線(例如:金屬線106、107)之剖面圖。上述兩金屬線106、107可為形成於介電層中(例如:層間介 電層)之金屬層中(例如:metal one)的金屬圖案之部分。根據本實施例,第一溝槽104及第二溝槽105係形成於第一層間介電層(Interlayer Dielectric Layer,簡稱ILD)102中。以一金屬材料(例如:用以形成第一金屬線106之金屬材料)部分填充第一溝槽104,而以上述金屬材料部分填充第二溝槽105而形成第二金屬線107。金屬線106及107之上表面皆與平面109共平面。第一金屬線及第二金屬線可包括多個膜層。在一些實施例中,上述金屬線(106及107)包括形成於溝槽側壁上之阻障層。在上述實施例中,金屬線(106及107)可進一步包括形成於阻障層上且填充上述溝槽之塊狀(bulk)金屬。舉例而言,阻障層包括氮化鈦、氮化鉭、或其他適當之材料。舉例而言,塊狀材料包括銅、或其他適當之金屬或金屬合金。
層間介電層102可形成於如半導體晶圓(Wafer)之半導體基板(未繪示)之頂部。半導體基板可包括各種電路裝置,例如形成於其上之電晶體。上述電路元件係於前段製程(front end of line)中形成。在一些情況下,互連結構係於後段製程(back end of line)形成於電路裝置之上。互連結構包括多層金屬層中之水平金屬線。位於不同金屬層中之金屬線係經由稱作導孔(via)之垂直導線相互連接。第1A圖繪示出層間介電層102中之上述金屬層之金屬線的一部分。
可以任何適當之介電材料形成層間介電層102。在一些實施例中,層間介電層102包括氧化矽、氟矽玻璃(fluorinated silicate glass,簡稱FSG)、有機矽酸鹽玻璃(organosilicate glass,簡稱OSG)、碳摻雜氧化矽(carbon doped silicon oxide)、乾凝膠(Xerogel)、氣凝膠(Aerogel)、氟化非晶碳(amorphous fluorinated carbon)、聚醯亞胺(polyimide)、多孔材料及/或其他材料。可依照蝕刻選擇性選擇形成層間介電層102之材料。舉例而言,如後文中將詳述之內容,可能需要一些對於層間介電層102幾乎不具有蝕刻效果之蝕刻製程。在一些其他的實施例中,層間介電層102可更包括不同介電材料之蝕刻停止層以提供蝕刻選擇性。
可以各種方式形成部分填充之溝槽104、105。在一些實施例中,以鑲嵌製程(damascene process)形成金屬層之金屬線(例如:106及107)。使用包括光微影之圖案化製程形成溝槽。具體而言,將光阻塗佈(apply)、曝光、以及顯影。接著施行蝕刻製程以將光阻中之圖案轉移至層間介電層102而形成溝槽。舉例而言,可使用硬罩幕,使得溝槽圖案先從圖案化光阻層傳遞至硬罩幕,再進一步從硬罩幕傳遞至層間介電層102。接著,沉積金屬材料至溝槽104、105中。上述之沉積步驟可填滿溝槽並有多餘之材料溢出溝槽之外。因此,可施行化學機械研磨製程以移除多餘之金屬材料並露出層間介電層102而留下完全填滿之溝槽。接著,施行蝕刻製程以部分地凹蝕上述金屬材料而形成部分填充之溝槽104、105。可選擇上述蝕刻製程以有效地移除上述金屬材料而保留層間介電層102實質上地完整。
可使用其他方法以形成部分填充之溝槽。舉例而言,可於未對應金屬特徵之區域中沉積額外之層間介電材料或其他適當之介電材料(例如:以自對準成長(self-aligned growth)) 而非凹蝕金屬材料。亦可考慮使用其他方法。
第1B圖繪示出沉積犧牲材料108之步驟。可選擇容易經由特定蝕刻製程移除(例如:濕蝕刻製程)之犧牲材料108。亦可選擇低成本之犧牲材料。在一些實施例中,使用聚合物材料(polymeric material)作為犧牲材料並以適當之技術(例如:旋轉塗佈製程)將之填充於溝槽中。
第1C圖繪示出化學機械研磨製程110,其係用以移除層間介電層102之表面上的犧牲材料108而露出第一層間介電層102。上述製程保留了溝槽104、105上部中之犧牲材料108。可替代地使用其他製程(例如:回蝕刻)以移除層間介電層102之表面上的犧牲材料108。
第1D圖繪示出於第一層間介電層102上沉積緩衝層112之步驟。在一些實施例中,緩衝層112包括不同於層間介電層102之介電材料,使得後續之蝕刻製程可選擇性蝕刻緩衝層112而未蝕刻層間介電層102。舉例而言,緩衝層112包括介電材料,例如:以適當之技術(例如:化學氣相沉積製程)形成於層間介電層102上之氮化矽或碳化矽。接著,形成光阻114於緩衝層112之上。第1D圖繪示出圖案化之光阻114。可使用一般的微影製程圖案化光阻。例如,可經由圖案化光罩將上述光阻暴露於光源。接著,顯影上述光阻以移除上述光阻之特定部分。
第1E圖繪示出光阻中之圖案轉移至緩衝層112後之積體電路結構。具體而言,可使用蝕刻製程以蝕刻緩衝層112之開口中之緩衝層112之露出之部分。因此,光罩中之圖案轉移至緩衝層以形成緩衝層112中之開口(opening)或孔洞 (hole)116而露出金屬線106上之犧牲材料108。開口116對應將形成之導孔之位置,上述導孔係用以連接金屬線106至其上方金屬層之金屬線。舉例而言,可使用異向性蝕刻製程(例如:乾蝕刻製程)以形成緩衝層112中之開口116。乾蝕刻製程通常使用離子轟擊及化學反應以移除特定類型之材料。之後,以適當之製程移除光阻,例如:濕式去光阻(wet stripping)或電漿灰化(plasma ashing)。
第1F圖繪示出蝕刻製程115,其係用以移除經由孔洞116露出之犧牲材料108。上述製程形成了向下延伸至金屬線106之孔洞118。上述蝕刻製程可為等向性蝕刻製程(例如:濕蝕刻製程)。濕蝕刻製程使用化學蝕刻劑以移除特定類型之材料。蝕刻製程115係用以選擇性移除犧牲材料108而保留第一層間介電層102及緩衝層112實質上地完整。
第1G圖繪示出導電特徵120(例如:形成於孔洞118中之金屬導孔)。可沉積金屬材料於晶圓之表面上,接著進行化學機械研磨製程以露出緩衝層112之上部而形成金屬導孔120。上述製程使得孔洞118中之金屬材料形成導孔120及電路中之任何其他導孔。在一些實施例中,可使用銅或鎢填充孔洞118以形成金屬導孔120。在上述實施例中,可更進一步以包括濺鍍形成銅晶種層、電鍍(plating)於孔洞120中形成塊狀銅的程序填充銅。在一些實施例中,於填充金屬之前,可沉積阻障層(例如:鉭、氮化鉭、鈦、氮化鈦、或上述之組合)於孔洞120之側壁上。
在各個實施例中,以上述之方式形成金屬導孔提 供許多好處。舉例而言,在圖案化導孔至緩衝層112中的時候,可能存在些微的錯位(金屬線106及其上方之導孔之間)。若沒有使用於此描述之原理,些微的錯位可能造成導孔過於靠近相鄰之金屬線107。具體而言,距離138可能過於靠近金屬線107。因此,所設計之電路需具有較多之金屬線之間的空間以容許預期之錯位問題。
然而,若使用於此描述之原理,部分填充之溝槽使得導孔與相鄰之金屬線107具有額外之距離。具體而言,距離140同時包括水平距離及垂直距離。因此,若使用於此描述之原理,所設計之電路可具有較靠近在一起之金屬線。
此外,因為錯位減少了接觸面積,使得金屬線106及其上方之導孔之間的接觸電阻增加。藉由應用所揭露之方法,因為上述之錯位,金屬導孔120包括上部及下部兩部分,且其介面位於層間介電層102之上表面。上述下部及上部彼此之間具有因上述之錯位所形成之偏移(offset)。金屬導孔120之上部係在層間介電層102之上,而其下部則埋置於層間介電層102之中。上述下部係自對準於金屬線106之上,因而最大化接觸面積而最小化接觸電阻。特別地,金屬導孔120係在金屬線106及107之上。
第1H圖繪示出移除緩衝層112之移除製程。在一些實施例中,亦移除相鄰金屬線107上之犧牲材料108。移除製程可包括蝕刻製程,其係用來移除緩衝層112而保留第一層間介電層102及金屬導孔120實質上地完整。
第1I圖繪示出於第一層間介電層102上形成第二層 間介電層122之步驟。在本實施例中,可以與第一層間介電層102相同之材料形成第二層間介電層122。然而,在一些實施例中,可以與第一層間介電層102不同之材料形成第二層間介電層122。第二層間介電層122係用以支撐第二金屬層並隔離第二金屬層之金屬線。因此,可於第二層間介電層中形成一組金屬線。一般而言,形成溝槽於第二層間介電層122中以形成上述金屬線。
第1J圖繪示出於第二層間介電層122中形成溝槽123之步驟。在本實施例中,形成溝槽123,使其垂直於第一層間介電層102中之金屬線106、107。以包括微影圖案化及蝕刻之適當步驟形成溝槽123。溝槽123露出導孔120,使得金屬材料形成於溝槽123中的時候,上述金屬係直接接觸導孔120因而電性連接至導孔120。
第1K圖繪示出形成金屬材料於溝槽123中以於第二層間介電層122中形成金屬線124。因此,第二層間介電層122中之金屬線124連接至第一層間介電層102中之金屬線106。由於使用於此所述之原理,使得導孔120位於第二層間介電層122中之上部相對於導孔120位於第一層間介電層102中之下部具有因本徵(intrinsic)錯位而形成之偏移。易言之,導孔120可具有一下部在第一層間介電層102中以及一上部在第二層間介電層122中。上述偏移與第一層間介電層102及第二層間介電層122之介面126共平面。在本實施例中,上述偏移之距離小於導孔120之寬度。導孔120之下部係自對準於金屬線。舉例而言,若將形成額外之金屬層,則金屬線124可僅部分填充溝槽123。 因此,可使用與前文所述相同之技術以形成額外之金屬層。
第1L圖繪示出蝕刻停止層128位於第一層間介電層102及第二層間介電層122之間的實施例。舉例而言,於形成第一層間介電層102之後及沉積緩衝層112之前沉積蝕刻停止層128。然而,可於製造流程中其他適當之時機應用蝕刻停止層128。蝕刻停止層128係用以避免對第一層間介電層不想要之蝕刻。例如,在蝕刻第二層間介電層122以圖案化第二層間介電層122的時候,不希望蝕刻到第一層間介電層102。所設計之蝕刻停止層128係實質上不會受到用來蝕刻第二層間介電層122之蝕刻劑的影響。
在一實施例中,緩衝層112可為層間介電層。上述層間介電層之蝕刻選擇性可不同於第一層間介電層102。在上述的實施例中,可保留緩衝層112而不是以第二層間介電層122將其取代。符合第1J至1L圖之上述步驟則可於緩衝層112上進行,而不是於第二層間介電層122上進行。
第2A至2E圖繪示出形成積體電路結構200之製程,上述製程使用部分填充之溝槽及雙鑲嵌步驟以形成連接下方金屬層之金屬線至上方金屬層之金屬線之導電導孔。此製程與前文所述之製程類似,不同的地方在於以第二層間介電層202取代緩衝層(例如:第1圖之112)。第2A圖繪示出於導電導孔形成之前,形成第二層間介電層202於第一層間介電層102之上。類似於前述之製程,塗佈光阻層114於第二層間介電層202之頂部。接著,使用各種光微影製程圖案化光阻114。
第2B圖繪示出光阻之圖案傳遞至第二層間介電層 202並形成孔洞204後之積體電路結構200。孔洞204延伸穿過整個第二層間介電層202以露出第一層間介電層102及犧牲材料108。在本實施例中,用來形成第二層間介電層202之材料不同於第一層間介電層102之材料。進一步而言,選擇相異之層間介電層材料以使其對於彼此具有蝕刻選擇性。藉此,用以形成孔洞204之蝕刻製程實質上不影響第一層間介電層102。之後,可以適當之技術移除光阻114,例如:濕式去光阻或電漿灰化。
第2C圖繪示出使用蝕刻製程(例如:濕蝕刻製程)以移除犧牲層108之步驟。上述製程形成從第二層間介電層202之頂部延伸至金屬線106之頂部之孔洞206。可選擇用以移除犧牲材料108之蝕刻製程,使其有效地移除犧牲材料而實質上未影響第二層間介電層202、第一層間介電層102、或金屬線106。
第2D圖繪示出於第二層間介電層202中形成溝槽205之步驟。在本實施例中,上述溝槽垂直於金屬線106、107。溝槽205亦與孔洞206交叉(intersect)。藉此,在沉積金屬材料的時候,將填充溝槽205以及孔洞206。
第2E圖繪示出上述沉積金屬以填充溝槽205之步驟。所沉積之金屬因而形成金屬線208及導電導孔210。金屬線208可為於第二層間介電層202中形成金屬圖案之諸多金屬線之其中之一。導電導孔210提供下方金屬層之金屬線106與上方金屬層之金屬線208之間的電性連接。因為使用單一沉積金屬之步驟同時形成導孔及金屬線,其可稱為雙鑲嵌製程。舉例而言,若將形成額外之金屬層,則金屬線208可僅部分填充溝槽205。因此,可使用與前文所述相同之技術以形成額外之金屬 層。
在以前述之方式形成導孔210之後,導孔210位於第二層間介電層202中之上部將從導孔210位於第一層間介電層102中之下部偏移。易言之,導孔210可具有一下部在第一層間介電層102中以及一上部在第二層間介電層202中。上述偏移之距離小於導孔210之寬度。此外,上述偏移與第一層間介電層102及第二層間介電層202之介面共平面。在一些實施例中,可以類似於前述伴隨第1L圖之內文中之蝕刻停止層128之方式使用一蝕刻停止層。
以上述之方式形成導孔210提供許多好處。舉例而言,在圖案化導孔210至第二層間介電層202中的時候,可能存在些微的錯位。若沒有使用於此描述之原理,些微的錯位可能造成導孔過於靠近相鄰之金屬線107。因此,所設計之電路需具有較多之金屬線之間的空間以容許預期之錯位問題。然而,若使用於此描述之原理,部分填充之溝槽使得導孔與相鄰之金屬線107之間具有額外之距離。具體而言,上述距離同時包括水平距離及垂直距離。因此,若使用於此描述之原理,所設計之電路可具有較靠近在一起之金屬線。
第3圖繪示出形成導孔之方法300之流程圖,上述導孔連接至部分填充之溝槽中之金屬線。上述方法使用緩衝層。根據本實施例,方法300包括步驟302以形成以第一金屬材料部分填充之溝槽。上述溝槽係形成於第一層間介電層中。舉例而言,施行包括光微影之圖案化製程以形成部分填充之溝槽。具體而言,塗佈光阻、曝光及顯影。接著施行蝕刻製程以 轉移光阻中之圖案至層間介電層而形成溝槽。接著,沉積金屬材料至上述溝槽之中。上述之沉積步驟可填滿溝槽並有多餘之材料溢出溝槽之外。因此,可施行化學機械研磨製程以移除多餘之金屬材料並露出層間介電層而留下完全填滿之溝槽。接著,施行蝕刻製程以部分移除上述金屬材料而形成部分填充之溝槽。
方法300更包括步驟304,其係以犧牲材料填充上述溝槽之剩餘部分。犧牲材料可為低成本且容易經由如濕蝕刻之移除製程移除之材料。
方法300更包括步驟306,以沉積緩衝層於第一層間介電層之上。緩衝層係為暫時性之膜層且將於後續被移除。緩衝層係由相對於第一層間介電層可選擇性蝕刻之材料形成。
方法300更包括步驟308,以圖案化緩衝層而於緩衝層中形成孔洞以露出犧牲材料。可經由包括光微影製程之各種製造流程完成上述步驟。接著,於步驟310,可移除犧牲材料。舉例而言,使用濕蝕刻製程以移除犧牲材料。移除犧牲材料露出了形成於部分填充之溝槽中之金屬線。
方法300更包括步驟312,其係以第二金屬材料填充上述溝槽之剩餘部分及上述孔洞以形成導孔。在一實施例中,接著施行化學機械研磨製程以移除任何不在上述孔洞中之多餘之金屬材料並露出緩衝層之上表面。然而,導孔仍然維持在相同之位置。
方法300更包括步驟314,其係以第二層間介電層取代緩衝層。上述步驟首先以蝕刻製程移除緩衝層,所設計之 蝕刻步驟係用以移除緩衝層而保留第一層間介電層及導孔實質上地完整。接著,沉積第二層間介電材料。然後可使用化學機械研磨製程以平坦化第二層間介電層之表面。
方法300更包括於第二層間介電層中形成金屬線之步驟。進一步而言,於第二層間介電層中形成金屬圖案。金屬圖案包括與導孔接觸之金屬線。舉例而言,於第二層間介電層中形成一組溝槽以形成金屬圖案。上述溝槽可延伸至足夠露出導孔之上表面之深度。因此,在以金屬材料填充溝槽而形成金屬線的時候,金屬線電性連接導孔。因而導孔連接其下方之金屬線至其上方之金屬線。
第4圖繪示出經由使用雙鑲嵌製程而形成導孔之方法400的流程圖,上述導孔連接至部分填充之溝槽中之金屬線。根據本實施例,方法400包括步驟402以形成以第一金屬材料部分填充之溝槽。上述溝槽係形成於第一層間介電層中。可以前述之方式形成上述溝槽。
方法400更包括步驟404,其係以犧牲材料填充上述溝槽之剩餘部分。犧牲材料可為低成本且容易經由如濕蝕刻之移除製程移除之材料。
方法400更包括步驟406,以沉積第二層間介電層於第一層間介電層之上。可以不同於第一層間介電層之材料形成第二層間介電層,因而相對於第一層間介電材料,可選擇性蝕刻第二層間介電材料。
方法400更包括步驟408,以圖案化第二層間介電層而於第二層間介電中形成孔洞以露出犧牲材料。可經由包括 光微影製程之各種製造流程完成上述步驟。接著,於步驟410,可移除犧牲材料。舉例而言,使用濕蝕刻製程以移除犧牲材料。移除犧牲材料露出了形成於部分填充之溝槽中之金屬線。
方法400更包括步驟412以圖案化第二層間介電層而形成用於金屬圖案之溝槽。至少一個上述溝槽與形成於第二層間介電層中之上述孔洞交叉。因此,上述孔洞將從溝槽之底部向下延伸至形成於第一層間介電層中之部分填充之溝槽中之金屬線之上表面。
方法400更包括步驟414,其係以金屬材料填充上述溝槽及孔洞,而於單一沉積製程中形成孔洞中之導孔及導孔上之金屬線。上述製程稱作雙鑲嵌製程。舉例而言,施行化學機械研磨製程於所沉積之金屬的頂部以移除多餘之金屬並露出第二層間介電層之上表面。
前文所述之技術描述了第一層間介電層中之第一金屬線及第二層間介電層中之第二金屬線之間的導孔。然而,前文所述之方法及裝置亦可應用於任何堆疊膜層中之兩膜層。舉例而言,在一些情況下,特定之電路後段製程部分可具有八層金屬層,其任一皆可使用於此所述之原理,使得下方之膜層形成於部分填充之溝槽中。藉此,在後續之膜層及導孔形成的時候,導孔與不欲接觸之相鄰金屬線之間將具有較大之距離。此外,雖然前文之描述使用金屬圖案、金屬線、及金屬導孔,應理解的是,可使用其他導電材料取代金屬。
以第3及4圖所述之方式形成導孔提供了許多好處。舉例而言,在圖案化導孔至緩衝層或第二層間介電層中的 時候,可能存在些微的錯位。若沒有使用於此描述之原理,些微的錯位可能造成導孔過於靠近相鄰之金屬線。因此,所設計之電路需具有較多之金屬線之間的空間以容許預期之錯位問題。然而,若使用於此描述之原理,部分填充之溝槽使得導孔與相鄰之金屬線之間具有額外之距離。具體而言,上述距離同時包括水平距離及垂直距離。因此,若使用於此描述之原理,所設計之電路可具有較靠近在一起之金屬線。
根據一實施例,一種半導體裝置之形成方法包括形成由第一金屬材料部分填充之溝槽。上述溝槽係形成於第一層間介電層之中。上述方法亦包括以犧牲材料填充上述溝槽之剩餘部分、沉積緩衝層於第一層間介電層之上、圖案化緩衝層以於緩衝層中形成孔洞而露出犧牲材料、以及移除犧牲材料。
根據一實施例,一種半導體裝置之形成方法包括形成由第一金屬材料部分填充之溝槽。上述溝槽係形成於第一層間介電層之中。上述方法亦包括以犧牲材料填充上述溝槽之剩餘部分、沉積第二層間介電層於第一層間介電層之上、圖案化第二層間介電層以於第二層間介電層中形成孔洞而露出犧牲材料、以及移除犧牲材料。
根據一實施例,一種半導體裝置包括形成於第一介電層中且包括第一金屬線之第一金屬圖案、形成於第二介電層中且包括第二金屬線之第二金屬圖案。第二介電層設置於第一介電層之上。上述半導體裝置亦包括導孔,其連接第一金屬圖案之第一金屬線至第二金屬圖案之第二金屬線。其中導孔之上部從導孔之下部偏移。
上述內容概述許多實施例的特徵,因此任何所屬技術領域中具有通常知識者,可更加理解本揭露之各面向。任何所屬技術領域中具有通常知識者,可能無困難地以本揭露為基礎,設計或修改其他製程及結構,以達到與本揭露實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通常知識者也應了解,在不脫離本揭露之精神和範圍內做不同改變、代替及修改,如此等效的創造並沒有超出本揭露的精神及範圍。
102‧‧‧層間介電層
106‧‧‧第一金屬線
107‧‧‧第二金屬線
108‧‧‧犧牲材料
112‧‧‧緩衝層
120‧‧‧金屬導孔
138、140‧‧‧距離

Claims (1)

  1. 一種半導體裝置之形成方法,包括:形成由一第一金屬材料部分填充之一溝槽,該溝槽係形成於一第一層間介電層之中;以一犧牲材料填充該溝槽之剩餘部分;沉積一緩衝層於該第一層間介電層之上;圖案化該緩衝層以於該緩衝層中形成一孔洞而露出該犧牲材料;以及移除該犧牲材料。
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