TW201715338A - Memory device and control method therefor - Google Patents

Abstract

A memory device is provided. The memory device includes a memory device, a plurality of word lines, a plurality of bit lines, a first decoder, a second decoder, and a control circuit. Each word line is coupled to memory cells on one row. Each bit line is coupled to memory cells on one column. The first decoder selects one word line according to an address signal and a first control signal. The control circuit generates the first control signal according to a first clock signal and further generates the second control signal according to a second clock signal. During a period when the first decoder selects one word line, the second decoder selects two bit lines according to the address signal and a second control signal, and the memory device performs a read/write operation to each of the two bit lines.

Description

Memory device and control method thereof

The present invention relates to a memory device, and more particularly to a static random access memory device capable of reducing execution by continuously performing a plurality of read/write operations on a memory cell on a word line. The number of pre-charges to reduce power consumption.

In general, the control circuit of the SRAM device controls the decoder based on a single clock signal to select a corresponding memory cell. Whenever the clock signal is positively triggered, the control circuit locks the address once to select the corresponding word line and bit line (ie, select the corresponding memory cell). At this time, the memory device performs a precharge operation on the corresponding bit line first, and then performs a bit read/write operation on the memory cell. Therefore, it can be known that the memory device performs a precharge operation every time the pulse signal is positively triggered. However, the precharge operation causes a glitch current to occur on the word line and the bit line. Referring to FIG. 1 , when the positive pulse signal CLK is triggered by a positive edge, the accompanying surge current instantaneously pulls down the power supply current I _VDD , thereby increasing the power consumption of the memory device during operation.

An embodiment of the present invention provides a memory device including a memory array, a complex digital element line, a complex bit line, a first decoder, a second decoder, and a control circuit. The memory array includes a plurality of memory cells and a complex The number of memory cells is a complex memory cell. Each word line is coupled to a memory cell on a memory cell. Each bit line is coupled to a memory cell on a memory cell line. The first decoder receives the address signal and the first control signal, and selects a word line according to the address signal and the first control signal. The second decoder receives the address signal and the second control signal. The control circuit receives the first clock signal and the second clock signal. The control circuit generates a first control signal according to the first clock signal, and generates a second control signal according to the second clock signal. During a period in which the first decoder selects the word line according to the address signal and the first control signal, the second decoder selects at least two bit lines according to the address signal and the second control signal, and the memory device At least two bit lines each perform a read/write operation.

An embodiment of the present invention provides a control method for a memory device. The memory device includes a memory array, complex digital lines coupled to the memory array, and complex bit lines coupled to the memory array. The control method includes the steps of: receiving a first clock signal and a second clock signal; generating a first control signal according to the first clock signal; generating a second control signal according to the second clock signal; And an enable state of the first control signal to select one of the word lines; during the selection of one of the word lines according to the address signal and the first control signal, according to the address signal and the second Controlling an enable state of the signal to select at least two of the bit lines; and performing a read/write operation on each of the selected bit lines.

1‧‧‧ memory device

10‧‧‧ memory array

11, 12‧‧‧ decoder

13‧‧‧Control circuit

142‧‧‧Write-read circuit

15‧‧‧Precharge circuit

100‧‧‧ memory cells

ADD‧‧‧ address signal

BL0...BLY‧‧‧ bit line

CCLK, RCLK‧‧‧ clock signal

CEB, WEB‧‧‧ enable signal

DIN, DOUT‧‧‧ data

S13R, S13C, S14‧‧‧ control signals

S40...S46‧‧‧ method steps

WL0...WLX‧‧‧ character line

Figure 1 is a schematic diagram showing the clock signal and power supply current of a conventional memory device.

Fig. 2 shows a memory device in accordance with an embodiment of the present invention.

Figure 3 is a diagram showing the clock signal and power supply current of the memory device in accordance with an embodiment of the present invention.

Figure 4 is a diagram showing a control method for a memory device in accordance with an embodiment of the present invention.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

Figure 2 is a diagram showing a memory device in accordance with an embodiment of the present invention. Referring to FIG. 1, the memory device 1 includes a memory array 10, a column decoder 11, a row decoder 12, a control circuit 13, a read-write circuit 14, and a precharge circuit 15. In one embodiment, the memory device 1 is a static random access memory. The memory array 10 includes a plurality of memory cells 100 configured in a plurality of columns and a plurality of rows. The column decoder 11 is connected to the memory array 10 via word lines WL1-WLX, and each word line is connected to the memory cells 100 arranged in the same column. The row and column decoder 12 is connected to the memory array 10 through the bit lines BL1-BLY, and each bit line is connected to the memory cell 100 disposed in the same row. According to the configuration of the word line WL1-WLX, the bit line BL1-BLY, and the memory cell 100, each memory cell 100 corresponds to a set of word lines and bit lines.

Control circuit 13 receives two different clock signals RCLK and CCLK. The control circuit 13 generates a control signal S13R to the column decoder 11 based on the clock signal RCLK, and generates a control signal S13C to the row decoder 12 based on the clock signal CCLK. Referring to Figure 3, the frequency of the clock signal RCLK is different from the clock signal. No. CCLK frequency. In detail, the clock signal RCLK includes a plurality of pulse waves PLSR and the clock signal CCLK includes a plurality of pulse waves PLSC. During the duration of each pulse wave PLSR of the clock signal RCLK, a plurality of clock signals CCLK occur. Pulse wave PLSC. For example, during the duration of each pulse wave PLSR of the clock signal RCLK, (N+1) pulse waves PLSC occur, where N≧1. The control circuit 13 also receives the enable signals WEB and CEB for write enable and wafer enable for the memory device 1, respectively. The control circuit 13 additionally generates a control signal S14 to the read-write circuit 14 to control the read-write circuit 14 to perform a read or write operation. The operation of the memory device 1 will be described below with reference to FIGS. 2 and 3.

Whenever the clock signal RCLK is positively triggered, the control circuit 13 generates a control signal S13R in an enabled state to enable the decoder 11 to lock the address according to the received address signal ADD and according to the locked bit. The address is used to select a word line such as the word line WL1. Whenever the clock signal CCLK is positively triggered, the control circuit 13 generates a control signal S13C in an enabled state to enable the decoder 12 to lock the address according to the received address signal ADD and according to the locked bit. Address to select a bit line. Referring to FIG. 3, during the period between two consecutive positive edge triggers of the clock signal RCLK, the clock signal CCLK is triggered multiple times by the positive edge. Therefore, it can be known that during the period in which one word line is selected, a plurality of (at least two) bit lines are selected, and the read-write circuit 14 pairs the selected bits in accordance with the control signal S14 from the control circuit 13. The element lines each perform a read/write operation to read the material DOUT from the corresponding memory cell or write the data DIN to the corresponding memory cell. In one embodiment, the data DOUT and the data DIN are serial data. When the read-write circuit 14 performs a read/write operation, the material DOUT is read in a frame-page mode, a packet mode, or a sequence mode. Output or write data DIN. In this case, the memory device 1 can function as a buffer device.

According to the above, the control circuit 13 controls the decoders 11 and 13 according to different clock signals so that when at least two memory cells on the same memory cell are read/written, the decoder 11 does not need to be executed twice. Address lock for the same character line. In detail, when a word line is selected, at least two memory cells on a memory cell coupled to the word line can be read/written until read/write to the memory cell column. Into the completion. Next, another word line can be selected for subsequent read/write operations. In other words, reading/writing of the next memory cell row is performed after the memory cell reading or writing on a memory cell column is completed. Therefore, for a read/write of a memory cell, the decoder 11 only needs to lock the address once.

In addition, due to the word line and bit line selection and the data read/write mode disclosed in the above embodiments, in the period in which the decoder 11 locks the address to select a corresponding word line, the plurality of bits are Before the source line performs the read/write operation, the precharge circuit 15 only needs to perform a precharge operation on the bit line BL1-BLY. Referring to Fig. 3, when the decoder 11 selects a word line period, only the one-time precharge operation causes the accompanying surge current to instantaneously pull down the power supply current I _VDD once. In this way, the power consumption of the memory device 1 during operation can be reduced.

In the above embodiment, during a period in which a word line is selected (i.e., during the duration of a pulse PLSR of the clock signal RCLK), the read-write circuit 14 can perform a read on all of the selected bit lines. Take operation, perform a write operation on all selected bit lines, or perform a read on a part of the selected bit line The operation is performed while the other part performs the write operation.

Figure 4 is a flow chart showing a control method for a memory device in accordance with an embodiment of the present invention. This control method will be explained with reference to Figure 2-4. First, two different clock signals RCLK and CCLK are received (step S40). The control signal S13R is generated based on the clock signal RCLK (step S41). In an embodiment, when a positive edge trigger occurs on the pulse signal RCLK, the control signal S13R is enabled. The control signal S13C is generated based on the clock signal CCLK (step S42). In an embodiment, when a positive edge trigger occurs on the pulse signal CCLK, the control signal S13C is enabled. The address is locked in accordance with the enable state of the address signal ADD and the control signal S13R to select a word line (step S43). During the selection of the word line (step S43), a precharge operation is performed on the bit line BL1-BLY once (step S44). During the selection of the word line (step S43), after the precharge operation is completed, the address is locked according to the enable state of the address signal ADD and the control signal S13C to select at least two bit lines (steps) S45), and a read/write operation is performed on each of the selected bit lines (step S46). When the reading/writing of step S46 is completed, the method returns to step S43 to select another character line.

According to the above, the clock signal RCLK for word line selection is different from the clock signal CCLK for bit line selection, so that when at least two memory cells on the same memory cell are read/written, The address lock for the same character line must be performed twice. In addition, when a period of one word line is selected, even if a read/write operation is performed on a plurality of bit lines, only one precharge operation is accompanied, so that the accompanying surge current only causes the power source current I. _VDD is pulled down once. In this way, the power consumption of the memory device 1 during operation can be reduced.

Although the present invention has been disclosed above in the preferred embodiment, it is not The scope of the present invention is defined by those skilled in the art, and the scope of the invention is intended to be modified and modified. The definition is final.

1‧‧‧ memory device

10‧‧‧ memory array

11, 12‧‧‧ decoder

13‧‧‧Control circuit

14‧‧‧Write-read circuit

15‧‧‧Precharge circuit

100‧‧‧ memory cells

ADD‧‧‧ address signal

BL0...BLY‧‧‧ bit line

CCLK, RCLK‧‧‧ clock signal

CEB, WEB‧‧‧ enable signal

DIN, DOUT‧‧‧ data

S13R, S13C, S14‧‧‧ control signals

WL0...WLX‧‧‧ character line

Claims (14)

A memory device includes: a memory array comprising a plurality of memory cells configured as a plurality of memory cells and a plurality of memory cells; a complex digital line, each of the word lines coupled to one of the memory cells The memory cells; the plurality of bit lines, each of the bit lines being coupled to the memory cells of one of the memory cell lines; a first decoder receiving the address signal and a first Controlling a signal, and selecting one of the word lines according to the address signal and the first control signal; a second decoder receiving the address signal and a second control signal; and a control circuit receiving a first clock signal and a second clock signal, generating the first control signal according to the first clock signal, and generating the second control signal according to the second clock signal; wherein, in the a decoder selects one of the word lines according to the address signal and the first control signal, and the second decoder selects the bit line according to the address signal and the second control signal At least two lines in the middle, and the memory Be at least two lines of the apparatus and the like each execute a read / write operations. The memory device of claim 1, wherein the first clock signal comprises a plurality of first pulse waves, the second clock signal comprises a plurality of second pulse waves, and each of the first pulse waves At least two of the first occurrences Two pulse waves. The memory device of claim 1, wherein the control circuit generates the first control signal whenever the first clock signal generates a positive edge trigger, so that the first decoder can The address signal is used to select one of the word lines; wherein the control circuit generates the second control signal whenever the positive edge trigger occurs on the second clock signal, so that the second decoder can Addressing a signal to select one of the bit lines; and wherein, during a period between two consecutive positive edge triggers of the first clock signal, the second clock signal occurs the positive edge multiple times trigger. The memory device of claim 1, wherein the memory device is in a period in which the first decoder selects one of the word lines based on the address signal and the first control signal Only one precharge operation is performed on the bit line. The memory device of claim 1, wherein the memory device is in a period in which the first decoder selects one of the word lines based on the address signal and the first control signal A read/write operation is performed on each of at least two of the bits to read or write a list of data. The memory device of claim 5, wherein the memory device reads or writes the serial data in a frame-page mode, a packet mode, or a sequence mode. The memory device of claim 1, wherein the memory device is a static random access memory. The memory device of claim 1, wherein the memory device The device is a buffer device. A control method for a memory device, the memory device comprising a memory array, a complex digital element coupled to the memory array, and a plurality of bit lines coupled to the memory array, the control method comprising Receiving a first clock signal and a second clock signal; generating a first control signal according to the first clock signal; generating a second control signal according to the second clock signal; Selecting one of the word lines by the signal and the consistent energy state of the first control signal; and selecting one of the word lines according to the address signal and the first control signal, according to the bit The address signal and the enable state of the second control signal select at least two of the bit lines; and perform a read/write operation on each of the selected bit lines. The control method of claim 9, wherein the first clock signal comprises a plurality of first pulse waves, the second clock signal comprises a plurality of second pulse waves, and each of the first pulse waves At least two of the second pulses occur during the duration. The control method of claim 9, wherein the first control signal is enabled each time the first clock signal generates a positive edge trigger; wherein the second clock signal occurs every time The second control signal is generated when the positive edge is triggered; and wherein the second clock signal occurs the positive edge multiple times during the period between the two consecutive positive edge triggers of the first clock signal trigger. For example, the control method described in claim 9 of the patent scope further includes: While the first decoder selects one of the word lines based on the address signal and the first control signal, only one pre-charge operation is performed on the bit line. The control method of claim 9, wherein the step of performing the read/write operation on each of the selected bit lines comprises: reading or writing a series of data. The control method of claim 13, wherein the serial data is read or written in a frame-page manner, a packet manner, or a sequence.