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TW201639165A - 半導體結構及其製作方法 - Google Patents

半導體結構及其製作方法 Download PDF

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TW201639165A
TW201639165A TW104113242A TW104113242A TW201639165A TW 201639165 A TW201639165 A TW 201639165A TW 104113242 A TW104113242 A TW 104113242A TW 104113242 A TW104113242 A TW 104113242A TW 201639165 A TW201639165 A TW 201639165A
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recess
angstroms
groove
substrate
semiconductor structure
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TW104113242A
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TWI637514B (zh
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林猷穎
陳廣修
郭敏郎
王俞仁
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聯華電子股份有限公司
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Priority to TW104113242A priority Critical patent/TWI637514B/zh
Priority to US14/714,361 priority patent/US9419089B1/en
Priority to US15/166,291 priority patent/US9502244B2/en
Publication of TW201639165A publication Critical patent/TW201639165A/zh
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Abstract

本發明提供一種半導體結構，包含一基底，至少兩閘極結構位於該基底上，一第一凹槽，位於該兩閘極結構之間的該基底中，且該第一凹槽具有一U型剖面結構，以及一第二凹槽，位於該第一凹槽上，其中該第二凹槽具有一多角形剖面結構，且至少包含兩尖角分別位於該第二凹槽的兩側壁，該第一凹槽與該第二凹槽共同組成一磊晶凹槽結構。

Description

半導體結構及其製作方法
本發明係有關於半導體製程領域，尤其是關於一種特殊形狀的磊晶凹槽結構以及其製作方法。
隨著半導體製程進入到深次微米時代，例如65奈米(nm)以下之製程，對於金氧半導體(metal-oxide semiconductor，MOS)電晶體元件的驅動電流(drive current)的提昇已顯得日益重要。為了改善元件的效能，目前業界已發展出所謂的應變矽技術，例如採用選擇性磊晶成長(selective epitaxial growth，以下簡稱為SEG)方法，來製作MOS電晶體的源極/汲極，利用成長於源極/汲極區域的磊晶層使閘極通道部分的矽晶格產生應變，使電荷在通過此應變之閘極通道時的遷移率增加，進而達到使MOS電晶體運作更快的目的。
本發明提供一種半導體結構，包含一基底，至少兩閘極結構位於該基底上，一第一凹槽，位於該兩閘極結構之間的該基底中，且該第一凹槽具有一U型剖面結構，以及一第二凹槽，位於該第一凹槽上，其中該第二凹槽具有一多角形剖面結構，且至少包含兩尖角分別位於該第二凹槽的兩側壁，該第一凹槽與該第二凹槽共同組 成一磊晶凹槽結構。
本發明另提供一種半導體結構的製作方法，包含：提供一基底，進行一第一乾蝕刻步驟，於該基底中形成一凹槽，對該凹槽的一底面進行一離子佈植步驟，進行一濕蝕刻步驟，蝕刻該凹槽的部分側壁，形成至少兩尖角分別位於該凹槽的兩側壁，以及進行一第二乾蝕刻步驟，蝕刻該凹槽的部分底面，使該凹槽底部具有一U型剖面結構。
藉由執行本發明步驟，可形成一磊晶凹槽結構，此磊晶凹槽結構的上半部具有一鑽石形狀(或六角形狀)，且磊晶凹槽結構的下半部具有一平坦底部。上半部的鑽石形狀會產生一指向通道區域的尖角。因此，沿著凹槽表面形成的磊晶層亦可獲得指向通道區域的尖角，可增加對通道區域的有效應力，提升通道區域的載子遷移率並進而提升元件的電性表現。而磊晶凹槽結構的下半部具有平坦底部，沿著凹槽平坦底部成長的磊晶層亦隨之獲得一平坦底部，故可避免底部尖角發生的元件漏電等問題，增加了元件的可靠度。簡單地說，本發明所提供之半導體結構之製作方法係不僅可改善元件的電性表現，更可提升元件的可靠度。
100‧‧‧基底
110‧‧‧閘極
112‧‧‧閘極介電層
114‧‧‧側壁子
120‧‧‧凹槽
122‧‧‧磊晶層
200‧‧‧基底
210‧‧‧閘極
212‧‧‧閘極介電層
214‧‧‧覆蓋層
216‧‧‧輕摻雜汲極
217‧‧‧頂面
218‧‧‧側壁子
218a‧‧‧封層
218b‧‧‧絕緣層
220‧‧‧閘極結構
232‧‧‧凹槽
234‧‧‧凹槽
234a‧‧‧第一側壁
234b‧‧‧第二側壁
236‧‧‧凹槽
236a‧‧‧第一側壁
236b‧‧‧底面
238‧‧‧磊晶凹槽結構
240‧‧‧磊晶層
P1‧‧‧第一乾蝕刻步驟
P2‧‧‧離子佈植步驟
P3‧‧‧濕蝕刻步驟
P4‧‧‧第二乾蝕刻步驟
b1‧‧‧底面
b2‧‧‧底面
t1‧‧‧夾角
t2‧‧‧夾角
d1~d4‧‧‧長度距離
第1圖係為一採用SEG方法之半導體結構之示意圖。
第2圖至第7圖係為本發明所提供之半導體結構之製作方法之一較佳實施例之示意圖。
請參閱第1圖，第1圖係為一採用SEG方法之半導體結構之示意圖。如第1圖所示，半導體結構150係設置於一基底100上，其包含一閘極導電層110與一閘極介電層112。閘極導電層110與閘極介電層112之周圍另包含有側壁子114。另外，側壁子114兩側之基底100內分別形成有一凹槽120，凹槽120內係包含利用SEG方法形成的磊晶層122。由於磊晶層122係藉由SEG方法沿著凹槽120的各表面成長，因此凹槽120的形狀與晶面方向對於所形成的磊晶層122亦越發具有影響力。舉例來說，當半導體結構150之凹槽120下半部呈一V形的結構時，沿著凹槽120表面成長的磊晶層122亦獲得一V形的底部尖角(圓圈A所示)，而此底部尖角處會造成元件漏電的問題。
請參閱第2圖至第7圖，第2圖至第7圖係為本發明所提供之半導體結構之製作方法之一較佳實施例之示意圖。如第2圖所示，本較佳實施例首先提供一基底200，基底200具有一平坦的頂面217且其上形成有閘極結構220，閘極結構220主要包含一閘極介電層212、一閘極導電層210與一覆蓋層214，由下而上堆疊於基底200上。如熟習該項技藝之人士所知，覆蓋層214係覆蓋於閘極導電層210上，初始用來當圖案化遮罩以定義閘極位置，後續則可用以於後續進行的各微影製程、離子佈植製程、接觸洞蝕刻製程或任何必需的清洗製程中保護閘極導電層210，避免閘極導電層210在上述製程中受到傷害。閘極結構220之閘極導電層210與閘極介電層212兩側之基底200內係分別形成有一輕摻雜汲極(LDD)216；而閘極導電層210與閘極介電層212兩側之側壁上，係形成有一側壁子218。如第2圖所示，側壁子218例如為一複合膜層，其可包 含一具有L字形狀的封層218a，以及一覆蓋封層218a的絕緣層218b。側壁子218係於完成LDD 216之製作後，形成於閘極導電層210與閘極介電層212之側壁上，其可在後續製程中保護閘極導電層210與閘極介電層212之側壁。
請參閱第3圖。接下來，係進行一第一乾蝕刻步驟P1，蝕刻閘極結構220與側壁子218兩側之基底200。其中，第一乾蝕刻步驟P1較佳為一非等向性蝕刻步驟，例如以含氟(F)或是含氯(Cl)等氣體，並選用氦氣(He)等惰性氣體為載氣，對基底200進行蝕刻，至少於兩閘極結構220之間的基底200中形成一凹槽232，凹槽232具有一U型剖面，且凹槽232有一平坦的底面b1。
如第4圖所示，接著，進行一離子佈植步驟P2，摻雜特定離子至凹槽232內的底面b1，本實施例中，離子佈植步驟P2所選用的離子可包含硼離子、磷離子、砷離子、鍺離子或氬離子或其組合。經過離子佈植步驟P2之後，凹槽232的底面b1之抗蝕刻率將會提高，而在凹槽232底部形成一耐蝕刻底面b2，換句話說，在後續的蝕刻步驟中，凹槽232內的底面b2將會比凹槽232的側壁更不易被蝕刻。
接下來，如第5圖所示，進行一濕蝕刻步驟P3，蝕刻凹槽232內部。本實施例中，濕蝕刻步驟P3主要是利用一四甲基氫氧化銨溶液(tetra methyl ammonium hydroxide，(CH3)4NOH，TMAH)蝕刻凹槽232。在本較佳實施例中，TMAH溶液中的TMAH之濃度低於5%，而水(H2O)之比例則高於95%。濕蝕刻步驟P3的製程溫度約在70℃，但不限於此。由於上述離子佈植步驟P2已經在凹 槽232內形成更耐蝕刻的底面b2，因此在濕蝕刻步驟P3的過程中，蝕刻凹槽232側壁的蝕刻率將會大於蝕刻凹槽232底面b2的蝕刻率。在濕蝕刻步驟P3之後，凹槽232的形狀改變，形成一凹槽234，其中從剖面圖來看，凹槽234為一多角形剖面，較佳而言，凹槽234具有鑽石型剖面或是六角形剖面，具有兩第一側壁234a，以及兩第二側壁234b，其中每一第一側壁234a與一第二側壁234b之間具有一夾角t1。也就是說，從第5圖上來看，凹槽234具有兩夾角t1，分別位於凹槽234的兩側壁上，且兩夾角t1位於同一水平位置上。
如第6圖所示，進行一第二乾蝕刻步驟P4，此處的第二乾蝕刻步驟P4為一非等向性蝕刻步驟，垂直蝕刻底面b2，並於基底200中形成凹槽236，其中凹槽236與凹槽234相互連通，且凹槽236具有一U型剖面。更詳細說明，從剖面圖來看，凹槽236具有兩第一側壁236a以及一平坦的底面236b。其中，凹槽236的第一側壁236a與凹槽234的第二側壁234b具有不同傾斜角度，且兩者之間有一夾角t2。
從剖面圖上來看，請參考第6圖，本發明的凹槽234與凹槽236共同組成一具有特殊形狀的磊晶凹槽結構238。其特徵在於位於下方的凹槽236具有一U型剖面結構，而位於上方的凹槽234則具有一多角形剖面(較佳為六角形剖面)，且具有兩夾角t1分別位於凹槽234的兩側壁上。此外，凹槽234與凹槽236直接接觸且相互連通。
另外，依序執行上述步驟P1-P4所完成的磊晶凹槽結構238，請一併參考第6圖，其尺寸滿足以下條件：
(1).基底200的頂面至任一夾角t1的垂直距離d1，介於90埃~150埃；
(2).磊晶凹槽結構238的一底面(也就是凹槽236的底面236b)至基底200的頂面之垂直長度d2，介於550埃~650埃；
(3).閘極結構210的一垂直側壁至任一夾角t1的水平距離d3，介於10埃~50埃；以及
(4).側壁子218位於閘極結構210的兩側壁上，且側壁子218的底部厚度d4，介於60埃~100埃。
(5).如上所述，其中d1/d2範圍介於0.15~0.25之間。
(6).如上所述，其中d3/d4範圍介於0.1~0.5之間。
可理解的是，上述各長度尺寸為本發明較佳實施例之範例，但本發明不以此為限，而上述的各元件尺寸仍可依照實際需求而調整。
請參閱第7圖。接下來，係進行一選擇性磊晶成長(SEG)方法P5，以於磊晶凹槽結構238內形成一磊晶層240，且磊晶層240係填滿磊晶凹槽結構238。熟習該項技藝之人士應知，在進行SEG方法P5時，磊晶層240係沿著磊晶凹槽結構238的各表面成長。因此，形成如第7圖所示形狀之磊晶層240。值得注意的是，由於磊晶凹槽結構238具有平坦底面236b，因此磊晶層240亦據此獲得一平坦底部。此外，在本較佳實施例中，磊晶層240係依據電性要求(p型或n型)而可包含一矽鍺(SiGe)磊晶層或一矽碳(SiC)磊晶層。此外，亦可一製程或產品需要，選擇性地移除覆蓋層214，並進行一金屬矽化物製程，而至少於磊晶層240表面形成金屬矽化物(圖未示)。另外，上述實施例中，以平面式的電晶體結構為例說明，但 本發明也可應用於非平面式的電晶體(例如鰭狀電晶體，finFET)等，也屬於本發明的涵蓋範圍內。
相較於第1圖所示的半導體結構，藉由執行本發明步驟P1-P4，可形成一磊晶凹槽結構，此磊晶凹槽結構的上半部具有一鑽石形狀(或六角形狀)，且磊晶凹槽結構的下半部具有一平坦底部。上半部的鑽石形狀會產生一指向通道區域的尖角。因此，沿著凹槽表面形成的磊晶層亦可獲得指向通道區域的尖角，可增加對通道區域的有效應力，提升通道區域的載子遷移率並進而提升元件的電性表現。而磊晶凹槽結構的下半部具有平坦底部，沿著凹槽平坦底部成長的磊晶層亦有一平坦底部，可避免底部尖角發生的元件漏電等問題，增加了元件的可靠度。簡單地說，本發明所提供之半導體結構之製作方法係不僅可改善元件的電性表現，更可提升元件的可靠度。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
200‧‧‧基底
210‧‧‧閘極
212‧‧‧閘極介電層
214‧‧‧覆蓋層
216‧‧‧輕摻雜汲極
218‧‧‧側壁子
218a‧‧‧封層
218b‧‧‧絕緣層
220‧‧‧閘極結構
234‧‧‧凹槽
234a‧‧‧第一側壁
234b‧‧‧第二側壁
236‧‧‧凹槽
236a‧‧‧第一側壁
236b‧‧‧底面
238‧‧‧磊晶凹槽結構
P4‧‧‧第二乾蝕刻步驟
t1‧‧‧夾角
t2‧‧‧夾角
d1~d4‧‧‧長度距離

Claims (20)

  1. 一種半導體結構，包含：一基底，至少兩閘極結構位於該基底上；一第一凹槽，位於該兩閘極結構之間的該基底中，且該第一凹槽具有一U型剖面結構；以及一第二凹槽，位於該第一凹槽上，其中該第二凹槽具有一多角形剖面結構，且至少包含兩夾角分別位於該第二凹槽的兩側壁，該第一凹槽與該第二凹槽共同組成一磊晶凹槽結構。
  2. 如申請專利範圍第1項所述的半導體結構，其中該多角形剖面結構為一六角型剖面結構。
  3. 如申請專利範圍第1項所述的半導體結構，其中該第二凹槽與該第一凹槽直接接觸。
  4. 如申請專利範圍第1項所述的半導體結構，其中該兩尖角位於同一水平位置上。
  5. 如申請專利範圍第4項所述的半導體結構，其中該基底的一頂面至該尖角之垂直距離介於90埃~150埃。
  6. 如申請專利範圍第1項所述的半導體結構，其中更包含一磊晶層填於該磊晶凹槽結構中。
  7. 如申請專利範圍第1項所述的半導體結構，其中該磊晶凹槽結構的一底面至該基底的一頂面之垂直距離介於550埃~650埃。
  8. 如申請專利範圍第1項所述的半導體結構，其中該閘極結構的一垂直側壁至該尖角的水平距離介於10埃~50埃。
  9. 如申請專利範圍第1項所述的半導體結構，更包含一側壁子位於該閘極結構的兩側壁上，且該側壁子的底部厚度介於60埃~100埃。
  10. 一種半導體結構的製作方法，包含：提供一基底；進行一第一乾蝕刻步驟，於該基底中形成一凹槽；對該凹槽的一底面進行一離子佈植步驟；進行一濕蝕刻步驟，蝕刻該凹槽的部分側壁，形成至少兩尖角分別位於該凹槽的兩側壁；以及進行一第二乾蝕刻步驟，蝕刻該凹槽的部分底面，使該凹槽底部具有一U型剖面結構。
  11. 如申請專利範圍第10項的方法，其中該濕蝕刻步驟在該離子佈植步驟之後進行，且該第二乾蝕刻步驟在該濕蝕刻步驟之後進行。
  12. 如申請專利範圍第10項的方法，其中該兩尖角的水平位置比該U型剖面結構高。
  13. 如申請專利範圍第10項的方法，更包含形成至少兩閘極結構於該基底上，且該凹槽位於該兩閘極結構之間的基底中。
  14. 如申請專利範圍第10項的方法，在該第二乾蝕刻步驟之後，更包含形成一磊晶層於該凹槽中。
  15. 如申請專利範圍第14項的方法，其中該磊晶層包含鍺化矽或碳化矽。
  16. 如申請專利範圍第10項的方法，其中該基底的一頂面至該尖角之垂直距離介於90埃~150埃。
  17. 如申請專利範圍第10項的方法，其中該磊晶凹槽結構的一底面至該基底的一頂面之垂直距離介於550埃~650埃。
  18. 如申請專利範圍第10項的方法，其中該閘極結構的一垂直側壁至該尖角的水平距離介於10埃~50埃。
  19. 如申請專利範圍第10項的方法，更包含一側壁子位於該閘極結構的兩側壁上，且該側壁子的底部厚度介於60埃~100埃。
  20. 如申請專利範圍第10項的方法，其中該離子佈植步驟中的摻雜離子包含硼離子、磷離子、砷離子、鍺離子或氬離子。
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TWI684215B (zh) * 2017-10-27 2020-02-01 美商格芯（美國）集成電路科技有限公司 用於磊晶半導體成長之雙曲度空腔
TWI778226B (zh) * 2018-02-20 2022-09-21 日商東京威力科創股份有限公司 達成側壁蝕刻的方法

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