TW201627731A - Array substrate and method for rubbing the same - Google Patents

Abstract

An array substrate includes a substrate, a pixel circuit, traces, an alignment film, and a flat layer. The substrate includes a display area and a periphery area. The pixel circuit is disposed on the display area. The traces are disposed on the periphery area and connected to the pixel circuit. The alignment film is disposed on the display area and the periphery area. The flat layer is disposed on the periphery area for flatting the periphery area.

Description

Array substrate and alignment method thereof

The present invention relates to an array substrate.

With the advancement of technology, the use of liquid crystal displays has become more and more popular. In the working principle of the liquid crystal liquid crystal display, since the liquid crystal has optical rotation, the polarization direction of the light passing through the liquid crystal layer can be controlled by applying an electric field to the liquid crystal layer. In addition, the alignment direction of the liquid crystal needs to be defined by the alignment film, that is, the alignment film provides the initial alignment direction of the liquid crystal at the boundary. Therefore, the display quality of a liquid crystal display has a certain relationship with its alignment film.

In the process of the alignment film, polyimide (PI) is usually formed first. Next, the alignment of the alignment bristles with the polyimide is used to cause the polyimide to form an extended array of grooves in the alignment direction, wherein the grooves provide a liquid crystal pretilt angle at the boundary. Furthermore, the quality of the alignment process is also related to the display quality of the liquid crystal display. Therefore, how to effectively improve the quality of the alignment process is one of the current important research and development topics, and has become the research direction of relevant fields.

In the alignment process, the angle of the alignment cloth entering the alignment film may be 45 degrees, 90 degrees or 135 degrees in response to the viewing angle direction of the liquid crystal display. Therefore, when the alignment cloth is in contact with the alignment film located in the peripheral area, the alignment cloth will be affected by the traces located in the peripheral area, causing the alignment of the tip of the distribution cloth to bifurcate or change direction, and causing uneven alignment to affect the display. Quality issues.

In view of this, the array substrate of the following embodiment of the present invention is provided with a flat layer in which the flat layer is disposed on the trace such that the gap between the traces is filled by the flat layer. Therefore, when the alignment is performed by the alignment cloth, the alignment cloth will not be affected by the wiring located in the peripheral area, thereby improving the problem of uneven alignment. Therefore, the alignment process quality and yield of the array substrate can be improved, and the display quality of the subsequently completed liquid crystal display can be improved.

One aspect of the present disclosure provides an array substrate comprising a substrate, a pixel circuit, traces, an alignment film, and a planarization layer. The substrate includes a display area and a peripheral area. The pixel circuit is disposed in the display area. The trace is placed in the peripheral area and connected to the pixel circuit. The alignment film is disposed in the display area and the peripheral area. A flat layer is disposed in the peripheral region, thereby flattening the peripheral region.

In some embodiments, the planarization layer is between the alignment film and the substrate.

In some embodiments, the alignment film is between the planar layer and the substrate.

In some embodiments, the flat layer thickness is between 0.5 microns and 5 microns.

In some embodiments, the alignment film thickness is between 80 nm and Between 135 nm.

One aspect of the present disclosure provides an alignment method of an array substrate, comprising the following steps. The interconnected pixel circuits are respectively formed and routed on the display area of the substrate and the peripheral area. An alignment film is formed on the display area and the peripheral area. A flat layer is formed on the alignment film of the peripheral region, thereby planarizing the peripheral region. The alignment of the alignment film is performed through the alignment cloth.

One aspect of the present disclosure provides an alignment method of an array substrate, comprising the following steps. The interconnected pixel circuits are respectively formed and routed on the display area of the substrate and the peripheral area. A flat layer is formed on the peripheral region, thereby flattening the peripheral region. An alignment film is formed on the display area and the peripheral area. The alignment of the alignment film is performed through the alignment cloth.

In some embodiments, the flat layer thickness is between 0.5 microns and 5 microns and the alignment film thickness is between 80 nm and 135 nm.

In some embodiments, the step of aligning the alignment film through the alignment cloth further comprises the following steps. The matching cloth hair enters the display area from the surrounding area.

In summary, the array substrate of the present invention is provided with a flat layer in which the flat layer is located on the peripheral region. Specifically, the flat layer is disposed on the path of the alignment cloth entering the display area. Therefore, when the alignment of the alignment film is performed through the alignment cloth, the alignment cloth is not affected by the wiring located in the peripheral area. Furthermore, the alignment cloth does not cause the tip end to bifurcate or change direction due to the gap between the wires, and thus the problem of uneven alignment. Therefore, by providing a flat layer, the alignment process quality and yield of the array substrate can be improved.

100‧‧‧Array substrate

110‧‧‧Substrate

112‧‧‧ display area

113‧‧‧ Surface

114‧‧‧The surrounding area

116‧‧‧Blocking area

120‧‧‧pixel circuit

122‧‧‧Wiring

124‧‧‧ terminals

130‧‧‧Alignment film

132‧‧‧ surface

140‧‧‧flat layer

142‧‧‧ surface

150‧‧‧Alignment cloth

BB’‧‧‧ segment

S10-S40, P10-P40‧‧‧ steps

FIG. 1A is a top plan view of an array substrate according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view taken along line BB' of Fig. 1A.

Figure 1C is a side elevational view of the array substrate of Figure 1A.

Fig. 2 is a top plan view showing alignment of an array substrate according to an embodiment of the present invention.

3A is a schematic cross-sectional view of an array substrate according to another embodiment of the present invention.

Figure 3B is a side elevational view of the array substrate of Figure 3A.

Fig. 4 is a flow chart showing the alignment method of the array substrate of Figs. 1A to 1C.

Fig. 5 is a flow chart showing the alignment method of the array substrate of Figs. 3A to 3B.

FIG. 1A is a top plan view of an array substrate 100 according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along line BB' of Fig. 1A. The array substrate 100 includes a substrate 110, a pixel circuit 120, traces 122, terminals 124, an alignment film 130, and a flat layer 140. The substrate 110 includes a display area 112 and a peripheral area 114. The pixel circuit 120 is disposed in the display area 112. The trace 122 is disposed in the peripheral region 114 and connects the pixel circuit 120 and the terminal 124. The alignment film 130 is disposed on the display area 112 and the peripheral area 114. The planarization layer 140 is disposed in the peripheral region 114, thereby planarizing the peripheral region 114.

In the peripheral region 114, the alignment film 130 covers the substrate 110 and the traces 122. The planarization layer 140 covers the alignment film 130 such that the surface of the array substrate 100 corresponding to the peripheral region 114 is a flat surface 142.

In particular, since there is a gap between the traces 122 located in the peripheral region 114, there will be a step difference between the substrate 110 and the trace 122, which will form a surface 113 having an undulation. Through the arrangement of the flat layer 140 and the alignment film 130, the step difference between the substrate 110 and the trace 122 is filled by this configuration.

Please refer to FIG. 1B and FIG. 1C again, wherein FIG. 1C is a side view of the array substrate 100 of FIG. 1A. In the present embodiment, the alignment film 130 is located between the flat layer 140 and the substrate 110. In addition, the alignment film 130 extends from the peripheral region 114 to the display region 112 and covers the pixel circuit 120, wherein the peripheral region 114 and the alignment film 130 of the display region 112 are the same layer alignment film 130. In the present embodiment, the planarization layer 140 covers only the alignment film 130 located in the peripheral region 114, so that when the subsequent alignment process is performed, the alignment film 130 located in the display region 112 can still be aligned by the alignment of the cloth.

Fig. 2 is a top plan view showing the alignment of the array substrate 100 according to the embodiment of the present invention. When the array substrate 100 is to be aligned by the alignment bristles 150, the alignment bristles 150 will enter the peripheral region 114 in the direction of the arrow, then enter the display region 112, and align the alignment film 130 in the display region 112.

In the alignment, the alignment bristles 150 will first contact the peripheral zone 114. When the alignment cloth 150 contacts the peripheral region 114, due to the presence of the flat layer 140, the alignment cloth 150 will contact the flat surface 142, thus the alignment The tip of the bristles 150 will not be bifurcated or redirected due to contact with the step. Therefore, the alignment process performed by the alignment cloth 150 on the alignment film 130 will also not cause significant unevenness.

That is to say, through the arrangement of the flat layer 140 and the alignment film 130, the alignment of the alignment cloth 150 to the alignment film 130 will be more uniform, so that the display quality of the liquid crystal display manufactured by the array substrate 100 can be improved.

Returning to FIG. 1B, in the present embodiment, the thickness of the trace 122 is 0.6 micrometers, that is, the depth of the step between the trace 122 and the substrate 110 is 0.6 micrometers. Further, in the present embodiment, the thickness of the alignment film 130 is between 80 nm and 135 nm, and the thickness of the flat layer 140 is between 0.5 μm and 5 μm.

In the present embodiment, the flat layer 140 and the alignment film 130 have an overall thickness of 1.5 μm, and thus can fill a step of a depth of 0.6 μm. However, it should be understood that the thickness of the trace 122 and the depth of the step between the trace 122 and the substrate 110 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention can flexibly select the thickness of the flat layer 140 and the alignment film 130 according to actual needs, as long as the step difference between the trace 122 and the substrate 110 can be filled.

As shown in FIG. 1C, since the flat layer 140 covers only the alignment film 130 located in the peripheral region 114, there is a difference between the display region 112 and the peripheral region 114. However, compared to the step difference between the trace 122 and the substrate 110, the step difference between the display region 112 and the peripheral region 114 is a single step difference, and the single step difference spans the entire array substrate 100, so there is no uniformity. problem.

Please return to Figure 1A. The flat layer 140 of the present embodiment may not necessarily cover the terminal 124, so that the terminal 124 is electrically connected to an external circuit. In addition, the finished alignment film 130 may be provided with a sealant area 116, which may be used to set the sealant for subsequent bonding processes.

Fig. 3A is a schematic cross-sectional view showing an array substrate 100 according to another embodiment of the present invention, the cross-sectional position of which is the same as that of Fig. 1B. 3B is a side view of the array substrate 100 of FIG. 3A. The difference between this embodiment and the previous embodiment is that the flat layer 140 of the present embodiment is located between the alignment film 130 and the substrate 110.

More specifically, in the peripheral region 114, the planar layer 140 covers the substrate 110 and the traces 122. The alignment film 130 covers the flat layer 140. Since the planarization layer 140 is capable of planarizing the peripheral region 114, when the alignment film 130 is overlaid on the planarization layer 140, the location where the alignment film 130 is located is the planar surface 142 provided by the planarization layer 140. Therefore, the surface 132 of the alignment film 130 will also be a flat surface without an excessive step.

Similarly, when the alignment film 130 is subjected to the alignment process, since the alignment cloth is in contact with the peripheral region 114, it will be a flat surface. Therefore, the tip of the alignment cloth will not be bifurcated or redirected due to contact with the step. Therefore, there is no significant unevenness in the alignment process performed by the alignment cloth on the alignment film 130.

Fig. 4 is a flow chart showing the alignment method of the array substrate 100 of Figs. 1A to 1C. The alignment method of the array substrate 100 of FIGS. 1A to 1C includes the following steps. In step P10, interconnected pixel circuits 120 and traces 122 are formed on the display area 112 and the peripheral area 114 of the substrate 110, respectively. step P20, an alignment film 130 is formed on the display area 112 and the peripheral area 114. In step P30, a flat layer 140 is formed on the alignment film 130 of the peripheral region 114, thereby planarizing the peripheral region 114. In step P40, the alignment of the alignment film 130 is performed through the alignment cloth.

Fig. 5 is a flow chart showing the alignment method of the array substrate 100 of Figs. 3A to 3B. The alignment method of the array substrate 100 of FIGS. 3A to 3B includes the following steps. In step S10, interconnected pixel circuits 120 and traces 122 are formed on the display area 112 of the substrate 110 and the peripheral area 114, respectively. In step S20, a flat layer 140 is formed on the peripheral region 114, thereby flattening the peripheral region 114. In step S30, an alignment film 130 is formed on the display area 112 and the peripheral area 114. In step S40, the alignment of the alignment film 130 is performed through the alignment cloth.

In summary, the array substrate of the above embodiment of the present invention is provided with a flat layer located in the peripheral region. Therefore, when the alignment of the array substrate is performed through the alignment cloth, the alignment cloth will not be affected by the wiring located in the peripheral area, so that the alignment cloth tip has a bifurcation or a change of direction.

While the invention has been described above in terms of various embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100‧‧‧Array substrate

110‧‧‧Substrate

112‧‧‧ display area

114‧‧‧The surrounding area

116‧‧‧Blocking area

120‧‧‧pixel circuit

122‧‧‧Wiring

124‧‧‧ terminals

130‧‧‧Alignment film

140‧‧‧flat layer

BB’‧‧‧ segment

Claims (10)

An array substrate comprising: a substrate comprising a display area and a peripheral area; a pixel circuit disposed in the display area; a plurality of traces disposed in the peripheral area and connected to the pixel circuit; an alignment film And disposed in the display area and the peripheral area; and a flat layer disposed in the peripheral area, thereby planarizing the peripheral area. The array substrate of claim 1, wherein the planar layer is between the alignment film and the substrate. The array substrate of claim 1, wherein the alignment film is located between the flat layer and the substrate. The array substrate of claim 1, wherein the flat layer has a thickness of between 0.5 micrometers and 5 micrometers. The array substrate of claim 1, wherein the alignment film has a thickness of between 80 nm and 135 nm. An alignment method for an array substrate, comprising the steps of: forming a pixel circuit connected to each other and a plurality of traces on a display area and a peripheral area of a substrate; forming an alignment film on the display area and the peripheral area And forming a flat layer on the alignment film of the peripheral region, thereby planarizing The peripheral region; the alignment of the alignment film is performed through a matching cloth. The alignment method of the array substrate according to claim 6, wherein the flat layer has a thickness of between 0.5 μm and 5 μm, and the alignment film has a thickness of between 80 nm and 135 nm. The alignment method of the array substrate according to claim 6, wherein the step of aligning the alignment film through the alignment cloth further comprises the step of: entering the alignment cloth from the peripheral area into the display area. An alignment method for an array substrate, comprising the steps of: forming a pixel circuit connected to each other and a plurality of traces on a display area of a substrate and a peripheral area; forming a flat layer on the peripheral area to thereby flatten Forming the peripheral region; forming an alignment film on the display region and the peripheral region; and performing alignment of the alignment film through a matching cloth. The alignment method of the array substrate according to claim 9, wherein the flat layer has a thickness of between 0.5 μm and 5 μm, and the alignment film has a thickness of between 80 nm and 135 nm.