TW201611203A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package and manufacturing method thereof is provided. The semiconductor package comprises an encapsulation, a semiconductor element, a plurality of conductive pillars and a build-up structure. The encapsulation has opposite a first and a second surface. The semiconductor element is embedded in the encapsulation and has opposite an active surface and a passive surface, and the active surface is at the same side with the first surface of the encapsulation. The conductive pillars are embedded in the encapsulation, and each of the conductive pillars has opposite a first and a second terminal to expose separately at the first and second surface. The build-up structure is formed on the first surface of the encapsulation, and electrically connected with the semiconductor element and the first terminals of the conductive pillars. Thereby, the invention can make the build-up structure be electrically connected to the conductive pillars without precise alignment.

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package electrically connected to a build-up structure by a conductive pillar and a method of fabricating the same.

In a semiconductor package having a build-up structure or a fan-out structure, a plurality of through holes are formed in the package body, and a circuit layer is formed on the package body and the through holes. The conductive blind holes of the build-up structure are electrically connected, but the through holes and the conductive blind holes are accurately aligned.

1A to 1H are cross-sectional views showing a semiconductor package 1 of the prior art and a method of manufacturing the same.

As shown in FIG. 1A, the first carrier 10 is provided first, and the wafer 11 having a plurality of pads 111 and opposite active surfaces 11a and 11b is disposed on the first carrier 10.

Next, an encapsulant 12 having a first surface 12a and a second surface 12b opposite to each other is formed on the first carrier 10 to cover the wafer 11 and expose the passive surface 11b of the wafer 11.

As shown in FIG. 1B, the second carrier plate 13 is disposed on the passive surface 11b of the wafer 11, and the entire structure of FIG. 1B is inverted upside down, and the first carrier plate 10 is removed.

As shown in FIG. 1C, a build-up structure 14 is formed on the active surface 11a of the wafer 11 and the first surface 12a of the encapsulant 12. The build-up structure 14 has at least one dielectric layer 141, a plurality of conductive vias 142 formed in the dielectric layer 141, and at least one first circuit layer 143 formed on the dielectric layer 141. A circuit layer 143 has a plurality of electrical contact pads 144.

Then, a first insulating protective layer 15 is formed on the build-up structure 14 and a plurality of under bump metal layers 151 are formed on the first insulating protective layer 15 to electrically connect the electrical contact pads 144, respectively.

As shown in FIG. 1D, a third carrier plate 16 having a peeling layer 161 is formed on the first insulating protective layer 15.

As shown in FIG. 1E, the entire structure of the 1D figure is inverted upside down, and the second carrier plate 13 is removed.

As shown in FIG. 1F, a plurality of through holes 121 are formed in the encapsulant 12 to be precisely aligned to the end portions 122 of the conductive vias 142, and the through holes 121 are penetrated through the encapsulant 12 The end portions 122 of the conductive blind holes 142 are respectively exposed.

As shown in FIG. 1G, a seed layer 17 is formed on the passive surface 11b of the wafer 11, the second surface 12b of the encapsulant 12, and the wall surfaces of the through holes 121, and a second wiring layer 171 is formed. The end portions 122 of the conductive blind vias 142 are electrically connected to a portion of the seed layer 17. Thereafter, the seed layer 17 corresponding to the second wiring layer 171 is removed.

As shown in FIG. 1H, a second insulating protective layer 18 is formed on the passive surface 11b of the wafer 11 and the second surface 12b of the encapsulant 12, and the second insulating protective layer 18 has a plurality of openings 181 to expose the first insulating layer 18 Two circuit layers 171. Thereafter, a plurality of solder balls 19 are formed on the under bump metal layers 151, thereby forming the semiconductor package 1.

A disadvantage of the above-mentioned prior art is that when the through hole 121 shown in FIG. 1F is to be formed, the conductive blind hole 142 of the build-up structure 14 is hidden under the first surface 12a of the encapsulant 12, so that the mine The light is not accurately aligned from the second surface 12b of the encapsulant 12 to the end portions 122 of the conductive blind holes 142, so that the through holes 121 formed by the laser light are easily deviated from the end portions 122 of the conductive blind holes 142. Aligned to the dielectric layer 141, and the apertures 123 of the through holes 121 are larger than the cross-sectional areas of the end portions 122 of the conductive vias 142, thereby destroying the dielectric layer 141 around the conductive vias 142. .

Meanwhile, the contact area between the seed layer 17 in the through hole 121 of the 1G drawing and the end portion 122 of the conductive via 142 is too small, so that the second wiring layer 171 and the conductive blind vias 142 on the seed layer 17 are too small. The electrical conductivity between the ends 122 is not good. Furthermore, the third carrier board 16 of the 1D figure is added to the first insulating protection layer 15 so that the material cost and process of the third carrier board 16 need to be increased, and the process of the semiconductor package 1 is too complicated and complicated. It is not conducive to implementation.

Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

The present invention provides a semiconductor package comprising: an encapsulant having opposite first and second surfaces; and a semiconductor component embedded in the encapsulant and having opposite active and passive faces, and The active surface is exposed on the first surface of the encapsulant; the plurality of conductive pillars are embedded in the encapsulant, and the conductive pillars have opposite first and second ends to respectively expose the encapsulant The first surface and the second surface; and the build-up structure is formed on the first surface of the encapsulant and electrically connected to the semiconductor element and the first ends of the conductive pillars.

The invention further provides a method for fabricating a semiconductor package, comprising: embedding a semiconductor component and a plurality of conductive pillars in a package body having opposite first and second surfaces, wherein the semiconductor component has a relative active surface and a passive surface, the active surface is exposed on the first surface of the encapsulant, the conductive post has a first end and a second end opposite to each other, and the first end of the conductive post is exposed to the package a first surface of the colloid; and a build-up structure on the first surface of the encapsulant, and the build-up structure electrically connects the semiconductor element and the first ends of the conductive posts.

The conductive pillar may be a cylinder, an elliptical cylinder, a polygonal cylinder or a spherical cylinder, and the conductive pillar may be made of gold, silver, copper, tin or an alloy thereof.

The method of manufacturing the semiconductor package may include: providing a first carrier and having the semiconductor component disposed thereon, the active surface facing the first carrier; and providing the conductive pillars on the first carrier, the first The end portion faces the first carrier plate; the encapsulant is formed on the first carrier plate to embed the semiconductor component and the conductive pillars in the encapsulant, and the outer surface of the encapsulant is exposed Second ends of the conductive posts; and Except for the first carrier, the active surface of the semiconductor component and the first ends of the conductive pillars are exposed from the first surface of the encapsulant.

The first carrier plate may have a release layer, and the semiconductor component, the conductive pillar and the encapsulant system are located on the release layer.

The method of fabricating the semiconductor package may include: thinning the encapsulant from the second surface and exposing a passive surface of the semiconductor component outside the conductive pillars.

The method of fabricating the semiconductor package may include: disposing a second carrier on the second surface of the encapsulant before removing the first carrier.

The semiconductor package and the method of fabricating the same may include: forming a first wiring layer on the second surface of the encapsulant to electrically connect the second ends of the conductive pillars.

The semiconductor package and the manufacturing method thereof may include: forming a first circuit layer on the second surface of the encapsulant before embedding the conductive pillars in the encapsulant; or: embedding the conductive pillars Simultaneously, the first circuit layer is formed on the second surface of the encapsulant.

The semiconductor package and the manufacturing method thereof may include: forming a first insulating protective layer on the passive surface of the semiconductor component and the second surface of the encapsulant to cover the first circuit layer, the first insulating protective layer having a plurality A portion of the first wiring layer is exposed outside the first opening.

The build-up structure may have at least one dielectric layer, a plurality of conductive vias formed in the dielectric layer, and at least one second circuit layer formed on the dielectric layer and electrically connected to the conductive vias. The second circuit layer has a plurality of electrical contact pads.

The semiconductor package and the method of fabricating the same may include: forming a second insulating protective layer on the outermost layer of the dielectric layer and the second wiring layer, the second insulating protective layer having a plurality of second openings and exposing the outermost layer An electrical contact pad of the second circuit layer.

The semiconductor package may include a plurality of under bump metal layers and a plurality of solder balls. The underlying metal layers are respectively formed on the exposed contact pads of the second openings, and the solder balls are respectively formed. On the underlying metal layer of the bumps.

The method for fabricating the semiconductor package may include: forming a metal layer under the plurality of bumps on the electrical contact pads exposed by the second openings; performing a singulation operation; and forming a plurality of solder balls on the metal layer under the bumps .

As can be seen from the above, in the semiconductor package of the present invention and the method of manufacturing the same, the semiconductor element and the plurality of conductive pillars are embedded in the encapsulant and the ends of the conductive pillars are exposed, and the build-up structure is formed on the encapsulant. And electrically connecting the conductive blind via of the build-up structure to the semiconductor component and the ends of the conductive pillars.

Therefore, the present invention does not need to use the laser light of the prior art to form a plurality of through holes which are accurately aligned to the conductive blind holes of the build-up structure, and electrically connect the conductive blind vias of the build-up structure to The conductive pillar exposed by the encapsulant prevents the through hole of the prior art from being easily deviated from the end of the conductive blind hole to be erected to the dielectric layer, thereby eliminating the need for the through hole to be accurately The process to the conductive blind holes and related fixtures (such as laser devices).

Furthermore, the cross-sectional area of the conductive pillar of the present invention can be increased without being subject to Limited to the smaller cross-sectional area of the conductive blind vias, the contact area between the ends of the conductive pillars and the conductive vias can be increased to enhance the electrical conductivity between each other.

In addition, the present invention does not need to provide a third carrier plate of the prior art to reduce materials and reduce cost, and can also simplify the process of the semiconductor package of the prior art to facilitate implementation.

1, 2‧‧‧ semiconductor package

10, 20‧‧‧ first carrier board

11‧‧‧ wafer

11a, 21a‧‧‧ active face

11b, 21b‧‧‧ passive face

111, 211‧‧‧ solder pads

12, 23‧‧‧Package colloid

12a, 23a‧‧‧ first surface

12b, 23b‧‧‧ second surface

121, 231‧‧‧through holes

122‧‧‧End

123‧‧‧Aperture

13, 26‧‧‧Second carrier board

14, 27‧‧ ‧ layered structure

141, 271‧‧‧ dielectric layer

142, 272‧‧‧ conductive blind holes

143, 24‧‧‧ first line layer

144, 274‧‧‧Electrical contact pads

15, 25‧‧‧ first insulating protective layer

151, 282‧‧‧ metal layer under the bump

16‧‧‧ Third carrier board

161, 201‧‧‧ peeling layer

17‧‧‧ seed layer

171, 273‧‧‧ second circuit layer

18, 28‧‧‧Second insulation protection layer

181‧‧‧Opening

19, 29‧‧‧ solder balls

21‧‧‧Semiconductor components

22‧‧‧conductive column

22a‧‧‧First end

22b‧‧‧second end

251‧‧‧ first opening

281‧‧‧Second opening

H1, H2‧‧‧ height

SS‧‧‧ cutting line

1A to 1H are schematic cross-sectional views showing a semiconductor package of a prior art and a method of fabricating the same; and FIGS. 2A to 2F are cross-sectional views showing a semiconductor package of the present invention and a method of fabricating the same, wherein 2A' and 2B' are another embodiment of FIGS. 2A and 2B; and 3A to 3C are schematic cross-sectional views showing the manufacturing method of FIG. 2A.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. Technology disclosed by the invention The content can be covered.

At the same time, the terms "upper", "one", "first", "second", "surface", "active surface", "passive surface" and "end" are also used in this manual. For the sake of brevity, and not to limit the scope of the invention, the relative relationship changes or adjustments are considered to be within the scope of the invention.

2A to 2F are schematic cross-sectional views showing the semiconductor package 2 of the present invention and a method of manufacturing the same, wherein the 2A' and 2B' are another embodiment of the 2A and 2B.

As shown in FIG. 2A, a semiconductor element 21 (such as a wafer) having a height H1 and a conductive pillar 22 are disposed on a first carrier 20, and an encapsulant 23 having a first surface 23a and a second surface 23b opposite thereto is formed. The semiconductor device 21 and the conductive pillars 22 are embedded in the encapsulant 23 on the first carrier 20 .

In the present embodiment, the process of the structure shown in FIG. 2A can be referred to FIGS. 3A to 3C.

As shown in FIG. 3A, a first carrier 20 and a semiconductor component 21 (such as a wafer) having a height H1 are provided, and the semiconductor component 21 is disposed on the first carrier 20. The semiconductor device 21 has a plurality of pads 211, an opposite active surface 21a and a passive surface 21b, and the pads 211 and the active surface 21a face the first carrier 20.

In this embodiment, the first carrier 20 can also have a peeling layer 201. The semiconductor component 21 is disposed on the peeling layer 201, and the peeling layer 201 can be a release film or an adhesive layer.

As shown in FIG. 3B, a plurality of conductive pillars 22 having a height H2 are provided, and the conductive pillars 22 are disposed on the peeling layer 201 of the first carrier board 20. The conductive post 22 has an opposite first end 22a and a second end 22b, and the first end 22a faces the first carrier 20.

The conductive pillars 22 may be a cylinder, an elliptical cylinder, a polygonal cylinder or a spherical cylinder, and the conductive pillars 22 may be made of gold, silver, copper, tin or alloys thereof. In this embodiment, the height H2 of the conductive pillars 22 is higher than the height H1 of the semiconductor component 21, but is not limited thereto.

As shown in FIG. 3C, the encapsulant 23 having the opposite first surface 23a and the second surface 23b is formed on the peeling layer 201 of the first carrier 20 to embed the semiconductor component 21 and the conductive pillars 22 The second end portion 22b of the conductive pillars 22 is exposed from the second surface 23b of the encapsulant 23, and the first surface 23a of the encapsulant 23 is active with the semiconductor component 21. Face 21b is on the same side. The encapsulant 23 may have the same height H2 as the conductive post 22, but is not limited thereto.

Then, a thinning process is performed, and a part of the encapsulant 23 and the conductive pillars 22 are removed from the second surface 23b, thereby thinning the height H2 of the encapsulant 23 and the conductive pillars 22 to a height H1. The passive surface 21b of the semiconductor component 21 is exposed, so that the second surface 23b of the encapsulant 23 and the second end 22b of the conductive pillars 22 are flush with the passive surface 21b of the semiconductor component 21, as shown in FIG. 2A. Show.

In other embodiments, in the processes of the third to third embodiments, the semiconductor device 21 having the same height H1, the conductive pillar 22, and the encapsulant 23 as shown in FIG. 2A can be directly used, thereby omitting the thinning process. .

As shown in FIG. 2B, the first circuit layer 24 is formed on the second surface 23b of the encapsulant 23 to electrically connect the second end portions 22b of the conductive pillars 22.

Next, a first insulating protective layer 25 is formed on the passive surface 21b of the semiconductor element 21 and the second surface 23b of the encapsulant 23 to cover the first wiring layer 24. The first insulating protective layer 25 has a plurality of A portion of the first wiring layer 24 is exposed outside an opening 251.

In addition, as shown in FIGS. 2A' and 2B', another embodiment of FIGS. 2A and 2B is different from the 2A and 2B drawings in that the embedded portions are Before the conductive pillars 22 are in the encapsulant 23, the first wiring layer 24 is formed on the second surface 23b of the encapsulant 23.

As shown in FIG. 2C, the second FIG. 2B is connected, and the second carrier 26 is disposed on the first insulating protective layer 25. Then, the entire structure of FIG. 2C is inverted upside down, and the first carrier plate 20 is removed by removing the peeling layer 201, thereby exposing the active surface of the semiconductor component 21 from the first surface 23a of the encapsulant 23. 21a and the first end 22a of the conductive pillars 22.

FIG. 2C is further connected to FIG. 2B′, and after the first carrier 20 is removed, a plurality of through holes 231 penetrating through the first surface 23a and the second surface 23b of the encapsulant 23 are formed to respectively expose portions. The first circuit layer 24 is further filled with a conductive material (such as a copper material or a tin material) in the through holes 231 to form a plurality of conductive pillars 22 having a first end portion 22a and a second end portion 22b, and the conductive layers are electrically conductive. The pillars 22 are electrically connected to the first circuit layer 24 exposed by the through holes 231, respectively.

In addition, in other embodiments, the first circuit layer 24 is formed on the second surface 23b of the encapsulant 23 while the conductive pillars 22 are embedded in the encapsulant 23.

As shown in FIG. 2D, a build-up structure 27 is formed on the active surface 21a of the semiconductor component 21 and the first surface 23a of the encapsulant 23, and electrically connected to the build-up structure 27 to the pad of the semiconductor component 21. 211 and the first end portion 22a of the conductive pillars 22.

The build-up structure 27 can be a fan-out structure and has at least one dielectric layer 271, a plurality of conductive vias 272 formed in the dielectric layer 271, and at least one formed on the dielectric layer 271 and electrically connected. The second wiring layer 273 of the conductive vias 272, the conductive vias 272 in the innermost dielectric layer 271 are electrically connected to the pads 211 of the semiconductor component 21 and the first ends of the conductive pillars 22 The portion 22a of the second circuit layer 273 has a plurality of electrical contact pads 274. In this embodiment, the build-up structure 27 is composed of a three-layer dielectric layer 271, a three-layer conductive blind via 272, and a three-layer second trace layer 273, but is not limited thereto.

Next, a second insulating protective layer 28 is formed on the outermost dielectric layer 271 and the second wiring layer 273. The second insulating protective layer 28 has a plurality of second openings 281 and the second outermost layer is exposed. The electrical contact pads 274 of the circuit layer 273.

As shown in FIG. 2E, the first insulating layer 25 and the first circuit layer 24 of the first openings 251 are exposed outside the second carrier 26, and a plurality of under bump metal layers 282 are formed thereon. The second opening 281 is exposed on the electrical contact pad 274.

As shown in FIG. 2F, the singulation operation is performed on the entire structure according to the plurality of dicing lines SS of FIG. 2E, and a plurality of solder balls 29 are formed on the underlying metal layers 282, thereby forming a plurality of semiconductors. Package 2.

The present invention further provides a semiconductor package 2, as shown in FIG. 2F, comprising an encapsulant 23, a semiconductor component 21, a plurality of conductive pillars 22, and a build-up structure 27.

The encapsulant 23 has opposing first and second surfaces 23a, 23b. The semiconductor component 21 (such as a wafer) is embedded in the encapsulant 23 and has a plurality of pads 211, an opposite active surface 21a and a passive surface 21b, and the active surface 21a is connected to the first surface 23a of the encapsulant 23. The same side.

The conductive pillars 22 are embedded in the encapsulant 23, and the conductive pillars 22 have opposite first and second end portions 22a and 22b, respectively, and are exposed on the first surface 23a of the encapsulant 23, respectively. Two surfaces 23b. At the same time, the conductive pillar 22 is a cylinder, an elliptical cylinder, a polygonal cylinder or a spherical cylinder, and the material of the conductive pillar 22 is gold, silver, copper, tin or alloy thereof.

The build-up structure 27 can be a fan-out structure formed on the active surface 21a of the semiconductor component 21 and the first surface 23a of the encapsulant 23, and electrically connected to the pad 211 of the semiconductor component 212 and the conductive The first end 22a of the post 22.

The semiconductor package 2 can include a first circuit layer 24 formed on the second surface 23b of the encapsulant 23 to electrically connect the second ends 22b of the conductive pillars 22.

The semiconductor package 2 may include a first insulating protective layer 25 formed on the passive surface 21b of the semiconductor component 21 and the second surface 23b of the encapsulant 23 to cover the first wiring layer 24, and the first The insulating protective layer 25 has a plurality of first openings 251 and a portion of the first wiring layer 24 exposed.

The build-up structure 27 can have at least one dielectric layer 271, a plurality of conductive vias 272 formed in the dielectric layer 271, and at least one formed on the dielectric layer 271 and electrically connected to the conductive vias 272. The second circuit layer 273, the conductive via 272 in the innermost layer of the dielectric layer 271 is electrically connected to the pad 211 of the semiconductor component 21 and the first end 22a of the conductive pillars 22, the second Circuit layer 273 has a plurality of electrical contact pads 274. In this embodiment, the build-up structure 27 is composed of a three-layer dielectric layer 271, a three-layer conductive blind via 272, and a three-layer second trace layer 273, but is not limited thereto.

The semiconductor package 2 may include a second insulating protective layer 28 formed on the outermost dielectric layer 271 and the second wiring layer 273, and the second insulating protective layer 28 has a plurality of second openings 281. The electrical contact pads 274 of the second circuit layer 273 of the outermost layer are exposed.

The semiconductor package 2 can include a plurality of under bump metal layers 282 and a plurality of solder balls 29, and the under bump metal layers 282 are respectively formed on the electrical contact pads 274 exposed by the second openings 281, and The solder balls 29 are respectively formed on the under bump metal layers 282.

As can be seen from the above, in the semiconductor package of the present invention and the method of manufacturing the same, the semiconductor element and the plurality of conductive pillars are embedded in the encapsulant and the ends of the conductive pillars are exposed, and the build-up structure is formed on the encapsulant. On, again Conductive blind vias of the build-up structure are electrically connected to the semiconductor component and the ends of the conductive pillars.

Therefore, the present invention does not need to use the laser light of the prior art to form a plurality of through holes which are accurately aligned to the conductive blind holes of the build-up structure, and electrically connect the conductive blind vias of the build-up structure to The conductive pillar exposed by the encapsulant prevents the through hole of the prior art from being easily deviated from the end of the conductive blind hole to be erected to the dielectric layer, thereby eliminating the need for the through hole to be accurately The process to the conductive blind holes and related fixtures (such as laser devices).

Furthermore, the cross-sectional area of the conductive pillar of the present invention can be increased without being limited by the smaller cross-sectional area of the conductive blind vias, so that the contact area between the ends of the conductive pillars and the conductive blind vias can be increased. And enhance the electrical conductivity between each other.

In addition, the present invention does not need to provide a third carrier plate of the prior art to reduce materials and reduce cost, and can also simplify the process of the semiconductor package of the prior art to facilitate implementation.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be as set forth in the appended claims.

2‧‧‧Semiconductor package

21‧‧‧Semiconductor components

21a‧‧‧Active face

21b‧‧‧ Passive

211‧‧‧ solder pads

22‧‧‧conductive column

22a‧‧‧First end

22b‧‧‧second end

23‧‧‧Package colloid

23a‧‧‧ first surface

23b‧‧‧ second surface

24‧‧‧First line layer

25‧‧‧First insulation protection layer

251‧‧‧ first opening

27‧‧‧Additional structure

271‧‧‧ dielectric layer

272‧‧‧conductive blind holes

273‧‧‧Second circuit layer

274‧‧‧Electrical contact pads

28‧‧‧Second insulation protection layer

281‧‧‧Second opening

282‧‧‧ Metal layer under the bump

29‧‧‧ solder balls

Claims (21)

A semiconductor package comprising: an encapsulant having opposite first and second surfaces; a semiconductor component embedded in the encapsulant and having opposite active and passive faces, and the active surface is exposed a first surface of the encapsulant; a plurality of conductive pillars embedded in the encapsulant, and the conductive pillars have opposite first and second ends to respectively expose the first surface of the encapsulant And a second surface; and a build-up structure formed on the first surface of the encapsulant and electrically connected to the semiconductor element and the first ends of the conductive pillars. The semiconductor package of claim 1, wherein the conductive pillar is a cylinder, an elliptical cylinder, a polygonal cylinder or a spherical cylinder. The semiconductor package of claim 1, wherein the conductive pillar is made of gold, silver, copper, tin or an alloy thereof. The semiconductor package of claim 1, further comprising a first circuit layer formed on the second surface of the encapsulant to electrically connect the second ends of the conductive pillars. The semiconductor package of claim 1, further comprising a first insulating protective layer formed on the passive surface of the semiconductor component and the second surface of the encapsulant to encapsulate the first wiring layer, and The first insulating protective layer has a portion of the first wiring layer exposed outside the plurality of first openings. The semiconductor package of claim 1, wherein the build-up structure has at least one dielectric layer, a plurality of conductive blind vias formed in the dielectric layer, and at least one formed on the dielectric layer And electrically connecting the second circuit layers of the conductive blind holes, and the second circuit layer has a plurality of electrical contact pads. The semiconductor package of claim 6, further comprising a second insulating protective layer formed on the dielectric layer of the outermost layer and the second wiring layer, wherein the second insulating protective layer has a plurality of An electrical contact pad of the second circuit layer of the outermost layer is exposed outside the second opening. The semiconductor package of claim 7, further comprising a plurality of under bump metal layers and a plurality of solder balls, wherein the underlying metal layers are respectively formed in electrical contacts exposed by the second openings Pads, and the solder balls are respectively formed on the underlying metal layers of the bumps. A method of fabricating a semiconductor package, comprising: embedding a semiconductor component and a plurality of conductive pillars in a package body having opposite first and second surfaces, wherein the semiconductor component has opposite active and passive faces, and The active surface is exposed on the first surface of the encapsulant, the conductive post has opposite first and second ends, and the first end of the conductive posts is exposed to the first of the encapsulant And forming a build-up structure on the first surface of the encapsulant, and the build-up structure electrically connects the semiconductor element and the first ends of the conductive pillars. For example, the method for manufacturing a semiconductor package as described in claim 9 is The conductive pillar is a cylinder, an elliptical cylinder, a polygonal cylinder or a spherical cylinder. The method of manufacturing a semiconductor package according to claim 9, wherein the process before forming the build-up structure comprises: providing a first carrier plate on which the semiconductor component is disposed, the active surface facing the first a carrier plate; the conductive pillars are disposed on the first carrier plate, the first end portion faces the first carrier plate; the package body is formed on the first carrier plate to embed the semiconductor component and the a conductive pillar is disposed in the encapsulant and exposing the second ends of the conductive pillars from the second surface of the encapsulant; and removing the first carrier to expose the first surface of the encapsulant An active surface of the semiconductor component and a first end of the conductive pillars. The method of fabricating a semiconductor package according to claim 11, wherein the first carrier has a release layer, and the semiconductor component, the conductive pillar and the encapsulant system are located on the release layer. The method of fabricating a semiconductor package according to claim 11, further comprising thinning the encapsulant from the second surface and exposing a passive surface of the semiconductor element outside the conductive pillars. The method of fabricating a semiconductor package according to claim 11, wherein the second carrier is disposed on the second surface of the encapsulant prior to removing the first carrier. For example, the method for manufacturing a semiconductor package as described in claim 9 is The method further includes forming a first circuit layer on the second surface of the encapsulant to electrically connect the second ends of the conductive pillars. The method for manufacturing a semiconductor package according to claim 9 further comprises forming a first circuit layer on the second surface of the encapsulant before embedding the conductive pillars in the encapsulant. The method for manufacturing a semiconductor package according to claim 9 further comprises: forming a first wiring layer on the second surface of the encapsulant while embedding the conductive pillars in the encapsulant. The method of fabricating a semiconductor package according to claim 15, wherein the first insulating protective layer is formed on the passive surface of the semiconductor component and the second surface of the encapsulant. The first circuit layer is covered, and the first insulating protection layer has a portion of the first circuit layer exposed outside the plurality of first openings. The method of fabricating a semiconductor package according to claim 9, wherein the build-up structure has at least one dielectric layer, a plurality of conductive blind vias formed in the dielectric layer, and at least one formed in the dielectric layer The second circuit layer of the conductive blind holes is electrically connected to the electrical layer, and the second circuit layer has a plurality of electrical contact pads. The method of fabricating a semiconductor package according to claim 19, further comprising forming a second insulating protective layer on the outermost layer of the dielectric layer and the second wiring layer, the second insulating protective layer having a plurality of An electrical contact pad of the second circuit layer of the outermost layer is exposed outside the two openings. The method for manufacturing a semiconductor package as described in claim 20, comprising: Forming a plurality of under bump metal layers on the electrical contact pads exposed by the second openings; performing a singulation operation; and forming a plurality of solder balls on the underlying metal layers of the bumps.