TW201607883A - Method for producing a micromechanical component and a correspondingly produced micromechanical component - Google Patents
Method for producing a micromechanical component and a correspondingly produced micromechanical component Download PDFInfo
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- TW201607883A TW201607883A TW104116621A TW104116621A TW201607883A TW 201607883 A TW201607883 A TW 201607883A TW 104116621 A TW104116621 A TW 104116621A TW 104116621 A TW104116621 A TW 104116621A TW 201607883 A TW201607883 A TW 201607883A
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- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000009736 wetting Methods 0.000 claims description 10
- 230000004913 activation Effects 0.000 claims description 5
- 238000012856 packing Methods 0.000 claims description 5
- 230000001154 acute effect Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001994 activation Methods 0.000 claims 3
- 238000000678 plasma activation Methods 0.000 claims 1
- 238000005496 tempering Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 13
- 235000012431 wafers Nutrition 0.000 description 37
- 238000012545 processing Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 238000004513 sizing Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000007688 edging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002118 epoxides Chemical class 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
本發明係有關於一種製造包含半導體晶片之構件的方法，以及一種用此方法製造的構件。 The present invention relates to a method of fabricating a component comprising a semiconductor wafer, and a component fabricated by the method.
在製造微機械或微電子構件時，通常將半導體晶片設置至一載體基板上，以便對半導體晶片進行進一步處理。其中為進行接觸，藉由接合連接件或其他電接觸件為此等半導體晶片(例如感測器元件(MEMS)、ASIC等)與該基板或與位於此基板上之接觸面建立電連接。為對MEMS與基板的連接進行改進，可設有MEMS的底部填充物，其至少部分地將位於此基板與此MEMS間的中間腔填充。可採用施膠法來設置此底部填料，其中將液態的底部填料以接近待底部填充區域的方式設置至基板上。一旦此具流散及潤濕特性的底部填料到達此MEMS，毛細力便立即起作用，從而對MEMS實現儘可能均勻的底部填充。為對底部填料的側向流出進行抑制，在基板上必須針對此具流散特性的材料設有對應的保持件。此外，採用施膠法時的製程波動可能會導致底部填料濺在MEMS或基板上的其他地點上。 In the fabrication of micromechanical or microelectronic components, a semiconductor wafer is typically placed onto a carrier substrate for further processing of the semiconductor wafer. In order to make contact, a semiconductor wafer (eg, a sensor element (MEMS), an ASIC, etc.) is electrically connected to the substrate or a contact surface on the substrate by bonding a connector or other electrical contact. To improve the connection of the MEMS to the substrate, a MEMS underfill may be provided that at least partially fills the intermediate cavity between the substrate and the MEMS. This underfill can be provided by a sizing process in which a liquid underfill is placed on the substrate in a manner close to the area to be underfilled. Once the underfill with the dispersive and wetting properties reaches the MEMS, the capillary forces act immediately, thereby achieving as uniform an underfill as possible for the MEMS. In order to suppress the lateral outflow of the underfill, a corresponding retaining member must be provided on the substrate for the material having the dispersive properties. In addition, process fluctuations in the sizing process may cause the underfill to splash on other locations on the MEMS or substrate.
舉例而言，DE 10 2005 037 948 A1描述過一種底部填充物， 其中設有止流元件，以防止此填料的意外擴散。 For example, DE 10 2005 037 948 A1 describes an underfill, A stop element is provided therein to prevent accidental diffusion of the filler.
DE 10 2004 051 468 A1公開過另一結構，其中在感測器晶片 之敏感區域的下方設有一凹口。此凹口提供一邊沿，其用作針對底部填充物的脫離區域，從而防止底部填充物進入膜片區域。 Another structure is disclosed in DE 10 2004 051 468 A1, in which the sensor wafer There is a notch below the sensitive area. This notch provides an edge that acts as a detachment area for the underfill to prevent the underfill from entering the diaphragm area.
DE 10 2011 084 582 B3公開過對通孔的應用，其中隨後進行 填充，以便插入一接合連接件。 DE 10 2011 084 582 B3 discloses the use of through holes, which are subsequently carried out Fill to insert a joint connector.
本發明提出一種在基板上對半導體晶片，特別是對MEMS進行底部填充的方法，以及一種用此方法製造的構件。其中，既將一半導體晶片，亦將一底部填料設置至一基板上，隨後使用該底部填料對位於該半導體晶片與該基板間的中間腔的至少一部分進行填充或底部填充。本發明之核心在於，在該基板中產生至少一用於容置該底部填料的保持容積。 The present invention provides a method of underfilling a semiconductor wafer, particularly a MEMS, on a substrate, and a member fabricated by this method. Wherein, a semiconductor wafer is also disposed on a substrate, and then at least a portion of the intermediate cavity between the semiconductor wafer and the substrate is filled or underfilled using the underfill. The core of the invention consists in producing at least one holding volume for accommodating the underfill in the substrate.
藉由此設計方案，在製造過程中能夠針對性地將該底部填料設置至一位於該基板上的特定區域上，而不會對鄰接區域造成非期望的污染。此外，亦能夠透過此存放方案對底部填料的量進行限制，因為在該基板之表面上不會發生計劃外的流散。 With this design, the underfill can be targeted to a specific area on the substrate during the manufacturing process without undesired contamination of the adjacent area. In addition, the amount of underfill can also be limited by this storage scheme because no unplanned dispersion occurs on the surface of the substrate.
較佳以與該半導體晶片之在基板上的設置地點空間鄰近的方式產生該保持容積。舉例而言，可直接在該基板中構建出該實施為第一凹槽的保持容積。為建立該底部填料之流動能力的較佳方向，根據一種可選方案，該第一凹槽之與該設置地點更為接近的壁部呈傾斜狀，例如具有一銳角。作為替代方案，該保持容積亦可實施為位於該基板上的邊框。在此情形下，可在該基板上產生若干壁部，以便將該底部填料送入。為在此 亦實現該流動能力的較佳方向，該與設置地點更為接近的壁部的至少一部分的高度可比該邊框之其餘部分有所減小。 The retention volume is preferably created in a manner adjacent to the location of the semiconductor wafer on the substrate. For example, the holding volume embodied as a first groove can be constructed directly in the substrate. In order to establish a preferred direction of flowability of the underfill, according to an alternative, the wall of the first recess which is closer to the installation location is inclined, for example having an acute angle. Alternatively, the holding volume can also be embodied as a bezel on the substrate. In this case, a plurality of walls may be created on the substrate to feed the underfill. For here A preferred direction of the flow capability is also achieved, and the height of at least a portion of the wall portion that is closer to the location may be reduced than the remainder of the bezel.
根據本發明的另一設計方案，在該基板中產生第二凹槽。可 將該半導體晶片送入此第二凹槽。透過位於該二凹槽間之連接件，例如溝槽或通道，該底部填料能夠自該第一凹槽流入該第二凹槽。根據一種可選方案，該第二凹槽之深度比該第一凹槽更大，故在適宜的流動條件下該底部填料能夠自該第一凹槽流至該第二凹槽。 According to a further refinement of the invention, a second recess is produced in the substrate. can The semiconductor wafer is fed into the second recess. The underfill can flow from the first groove into the second groove through a joint between the two grooves, such as a groove or a passage. According to an alternative, the second groove has a greater depth than the first groove, so that the underfill can flow from the first groove to the second groove under suitable flow conditions.
根據本發明的一種改進方案，在對該位於半導體晶片與基板 間的中間腔進行填充時，使用一特別的激活步驟來實施底部填充。其中，透過適宜的處理條件將該底部填料之流動能力增大至能夠實際發生流動的程度。例如可透過相應提昇溫度或採用特別的環境氛圍來實現此點。亦可藉由對該基板之表面特性的針對性改變來對該底部填料之流動能力進行控制。舉例而言，可在該底部填料發生沈積前透過電漿處理將該基板表面激活，從而增強該底部填料之流動能力。 According to a further development of the invention, the semiconductor wafer and the substrate are When the intermediate chamber is filled, a special activation step is used to perform the underfill. Among them, the flow capacity of the underfill material is increased to a degree that can actually flow through appropriate processing conditions. This can be achieved, for example, by a corresponding elevated temperature or by using a special ambient atmosphere. The flowability of the underfill can also be controlled by a targeted change in the surface properties of the substrate. For example, the surface of the substrate can be activated by plasma treatment prior to deposition of the underfill to enhance the flowability of the underfill.
根據一種尤佳方案，採用至少兩個不同的底部填料，其位於 不同的保持容積中並具有不同的潤濕能力及/或流動能力。如此便能透過針對性的處理條件使得該二底部填料在不同的時間點上發生流散，從而在實施填充或鈍化時實現不同的目的。 According to a preferred embodiment, at least two different underfills are used, which are located Different holding volumes have different wetting and/or flow capabilities. In this way, the two underfills can be dispersed at different points in time through targeted processing conditions, thereby achieving different purposes in carrying out filling or passivation.
根據本發明的一種設計方案，不論是在該基板中還是在該基 板上產生該保持容積，皆可將該保持容積用作針對接合連接件的接觸區域。藉由隨後將該底部填料送入該保持容積，便能對該接觸件進行鈍化。 According to one embodiment of the invention, whether in the substrate or at the base This holding volume is produced on the plate, which can be used as a contact area for the joint connection. The contact can be passivated by subsequently feeding the underfill into the holding volume.
其他優點參閱下文對實施例的說明及附屬項。 Other advantages are described in the following description of the embodiments and the accompanying items.
100‧‧‧基板 100‧‧‧Substrate
110‧‧‧凹槽 110‧‧‧ Groove
120‧‧‧半導體晶片 120‧‧‧Semiconductor wafer
130‧‧‧接觸件 130‧‧‧Contacts
140‧‧‧底部填料 140‧‧‧Bottom packing
150‧‧‧邊沿 150‧‧‧Edge
160‧‧‧凹槽 160‧‧‧ Groove
170‧‧‧接合連接件 170‧‧‧Joint connectors
200‧‧‧步驟 200‧‧‧ steps
220‧‧‧步驟 220‧‧‧Steps
230‧‧‧步驟 230‧‧‧Steps
240‧‧‧步驟 240‧‧‧ steps
250‧‧‧步驟 250‧‧‧ steps
260‧‧‧步驟 260‧‧‧Steps
280‧‧‧步驟 280‧‧ steps
圖1a及1b為本發明中的用覆晶技術製造的、包含位於基板上之半導體晶片的構件；圖2a及2b示出對底部填料的設置操作，以及該半導體晶片在底部填充完畢後的狀態；圖3示出本發明的一種替代性設計方案；圖4示出將保持容積用作接合連接件之接觸區域的應用；及圖5為流程圖，其中結合此圖對與製造相關的方法作進一步說明。 1a and 1b are members of a semiconductor wafer fabricated on a substrate by a flip chip technique according to the present invention; and FIGS. 2a and 2b illustrate the operation of setting the underfill and the state of the semiconductor wafer after the underfill is completed. Figure 3 shows an alternative design of the invention; Figure 4 shows the application of the holding volume as the contact area for the joint connector; and Figure 5 is a flow chart in which the manufacturing-related method is combined with this figure. Further explanation.
如前文所述，在採用覆晶技術來為半導體晶片與特別是由半導體構成的基板建立連接時，使用一底部填料來對位於半導體晶片與作為其基礎之基板間的區域進行最大程度的填充。透過此底部填充物便能對該區域及位於其中的接觸件進行鈍化及增強。 As described above, when a flip chip technique is employed to establish a connection between a semiconductor wafer and a substrate, particularly a semiconductor, an underfill is used to maximize filling of the region between the semiconductor wafer and the substrate underlying it. The area and the contacts located therein can be passivated and reinforced by the underfill.
就由半導體晶片120與基板100構成的構件而言，與常用結構的不同之處在於，本發明採用一保持容積，其中針對性地將底部填料140設置在該保持容積中。如圖1a及1b所示，此保持容積係實施為位於半導體晶片120附近的凹槽110。作為替代方案，在基板100上亦可設有透過壁部產生的鑲邊或邊框，從而實現此保持容積。如圖2a所示，可將底部填料140設置至凹槽110中，隨後此底部填料140因其流散特性而分佈在半導體晶片120之區域下。在較窄的中間腔中產生的毛細力能夠對此分佈，以及對位於半導體晶片120與基板100間的中間區域的填充提供支持。在底部填料140 充足的情況下，即便在無法將該中間腔完全填充時，此等毛細力亦能夠對該中間腔進行最大程度的填充。藉此亦能夠對半導體晶片120與基板100間可能設有的接觸件130或連接件進行包圍及必要的鈍化。在圖2b所示實施例中，基板100之邊沿150用作針對底部填料140的停止邊沿，在此等邊沿上產生相應的潤濕角。可透過此等邊沿的相應設計方案以及與所設置的半導體晶片的距離來改變此潤濕角。 In the case of a component consisting of the semiconductor wafer 120 and the substrate 100, the difference from the conventional structure is that the present invention employs a holding volume in which the underfill 140 is specifically disposed in the holding volume. As shown in FIGS. 1a and 1b, the retention volume is implemented as a recess 110 located adjacent the semiconductor wafer 120. Alternatively, a rim or a frame created by the wall portion may be provided on the substrate 100 to achieve the holding volume. As shown in FIG. 2a, the underfill 140 can be disposed into the recess 110, which is then distributed under the region of the semiconductor wafer 120 due to its flow characteristics. The capillary forces generated in the narrower intermediate cavities provide support for this distribution and for filling the intermediate regions between the semiconductor wafer 120 and the substrate 100. In the bottom filler 140 In sufficient circumstances, these capillary forces are capable of maximizing the filling of the intermediate chamber even when the intermediate chamber cannot be completely filled. Thereby, it is also possible to surround and possibly passivate the contact 130 or the connecting member which may be provided between the semiconductor wafer 120 and the substrate 100. In the embodiment shown in Figure 2b, the rim 150 of the substrate 100 acts as a stop edge for the underfill 140, on which a corresponding wetting angle is created. This wetting angle can be varied by the corresponding design of the edges and the distance from the semiconductor wafer being placed.
為對流散及填充提供支持，根據一種可選方案，凹槽110 之與半導體晶片120，或與此半導體晶片之位於基板100上的容置區域更為接近的壁部呈傾斜狀，例如呈銳角狀。藉此對該底部填料之流動方向進行預設，以及對流散進行簡化。在採用邊框來構成該保持容積的情況下，亦可減小該與半導體晶片120更為接近的壁部的高度。 To support flow and fill, according to an alternative, the groove 110 The wall portion closer to the semiconductor wafer 120 or the semiconductor wafer on the substrate 100 is inclined, for example, in an acute angle. Thereby, the flow direction of the underfill is preset, and the flow is simplified. In the case where the holding volume is configured by a bezel, the height of the wall portion closer to the semiconductor wafer 120 can also be reduced.
作為替代或附加方案，該保持容積之溝槽或通道可實施為設 於該基板中或該基板上的凹槽或邊框，以便對該底部填料之流動方向進行預設以及對流散提供支持。 As an alternative or in addition, the groove or channel for retaining the volume can be embodied as A groove or bezel in the substrate or on the substrate to preset the flow direction of the underfill and to support the flow.
圖3示出本發明的一種替代性實施方式。在此情形下，除凹 槽110外，在基板100中還設置有另一凹槽160，其中設有半導體晶片120，或者還設有接觸件130或連接件。在如圖3所示使得凹槽110與160彼此連通的情況下，能夠對底部填料140的流散進行簡化。 Figure 3 illustrates an alternate embodiment of the present invention. In this case, except for the concave Outside the slot 110, another recess 160 is provided in the substrate 100, in which the semiconductor wafer 120 is provided, or a contact 130 or a connector is also provided. In the case where the grooves 110 and 160 are communicated with each other as shown in FIG. 3, the flow dispersion of the underfill 140 can be simplified.
根據一種可選方案，在凹槽110與160並非緊鄰的情況下， 亦可透過通道或溝槽來產生連接，從而對流散提供支持。 According to an alternative, in the case where the grooves 110 and 160 are not in close proximity, It is also possible to create a connection through a channel or a groove to support the dispersion.
根據本發明的另一實施方式，亦可將該保持容積及位於其中 的底部填料用作接觸區域。舉例而言，圖4便示出一此類實施方式，在該 實施方式中，在凹槽110之底部上以某種方式設置有基板100與半導體晶片120的接合連接件，使得底部填料140不僅對位於半導體晶片120與基板100間之中間區域，亦對接合連接件170之腳部進行遮蓋、鈍化及保護。 According to another embodiment of the present invention, the holding volume can also be located therein The underfill is used as the contact area. For example, Figure 4 shows an embodiment in which In an embodiment, the bonding connection between the substrate 100 and the semiconductor wafer 120 is disposed on the bottom of the recess 110 in such a manner that the underfill 140 is not only located in the middle region between the semiconductor wafer 120 and the substrate 100, but also in the joint connection. The foot of the piece 170 is covered, passivated and protected.
結合圖5所示流程圖，對製造由半導體晶片120與(例如由 半導體構成之)基板100構成的構件時的主要步驟，包括對該中間區域之填充操作進行說明。在步驟200中，以某種方式對採用的基板100進行構造化，從而產生一用於構成保持容積的凹槽110。其中在採用半導體基板時，可採用常用的微機械方法，例如磊晶法、遮蔽或(溝槽)蝕刻步驟。可獨立地採用此等微機械處理步驟，或者將其與在基板製程中產生導電通路層及/或絕緣層的方案相組合。作為替代方案，亦可透過(相應的)微機械方法在(半導體)基板100上產生一鑲邊。隨後，在步驟220中例如藉由覆晶技術將半導體晶片120設置在基板100上，較佳設置在該保持容積附近。在此情形下，既可用接觸件130，亦可用若干連接件來對該半導體晶片進行支撐。在另一步驟260中，例如藉由施膠法或噴射施膠法將底部填料140送入該保持容積。為將該基板充分潤濕，以及對該中間區域進行填充，需要將充足的底部填料送入該保持容器，具體方式例如為，使得底部填料140澈底高出該基板表面(例如參閱圖2a)。 In conjunction with the flow chart shown in Figure 5, the fabrication is performed by the semiconductor wafer 120 (for example by The main steps in the case of a member composed of a substrate 100 include a filling operation of the intermediate portion. In step 200, the employed substrate 100 is structured in a manner to create a recess 110 for forming a holding volume. Where a semiconductor substrate is employed, conventional micromechanical methods such as epitaxing, masking or (trench) etching steps may be employed. These micromechanical processing steps can be employed independently or in combination with a scheme for creating a conductive via layer and/or insulating layer in a substrate process. Alternatively, a edging can also be produced on the (semiconductor) substrate 100 by a (corresponding) micromechanical method. Subsequently, in step 220, the semiconductor wafer 120 is disposed on the substrate 100, for example by flip chip technology, preferably disposed adjacent the holding volume. In this case, the semiconductor wafer can be supported by either the contact member 130 or a plurality of connectors. In a further step 260, the underfill 140 is fed into the holding volume, for example by sizing or spray sizing. In order to sufficiently wet the substrate and fill the intermediate region, sufficient underfill material is required to be fed into the holding container, for example, such that the underfill 140 is raised above the substrate surface (see, for example, Figure 2a).
一旦該具流散/潤濕特性的底部填料140越過凹槽110或該 邊框之邊緣並到達MEMS 120之邊沿，毛細力立即起作用，從而在材料充足的情況下對半導體晶片120進行最大程度的乃至完全的填充(參閱圖2b)。其中，該保持容積構成針對後續流動之底部填料140的儲存器。同時，該保持容積用作針對該材料之沿相反方向(朝向該基板邊沿)的過度流出 的攔阻槽。該基板之邊沿透過將該潤濕角增大而起到高效停止邊沿的作用。 Once the underfill/wetting property of the underfill 140 passes over the groove 110 or At the edge of the bezel and reaching the edge of the MEMS 120, the capillary forces act immediately to maximize or even completely fill the semiconductor wafer 120 with sufficient material (see Figure 2b). Therein, the holding volume constitutes a reservoir for the underlying flowing underfill 140. At the same time, the holding volume acts as an excessive flow out of the material in the opposite direction (towards the edge of the substrate) The blocking groove. The edge of the substrate acts to increase the wetting angle to effectively stop the edge.
根據一種可選方案，在將底部填料140送入後的另一步驟 280中，對底部填料140之流散進行激活。例如可透過適宜的處理條件實現此點，具體方式為提昇溫度或改變氛圍，從而增強該底部填料之流動特性。 According to an alternative, another step after the bottom packing 140 is fed In 280, the flow of the underfill 140 is activated. This can be achieved, for example, by suitable processing conditions, such as raising the temperature or changing the atmosphere to enhance the flow characteristics of the underfill.
根據一種可選方案，亦可在設置底部填料140前，對基板及 半導體晶片之待由該底部填料潤濕的表面實施一激活步驟250。如此便能相應地對該底部填料之流動能力進行改變。舉例而言，可在該底部填料發生沈積前透過電漿處理實現此點。 According to an alternative, the substrate and the substrate may be disposed before the underfill 140 is disposed. An activation step 250 is performed on the surface of the semiconductor wafer to be wetted by the underfill. This makes it possible to change the flow capacity of the underfill accordingly. For example, this can be achieved by plasma treatment prior to deposition of the underfill.
此外，可在另一步驟240中，在將底部填料140送入前，將 一接合連接件170設置至該保持容積中，例如設置至凹槽110之底部上。 In addition, in another step 240, before the bottom packing 140 is fed, A joint connector 170 is disposed into the retaining volume, for example, to the bottom of the recess 110.
根據另一實施例，可採用至少兩個不同的底部填料，較佳可 藉由不同的處理參數對此等底部材料的流動進行激活。如此便能針對性地在所期望的時間點上將該等不同的材料分佈在該基板上或設置在該中間區域內。此外，該等不同的底部填料亦可具有不同的潤濕特性。其中，該等不同的底部填料可放置在不同的保持容積中。 According to another embodiment, at least two different underfills may be employed, preferably The flow of these bottom materials is activated by different processing parameters. In this way, the different materials can be distributed on the substrate or in the intermediate region at the desired point in time. In addition, the different underfills may also have different wetting characteristics. Among them, the different underfills can be placed in different holding volumes.
此外，根據本發明，在該空穴之結構與該半導體晶片之待底 部填充區域之間亦可設置另一構造/構形(凹槽或凸起)，以對該底部填料的自該空穴至該半導體晶片的流動特性進行改進。基於同一原理，亦可設置其他用於防止該底部填料意外流入位於該基板上之不允許區域的構造/構形。舉例而言，在一個基板上需要採用多個組件/晶片，且僅需對個別組件進行底部填充的情況下，便會應用此原理。 Further, according to the present invention, the structure of the hole and the semiconductor wafer are to be bottomed. Another configuration/configuration (groove or protrusion) may also be provided between the filled regions to improve the flow characteristics of the underfill from the holes to the semiconductor wafer. Based on the same principle, other configurations/configurations for preventing the underfill from accidentally flowing into the impermissible area on the substrate may also be provided. For example, this principle is applied where multiple components/wafers are required on a substrate and only need to be underfilled for individual components.
根據本發明，亦可透過不同的材料潤濕特性對該基板進行構 造化。相應地透過各基板材料之潤濕能力對該底部填料之流動特性進行控制。 According to the present invention, the substrate can also be constructed by different material wetting characteristics. good fortune. Accordingly, the flow characteristics of the underfill are controlled by the wetting ability of each substrate material.
該等底部填料較佳係指填充有矽/氧化矽的環氧化物。但亦可採用其他具有與具體應用匹配之材料特性及間隙滲透特性的聚合物。 These underfills preferably refer to epoxides filled with cerium/yttria. However, other polymers having material properties and interstitial permeability characteristics that match the specific application may also be employed.
100‧‧‧基板 100‧‧‧Substrate
110‧‧‧凹槽 110‧‧‧ Groove
120‧‧‧半導體晶片 120‧‧‧Semiconductor wafer
130‧‧‧接觸件 130‧‧‧Contacts
140‧‧‧底部填料 140‧‧‧Bottom packing
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| DE102004051468A1 (en) | 2004-10-22 | 2006-04-27 | Robert Bosch Gmbh | Method for mounting semiconductor chips and corresponding semiconductor chip arrangement |
| DE102005037948A1 (en) | 2005-08-11 | 2007-02-15 | Robert Bosch Gmbh | Sensor arrangement with a sensor component and a carrier and method for producing a sensor arrangement |
| US8796075B2 (en) * | 2011-01-11 | 2014-08-05 | Nordson Corporation | Methods for vacuum assisted underfilling |
| DE102011084582B3 (en) | 2011-10-17 | 2013-02-21 | Robert Bosch Gmbh | Micromechanical sensor device, particularly micromechanical pressure sensors, microphones, acceleration sensors or optical sensors, has substrate, circuit chip fixed on substrate and mold package, in which circuit chip is packaged |
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