TW201503312A - Electrostatic discharge protection structure - Google Patents

Abstract

Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.

Description

Electrostatic discharge protection structure

This invention relates to a semiconductor component, and more particularly to an electrostatic discharge protection structure.

Electrostatic discharge (ESD) is a phenomenon in which charges accumulate on a non-conductor or an ungrounded conductor and then rapidly move (discharge) in a short time via a discharge path. Electrostatic discharge can damage circuits formed by components of an integrated circuit. For example, a human body, a machine that houses an integrated circuit, or a device that tests an integrated circuit are common charged bodies, and when the charged body is in contact with the wafer, it is possible to discharge the wafer. The instantaneous power of the electrostatic discharge can cause damage or failure of the integrated circuit in the wafer.

Generally, the electrostatic discharge tolerance of commercial integrated circuits must be tested by Human Body Model (HBM) 2 kV and Machine Discharge Mode (MM) 200 V. In order to withstand such high voltage electrostatic discharge tests, electrostatic discharge protection components on integrated circuits often have large component size designs. In order to save as much as possible on the die area, such large-sized components are usually implemented in a multi-finger manner on the layout. Finger-shaped protective element The area of the die can be saved, but this layout often causes problems with non-uniform turn-on of the component.

The invention provides an electrostatic discharge protection structure, which can improve the robustness of the electrostatic discharge protection structure.

The invention provides an electrostatic discharge protection structure, which can make the opening time of each parasitic BJT substantially the same.

The present invention provides an electrostatic discharge protection structure including a substrate, a pick up region, a first MOS device, a second MOS device, a first doped region, and a first doped region. A pick up zone is located in the substrate. A first MOS device is disposed on the substrate and includes a first drain region having a first conductivity type. A second MOS device is disposed on the substrate and includes a second drain region having a first conductivity type. The first bungee region is closer to the contact region than the second bungee region. The first doped region has a second conductivity type and is located below the first drain region. a second doped region having a second conductivity type, located below the second drain region, wherein an area, a doping concentration, or both of the first doped region is greater than an area of the second doped region, a doping concentration Or both.

According to an embodiment of the invention, the first conductivity type is an N type, and the second conductivity type is a P type.

According to an embodiment of the invention, the first conductivity type is a P type, and the second conductivity type is an N type.

According to an embodiment of the invention, the first oxynitride semiconductor element and the second oxynitride semiconductor device are juxtaposed into a finger-shaped MOS device.

According to an embodiment of the invention, the first oxynitride semiconductor element and the second oxynitride semiconductor component are Waffle MOS devices.

According to an embodiment of the invention, the contact region is annular, and the first oxynitride semiconductor element and the second MOS device are located within a region surrounded by the contact region.

The invention also provides an electrostatic discharge protection structure comprising: a substrate, a contact region, a plurality of MOS devices, and a plurality of doped regions. A pick up zone is located in the substrate. A plurality of MOS devices are located on the substrate and each have a first conductivity type drain region. A plurality of doped regions have a second conductivity type and are respectively located below the above-described drain regions of the respective MOS devices. The area, the doping concentration, or both of the doped regions far from the contact region to the contact region are gradually increased.

According to an embodiment of the invention, the first conductivity type is an N type, and the second conductivity type is a P type.

According to an embodiment of the invention, the first conductivity type is a P type, and the second conductivity type is an N type.

According to an embodiment of the invention, the first oxynitride semiconductor element and the second oxynitride semiconductor device are juxtaposed into a finger-shaped MOS device.

According to an embodiment of the invention, the first oxynitride semiconductor element and the second oxynitride semiconductor component are Waffle MOS devices.

According to an embodiment of the invention, the contact region is annular, and the first oxynitride semiconductor element and the second MOS device are located within a region surrounded by the contact region.

Based on the above, the present invention provides an electrostatic discharge protection structure in a bungee The doping region different from the conductivity type under the region can improve the soundness of the electrostatic discharge protection structure, and the doping region and the contact can be corrected by changing the area/doping concentration of the doping region under the drain region. The difference in the distance between the regions makes the breakdown voltage of each parasitic BJT substantially the same, and the conduction time of each BJT can be made almost the same.

The above described features and advantages of the present invention will be more apparent from the following description.

10‧‧‧Base

20‧‧‧First MOS components

22‧‧‧First gate structure

24‧‧‧First source area

24a, 26a, 34a, 36a, 50a, 74a‧‧‧ contact windows

26‧‧‧First bungee area

30‧‧‧Second MOS components

32‧‧‧Second gate structure

34‧‧‧Second source area

36‧‧‧Second bungee area

40‧‧‧First doped area

50‧‧‧pick up area

52‧‧‧Isolation structure

60‧‧‧Second doped area

70‧‧‧ Third MOS component

74‧‧‧ Third source region

80‧‧‧fourth oxynitride component

100a, 100b‧‧‧ Electrostatic discharge protection structure

110, 210‧‧‧ MOS components

220, 230‧‧ ‧ gate structure

212‧‧‧ source area

114, 114a, 114b, 214, 214a, 214b‧‧‧ bungee area

140, 140a, 140b, 240, 240a, 240b‧‧‧ doped areas

A ₁ , A ₂ ‧ ‧ area

P _W1 , P _W2 ‧‧‧Width

P _L1 , P _L2 ‧‧‧ length

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partial plan view showing an electrostatic discharge protection structure according to an embodiment of the present invention.

2 is a partial cross-sectional view showing an electrostatic discharge protection structure according to an embodiment of the present invention.

Fig. 3 is a partial plan view showing an electrostatic discharge protection structure according to another embodiment of the present invention.

4 is a partial cross-sectional view showing an electrostatic discharge protection structure according to another embodiment of the present invention.

Fig. 5 is a plan view showing an electrostatic discharge protection structure according to still another embodiment of the present invention.

An electrostatic discharge protection structure according to an embodiment of the present invention includes a plurality of MOS devices. Below the bungee region of each MOS device, set and The doping region of the draining region is different in conductivity, so as to improve the soundness of the electrostatic discharge protection structure. Furthermore, the area/doping concentration of the doped region below the drain region near the pick up region is greater than the area/doping concentration of the doped region below the drain region away from the contact region, so that The breakdown voltage of each parasitic BJT is approximately the same, and the parasitic BJT conduction time is almost the same.

1 is a partial plan view of an electrostatic discharge protection structure of an embodiment of the present invention. 2 is a partial cross-sectional view showing an electrostatic discharge protection structure of an embodiment of the present invention.

Referring first to FIGS. 1 and 2, an electrostatic discharge protection structure 100a according to an embodiment of the present invention includes a substrate 10, a first MOS device 20, a second MOS device 30, a pick up region 50, and a first Doped region 40 and second doped region 60. The first oxy-semiconductor element 20 and the second oxy-semiconductor element 30 have a first conductivity type channel. The contact region 50, the first doping region 40 and the second doping region 60 have a second conductivity type doping. In one embodiment, the first conductivity type is an N type and the second conductivity type is a P type. In another embodiment, the first conductivity type is a P type and the second conductivity type is an N type. The doping of the P-type doping region is, for example, boron or boron trifluoride (BF ₃ ). The doping of the N-type doping region is, for example, phosphorus or arsenic. In order to clearly describe the present embodiment, the conductivity types of the respective regions are indicated by text in FIGS. 1 and 2, and the "+" sign indicates a region having a higher doping concentration. However, the invention is not limited to the type of conductivity indicated in Figures 1 and 2.

The first MOS device 20 includes a first gate structure 22, a first source region 24, and a first drain region 26. The first gate structure 22 is located on the substrate 10 between the first source region 24 and the first drain region 26. The first gate structure 22 includes a first gate guide The bulk layer and the first gate dielectric layer. The material of the first gate conductor layer may be a conductor such as a metal or doped polysilicon. The material of the first gate dielectric layer may be an insulator such as hafnium oxide or a high dielectric constant material having a dielectric constant greater than four. The first gate structure 22 may also include a spacer, the material of which may be an insulator such as hafnium oxide or tantalum nitride. The first source region 24 and the first drain region 26 have a first conductivity type, located in the substrate 10, and have a first conductivity type channel therebetween, located below the first gate structure 22.

The second MOS device 30 includes a second gate structure 32, a second source region 34, and a second drain region 36. The second gate structure 32 is located on the substrate 10 between the second source region 34 and the second drain region 36. The second gate structure 32 includes a second gate conductor layer and a second gate dielectric layer. The material of the second gate conductor layer may be a conductor such as a metal or doped polysilicon. The material of the second gate dielectric layer may be an insulator such as hafnium oxide or a high dielectric constant material having a dielectric constant greater than four. The second gate structure 32 may also include a spacer, the material of which may be an insulator such as hafnium oxide or tantalum nitride. The second source region 34 and the second drain region 36 have a first conductivity type, located in the substrate 10, having a first conductivity type channel therebetween, below the second gate structure 32.

In one embodiment, the ESD protection structure 100a further includes a third MOS device 70 and a fourth MOS device 80 between the first MOS device 20 and the second MOS device 30. The third MOS device 70 shares the first drain region 26 with the first MOS device 20. The fourth MOS device 80 shares the second drain region 36 with the second MOS device 30 and shares the third source region 74 with the third MOS semiconductor. In one embodiment, the first MOS device 20, the second MOS device 30, the third MOS device 70, and the fourth gold oxide The semiconductor element 80 may be a pin-shaped MOS device.

The contact region 50 has a second conductivity type and is located in the substrate 10. In one embodiment, the contact region 50 is annular, and the first oxy-semiconductor element 20, the second MOS device 30, the third MOS device 70, and the fourth MOS device 80 are located in the contact region 50. Within the enclosed area. The contact region 50 is separated from the first oxynitride semiconductor element 20 by an isolation structure 52. The isolation structure 52 may contain an insulating material such as hafnium oxide. The isolation structure 52 can be a partial area oxide layer (FOX) or a shallow trench isolation structure (STI). The first MOS device 20 is closer to the pick up region 50 than the second MOS device 30. That is, the first drain region 26 of the first MOS device 20 is closer to the contact region 50 than the second drain region 36 of the second MOS device 30.

The first doped region 40 has a second conductivity type located below the first drain region 26 of the first MOS device 20. The second doped region 60 has a second conductivity type located below the second drain region 36 of the second MOS device 30. In one embodiment, the first doped region 40 is in close proximity to the first drain region 26, and the second doped region 60 is in close proximity to the second drain region 36, as shown in FIG. In another embodiment, the distance between the top surface of the first doping region 40 and the bottom surface of the first drain region 26 is, for example, about 0.05 μm to 0.2 μm; the top surface and the second portion of the second doping region 60 The distance between the bottom surfaces of the drain regions 36 is, for example, about 0.05 μm to 0.2 μm. By the arrangement of the first doping region 40 and the second doping region 60, the robustness of the electrostatic discharge protection structure can be improved. The first doped region 40 has a width P _W1 , a length P _L1 , and an area A ₁ = P _W1 × P _L1 . The second doped region 60 has a width P _W2 , a length P _L2 , and an area A ₂ = P _W2 × P _L2 . The size of the area of the first doping region 40 and the second doping region 60 or the doping concentration may affect the breakdown voltage of the lateral diode. In one embodiment, the first drain region 26 is closer to the contact region 50 than the second drain region 36, and the area A _{1 of the} first doped region 40 is larger than the area A _{2 of the} second doped region 60. In another embodiment, the first drain region 26 is closer to the contact region 50 than the second drain region 36, and the doping concentration of the first doping region 40 is greater than the second doping region 60. In still another embodiment, the first drain region 26 is closer to the contact region 50 than the second drain region 36, and the area A ₁ and the doping concentration of the first doped region 40 are both larger than the second doping region 60 . Area A ₂ and doping concentration.

In general, the conduction of the parasitic BJT is based on the substrate 10 leakage current Ioff. The value of the leakage current in the substrate is substantially fixed. The conduction speed of the parasitic BJT is determined by the magnitude of the base-to-emitter voltage (Vbe) (Vbe=Ioff×Rsub). The first doped region 40 is closer to the contact region 50, and the resistance of the substrate 10 is smaller, so the Vbe voltage is smaller, and the parasitic BJT is turned on slowly. On the contrary, the second doping region 60 is farther away from the contact region 50, and the resistance of the substrate 10 is larger, so the voltage Vbe is larger, and the BJT is turned on faster. Therefore, there is a problem that the respective BJT conduction times are inconsistent.

As described above, the key to turning on the parasitic BJT is the voltage Vbe, and the voltage of the voltage Vbe is equivalent to Ioff × Rsub. According to this embodiment, Ioff discussed herein will again be substantially proportional to the area A of the doped region (i.e., Ioff ≒ k x A, k is a proportionality constant). Therefore, if the parasitic BJTs can be turned on at the same time, that is, the voltage Vbe of each parasitic BJT is substantially the same, the following relationship can be derived: Vbe≒Ioff×Rsub≒k×A×Rsub, assuming that it is far away The area of the second doping region 60 of the dot region 50 is A ₂ , and the area of the first doping region 40 close to the contact region 50 is A ₁ , since the Rsub is far away from the contact region 50, The second doped region 60 requires a small area, whereas the Rsub near the contact region 50 is small, so that a large area is required for the first doped region 40. In this way, the voltage Vbe of each parasitic BJT away from the contact region 50 and the proximity contact region 50 can be almost equal, and the purpose of making each parasitic BJT turn on almost simultaneously can be achieved.

In summary, in the embodiment, the area A ₁ , the doping concentration, or both of the first doping region 40 is changed to be larger than the area A _{2 of the} second doping region 60, the doping concentration, or both. The difference between the first doping region 40 and the second doping region 60 and the contact region 50 can be corrected, so that the breakdown voltage of the lateral parasitic diode is substantially the same, so that the conduction time of each BJT can be made almost Consistent.

A plurality of contact windows 50a, 24a are disposed on the contact region 50, the first source region 24, the first drain region 26, the second source region 34, the second drain region 36, and the third source region 74. , 26a, 34a, 36a, and 74a. The material of the contact windows 50a, 24a, 26a, 34a, 36a, and 74a may be a conductor. Further, the structures of the contact windows 50a, 24a, 26a, 34a, 36a, and 74a may include a barrier layer and a main conductive layer. The barrier layer is, for example, a composite layer of Ti and TiN, a composite layer of Ta and TaN, or any combination thereof; the main conductive layer is, for example, a tungsten layer, a copper layer or an aluminum layer. a contact region 50, a first source region 24, a first drain region 26, a second source region 34, a second drain region 36, and the contact regions 50a, 24a, 26a, 34a, 36a, and 74a thereof A metal telluride layer may be selectively disposed between the third source regions 74 to ensure low contact resistance and ohmic contact.

In other embodiments, referring to FIGS. 3 and 4, the electrostatic discharge protection structure 100b includes a plurality of MOS devices 110. Each of the MOSFETs 110 has a doped region 140 under the drain region 114. The conductivity of the doped region 140 is different from the conductivity of the drain region 114, and is from the doped region 140 away from the contact region 150 to Proximity contact The area/doping concentration of the doped region 140 of the (pick up) region 150 is gradually increased.

In one embodiment, referring to FIGS. 1 and 2, the first MOS device 20, the second MOS device 30, the third MOS device 70, and the fourth MOS semiconductor of the above electrostatic discharge protection structure 100a. Element 80 can be a parallel finger MOS. The contact region 50 surrounds the periphery of the first MOS device 20, the second MOS device 30, the third MOS device 70, and the fourth MOS device 80. Similarly, referring to FIGS. 3 and 4, the plurality of MOS devices 110 of the above-described electrostatic discharge protection structure 100b may be juxtaposed finger MOS. The contact region 150 surrounds the periphery of the MOS device 110.

In another embodiment, referring to FIG. 5, the above-described electrostatic discharge protection structure 100c includes a plurality of MOS devices 210, and these MOS devices are arranged in a checkerboard shape (WaffLe). More specifically, the plurality of MOS devices 210 of the ESD protection structure 100c include a plurality of gate structures 220 arranged in a first direction and a plurality of gate structures 230 arranged in a second direction. In an embodiment, the first direction and the second direction are perpendicular to each other. The plurality of gate structures 220 and the plurality of gate structures 230 constitute a plurality of tiles. The source region 212 and the drain region 214 are alternately arranged in the chessboard such that any source region 212 is surrounded by four drain regions 214, and any of the drain regions 214 is surrounded by four source regions 212. . The contact region 250 surrounds the periphery of the chevron-shaped MOS device 210.

The oxynitride semiconductor elements are arranged in a checkerboard shape at the chevron-like center of the MOS element 210b farthest from the contact region 250, and the MOS device 210a at the checkered edge is closest to the contact region 250, The problem of inconsistent parasitic BJT conduction time is more serious. Therefore, the doping region 240, the conductivity type and the source region 212 of the doping region 240, and the doping region 240 may be disposed under the drain region 214 according to the above embodiment. The conductivity type of the drain region 214 is different. The area/doping concentration of the doped region 240a that is closer to the contact region 250 is designed to be larger than the area/doping concentration of the doped region 240b that is further from the contact region 250. Alternatively, the area/doping concentration from the doped region 240b below the drain region 214b of the contact region 250 to the doped region 240a under the drain region 214a of the contact region 250 is designed to gradually increase, thereby modifying the blend. The difference between the miscellaneous region 240 and the contact region 250 is different, so that the breakdown voltage of each parasitic BJT is substantially the same, and the conduction time of each BJT can be made almost uniform.

In the above embodiment, the contact region surrounds the periphery of the chevron-shaped MOS device. However, the invention is not limited thereto. The contact region can also be disposed between two adjacent MOS devices or between two adjacent sets of MOS devices.

In summary, in the embodiment of the present invention, the doping region different from the conductivity type is disposed under the drain region to improve the soundness of the electrostatic discharge protection structure. In addition, by changing the area/doping concentration of the doped region under the drain region, the difference between the doped region and the contact region can be corrected, so that the breakdown voltages of the parasitic BJTs in different regions are substantially the same. The conduction time of each BJT can be made almost the same.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

20‧‧‧First MOS components

22‧‧‧First gate structure

24‧‧‧First source area

24a, 26a, 34a, 36a, 50a, 74a‧‧‧ contact windows

26‧‧‧First bungee area

30‧‧‧Second MOS components

32‧‧‧Second gate structure

34‧‧‧Second source area

36‧‧‧Second bungee area

40‧‧‧First doped area

50‧‧‧Contact area

60‧‧‧Second doped area

70‧‧‧ Third MOS component

74‧‧‧ Third source region

80‧‧‧fourth oxynitride component

100a‧‧‧Electrostatic discharge protection structure

P _W1 , P _W2 ‧‧‧Width

P _L1 , P _L2 ‧‧‧ length

Claims (12)

An electrostatic discharge protection structure comprising: a substrate; a pick up region in the substrate; a first MOS device on the substrate, including a first 具有 having a first conductivity type a second MOS device, on the substrate, including a second drain region having the first conductivity type, wherein the first drain region is closer to the contact region than the second drain region a first doped region having a second conductivity type under the first drain region; and a second doped region having the second conductivity type under the second drain region, wherein the first doped region The area of the first doped region, the doping concentration, or both are greater than the area of the second doped region, the doping concentration, or both. The electrostatic discharge protection structure according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type. The electrostatic discharge protection structure according to claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The electrostatic discharge protection structure according to claim 1, wherein the first oxynitride semiconductor element and the second oxynitride semiconductor element are juxtaposed into a finger-shaped MOS device. The electrostatic discharge protection structure of claim 1, wherein the first oxynitride semiconductor component and the second oxynitride semiconductor component are Waffle MOS devices. The electrostatic discharge protection structure of claim 1, wherein the contact region is annular, and the first MOS device and the second MOS device are located within a region surrounded by the contact region. . An electrostatic discharge protection structure comprising: a substrate; a pick up region located in the substrate; a plurality of MOS devices located on the substrate, each having a first conductivity type of a drain region; Doped regions having a second conductivity type and respectively located under the drain regions of the respective MOS devices, wherein the doped regions away from the contact regions are close to the doped regions of the contact regions The area, doping concentration, or both are gradually increasing. The electrostatic discharge protection structure according to claim 7, wherein the first conductivity type is an N type, and the second conductivity type is a P type. The electrostatic discharge protection structure according to claim 7, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The electrostatic discharge protection structure according to claim 7, wherein the MOS devices are juxtaposed into a finger-shaped MOS device. The electrostatic discharge protection structure of claim 7, wherein the MOS devices are Waffle MOS devices. The electrostatic discharge protection structure of claim 7, wherein the contact region is annular, and the MOS devices are located within a region surrounded by the contact region.