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TW201503304A - 半導體裝置及其製法 - Google Patents

半導體裝置及其製法 Download PDF

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Publication number
TW201503304A
TW201503304A TW102124670A TW102124670A TW201503304A TW 201503304 A TW201503304 A TW 201503304A TW 102124670 A TW102124670 A TW 102124670A TW 102124670 A TW102124670 A TW 102124670A TW 201503304 A TW201503304 A TW 201503304A
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Taiwan
Prior art keywords
semiconductor device
pad
metal pad
opening
substrate
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TW102124670A
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English (en)
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TWI508247B (zh
Inventor
林長甫
姚進財
莊旻錦
黃富堂
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矽品精密工業股份有限公司
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Priority to TW102124670A priority Critical patent/TWI508247B/zh
Priority to CN201310317211.3A priority patent/CN104282648B/zh
Priority to US14/258,361 priority patent/US9607963B2/en
Publication of TW201503304A publication Critical patent/TW201503304A/zh
Application granted granted Critical
Publication of TWI508247B publication Critical patent/TWI508247B/zh

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Abstract

一種半導體裝置及其製法，該半導體裝置包括：基板，係具有基板本體與形成於該基板本體上之至少一金屬墊，該金屬墊具有第一表面與形成於該第一表面之至少一開孔；半導體元件，係具有至少一銲墊；導電元件，係形成於該金屬墊與該銲墊之間及該金屬墊之開孔內；以及膠體，係形成於該基板與該半導體元件之間，以包覆該導電元件。藉此，本發明能強化該導電元件與該金屬墊間之接合力，以提升該半導體裝置之良率。

Description

半導體裝置及其製法
本發明係關於一種半導體裝置及其製法，特別是指一種可提升良率之半導體裝置及其製法。
隨著半導體技術之日新月異、電子產品朝向輕薄化、以及半導體裝置追求高良率之趨勢下，半導體裝置之尺寸與體積亦隨之不斷縮小，但良率則需隨之不斷提高，俾使該半導體裝置達到輕薄短小及高良率之目的。
第1A圖係繪示習知技術之半導體裝置之剖視示意圖，第1B圖係依據第1A圖之線段AA繪示習知技術之半導體裝置之俯視示意圖。如圖所示，半導體裝置1係包括基板11、晶片12、凸塊13、銲料14以及膠體15。
該基板11係具有基板本體111與依序形成於基板本體111上之銅墊112及拒銲層113。該晶片12係具有形成於其表面120上之銲墊121與介電層122、形成於該介電層122之開口125上之凸塊底下金屬層123、以及形成於該介電層122上之保護層124。
該凸塊13係形成於該凸塊底下金屬層123上，該銲料 14係形成於該凸塊13與該拒銲層113之開口114之銅墊112間。該膠體15係形成於該基板11與該晶片12之間，用以包覆該基板11、晶片12、凸塊13及銲料14。
上述半導體裝置1之缺點，在於該銅墊112與該銲料14間之接合處16的接合力不佳，使得該銅墊112與該銲料14之間容易產生分離(delam)之情形，導致該半導體裝置1之良率下降。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明提供一種半導體裝置，其包括：基板，係具有基板本體與形成於該基板本體上之至少一金屬墊，該金屬墊具有第一表面與形成於該第一表面之至少一開孔；半導體元件，係具有至少一銲墊；導電元件，係形成於該金屬墊與該銲墊之間及該金屬墊之開孔內；以及膠體，係形成於該基板與該半導體元件之間，以包覆該導電元件。
本發明亦提供一種半導體裝置之製法，其包括：提供基板與半導體元件，該基板係具有基板本體與形成於該基板本體上之至少一金屬墊，且該金屬墊具有第一表面與形成於該第一表面之至少一開孔，該半導體元件並具有至少一銲墊；形成導電元件於該金屬墊與該銲墊之間及該金屬墊之開孔內；以及填充膠體於該基板與該半導體元件之間，以包覆該導電元件。
該基板可具有形成於該基板本體及金屬墊上之拒銲層，且該拒銲層具有開口以外露出該金屬墊之開孔。
該金屬墊可具有相對於該第一表面之第二表面，該開孔係貫穿該金屬墊之第一表面與第二表面以外露出該基板本體，使該導電元件形成於該開孔之側壁及所外露之基板本體上。該金屬墊可為銅墊。
該半導體元件與該基板係分別具有至少二銲墊及一金屬墊，且該金屬墊具有對應該二銲墊之開孔，該二銲墊藉由該導電元件共同連接至該金屬墊之開孔。或者，該半導體元件與該基板係分別具有二銲墊及二金屬墊，且該金屬墊具有對應該二銲墊之開孔，該二銲墊藉由該導電元件分別連接至該二金屬墊之開孔。
該開孔之形狀可為矩形、圓形、θ字形或Y字形。
該導電元件可具有導電體與銲料，該導電體形成於該銲墊上，該銲料形成於該導電體與該金屬墊之間及該金屬墊之開孔內。該導電體可為凸塊或銅柱。
由上可知，本發明之半導體裝置及其製法，主要係在半導體元件上形成至少一銲墊，並在基板之金屬墊中形成至少一開孔以外露出其側壁及基板本體，且藉由導電元件連接該銲墊與該金屬墊，使部分該導電元件形成於該開孔內以接觸該側壁及該基板本體。
藉此，本發明能增加該導電元件在該金屬墊及該基板本體上之接觸面積，以強化該導電元件與該金屬墊間之接合力而避免產生分離之情形，同時降低該半導體裝置之高 度及體積，並減少該膠體之使用量，進而提升該半導體裝置之良率，俾使該半導體裝置具備高良率、輕薄化及成本下降之效益。
1、2、2'‧‧‧半導體裝置
11、21‧‧‧基板
111、211‧‧‧基板本體
112‧‧‧銅墊
113、213‧‧‧拒銲層
114、125、216、225‧‧‧開口
12‧‧‧晶片
120、220‧‧‧表面
121、221‧‧‧銲墊
122、222‧‧‧介電層
123、223‧‧‧凸塊底下金屬層
124、224‧‧‧保護層
13‧‧‧凸塊
14、232‧‧‧銲料
15、24‧‧‧膠體
16‧‧‧接合處
212‧‧‧金屬墊
212a‧‧‧第一表面
212b‧‧‧第二表面
214‧‧‧開孔
215‧‧‧側壁
217‧‧‧底部
22‧‧‧半導體元件
23‧‧‧導電元件
231‧‧‧導電體
第1A圖係繪示習知技術之半導體裝置之剖視示意圖；第1B圖係依據第1A圖之線段AA繪示習知技術之半導體裝置之俯視示意圖；第2A圖至第2C圖係繪示本發明之半導體裝置及其製法之第一實施例之剖視示意圖，其中，第2A'圖為第2A圖之俯視示意圖；第3A圖至第3C圖係繪示本發明之半導體裝置及其製法之第二實施例之剖視示意圖，其中，第3A'圖為第3A圖之俯視示意圖；以及第4A圖與4B圖係繪示本發明之基板中金屬墊之不同開口形狀之俯視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功 效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。
同時，本說明書中所引用之如「上」、「一」、「第一」、「第二」及「表面」等用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A圖至第2C圖係繪示本發明之半導體裝置及其製法之第一實施例之剖視示意圖，其中，第2A'圖為第2A圖之俯視示意圖。
如第2A圖與第2A'圖所示，先提供一基板21，其具有基板本體211與形成於該基板本體211上之至少一金屬墊212，該金屬墊212係具有相對之第一表面212a與第二表面212b、以及形成於該第一表面212a之至少一開孔214。
該金屬墊212係具有開孔214，開孔214之形狀可為雙矩形。但在其他實施例中，該開孔214之形狀可為單矩形、圓形、θ字形、Y字形或各種不同的形狀。該金屬墊212可為銅墊。
該基板21可具有形成於該基板本體211及金屬墊212上之拒銲層213，且該拒銲層213具有開口216以外露出該金屬墊212之開孔214。
該開孔214可貫穿該金屬墊212之第一表面212a與第二表面212b，以外露出該基板本體211及該金屬墊212之側壁215。但在其他實施例中，該開孔214亦可不貫穿該 金屬墊212之第二表面212b而未外露出該基板本體211。
如第2B圖所示，提供一半導體元件22，其一表面220上形成有至少一銲墊221。該半導體元件22可為半導體晶片或半導體封裝件。
接著，形成導電元件23於該半導體元件22之銲墊221上，並將該導電元件23對應至該金屬墊212之開孔214。
該半導體元件22之表面220上亦可形成有介電層222、凸塊底下金屬層223及保護層224。該介電層222係形成於該表面220及該銲墊221上，並具有開口225以外露出部分該銲墊221，該凸塊底下金屬層223係形成於該介電層222之開口225所外露之銲墊221上，該保護層224係形成於該介電層222上。
如第2C圖所示，將該導電元件23接置於該拒銲層213所外露之第一表面212a上及該金屬墊212之開孔214處，再通過迴銲(reflow)製程，使該導電元件23流入該金屬墊212之開孔214內。藉此，該導電元件23可形成於該銲墊221(或該凸塊底下金屬層223)與該金屬墊212之第一表面212a之間、該開孔214內及其側壁215上、該開孔214所外露之基板本體211上。
最後，填充膠體24於該基板21之拒銲層213與該半導體元件22之保護層224之間，以包覆該導電元件23。
上述之半導體元件22與基板21可分別具有二銲墊221及一金屬墊212，該二銲墊221藉由二導電元件23共同連接該金屬墊212。但在其他實施例中，該半導體元件22與 該基板21可分別具有二銲墊221及二金屬墊212，該二銲墊221藉由二導電元件23分別連接該二金屬墊212。
該導電元件23可具有導電體231與銲料232，該導電體231可形成於該銲墊221或該凸塊底下金屬層223上，該銲料232可形成於該導電體231與該金屬墊212之第一表面212a之間、該金屬墊212之開孔214內及其側壁215上、該開孔214所外露之基板本體211上。該導電體231可為凸塊或銅柱等。
本發明另提供一種半導體裝置，如第2C圖所示。該半導體裝置2係包括基板21、半導體元件22、導電元件23以及膠體24。
該基板21係具有基板本體211與形成於該基板本體211上之至少一金屬墊212，該金屬墊212係具有相對之第一表面212a與第二表面212b、以及形成於該第一表面212a之至少一開孔214。該開孔214可貫穿該金屬墊212之第一表面212a與第二表面212b，以外露出該基板本體211及該金屬墊212之側壁215。該金屬墊212可為銅墊。
該基板21可具有拒銲層213，且該拒銲層213具有開口216以外露出該金屬墊212之開孔214。該開孔214之形狀可為單矩形、雙矩形、圓形、θ字形、Y字形或各種不同的形狀。
該半導體元件22之表面220上係形成有至少一銲墊221，該表面220上亦可形成有介電層222、凸塊底下金屬層223及保護層224。該介電層222係形成於該表面220 及該銲墊221上，並具有開口225以外露出部分該銲墊221，該凸塊底下金屬層223係形成於該介電層222之開口225所外露之銲墊221上，該保護層224係形成於該介電層222上。該半導體元件22可為半導體晶片或半導體封裝件。
該半導體元件22與該基板21可分別具有二銲墊221及一金屬墊212，該二銲墊221藉由二導電元件23共同連接該金屬墊212。但在其他實施例中，該半導體元件22與該基板21可分別具有二銲墊221及二金屬墊212，該二銲墊221藉由二導電元件23分別連接該二金屬墊212。
該導電元件23可形成於該銲墊221(或該凸塊底下金屬層223)與該金屬墊212之第一表面212a之間、該開孔214內及其側壁215上、該開孔214所外露之基板本體211上。
該導電元件23可具有導電體231與銲料232，該導電體231形成於該銲墊221或該凸塊底下金屬層223上，該銲料232形成於該導電體231與該金屬墊212之間及該金屬墊212之開孔214內。該導電體231可為凸塊或銅柱等。
該膠體24係形成於該基板21與該半導體元件22之間，用以包覆該基板21、半導體元件22及導電元件23。
第3A圖至第3C圖係繪示本發明之半導體裝置及其製法之第二實施例之剖視示意圖，其中，第3A'圖為第3A圖之俯視示意圖。第3A圖至第3C圖與上述第2A圖至第2C圖之半導體裝置及其製法大致相同，其主要差異如下： 在第3A圖與第3A'圖中，該基板21係具有二金屬墊212，該開孔214之形狀係為圓形。同時，該開孔214並不貫穿該金屬墊212之第二表面212b，故未外露出該基板本體211而是外露出該開孔214之底部217。
在第3B圖中，該半導體元件22係具有二銲墊221，該二銲墊221上分別形成有二導電元件23。
在第3C圖中，該二銲墊221係藉由該二導電元件23分別連接該二金屬墊212。
本發明另提供一種半導體裝置，如第3C圖所示。第3C圖之半導體裝置與上述第2C圖之半導體裝置大致相同，其主要差異如下：在第3C圖中，半導體裝置2'之基板21係具有二金屬墊212，該開孔214並不貫穿該金屬墊212之第二表面212b，故未外露出該基板本體211而是外露出該開孔214之底部217。該半導體元件22係具有二銲墊221，且該二銲墊221藉由該二導電元件23分別連接該二金屬墊212。
第4A圖與4B圖係繪示本發明之基板中金屬墊之不同開口形狀之俯視示意圖。
在第4A圖中，開口216之形狀係類似θ字形。而在第4B圖中，該開口216之形狀則類似Y字形或人字形。但在其他實施例中，該開口216亦可為各種不同的形狀。
由上可知，本發明之半導體裝置及其製法，主要係在半導體元件上形成至少一銲墊，並在基板之金屬墊中形成至少一開孔以外露出其側壁及基板本體，且藉由導電元件 連接該銲墊與該金屬墊，使部分該導電元件形成於該開孔內以接觸該側壁及該基板本體。
藉此，本發明能增加該導電元件在該金屬墊及該基板本體上之接觸面積，以強化該導電元件與該金屬墊間之接合力而避免產生分離之情形，同時降低該半導體裝置之高度及體積，並減少該膠體之使用量，進而提升該半導體裝置之良率，俾使該半導體裝置具備高良率、輕薄化及成本下降之效益。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體裝置
21‧‧‧基板
211‧‧‧基板本體
212‧‧‧金屬墊
212a‧‧‧第一表面
212b‧‧‧第二表面
213‧‧‧拒銲層
215‧‧‧側壁
216‧‧‧開口
22‧‧‧半導體元件
220‧‧‧表面
221‧‧‧銲墊
222‧‧‧介電層
223‧‧‧凸塊底下金屬層
224‧‧‧保護層
225‧‧‧開口
23‧‧‧導電元件
231‧‧‧導電體
232‧‧‧銲料
24‧‧‧膠體

Claims (18)

  1. 一種半導體裝置，其包括：基板，係具有基板本體與形成於該基板本體上之至少一金屬墊，該金屬墊具有第一表面與形成於該第一表面之至少一開孔；半導體元件，係具有至少一銲墊；導電元件，係形成於該金屬墊與該銲墊之間及該金屬墊之開孔內；以及膠體，係形成於該基板與該半導體元件之間，以包覆該導電元件。
  2. 如申請專利範圍第1項所述之半導體裝置，其中，該基板復具有形成於該基板本體及金屬墊上之拒銲層，且該拒銲層具有開口以外露出該金屬墊之開孔。
  3. 如申請專利範圍第1項所述之半導體裝置，其中，該金屬墊復具有相對於該第一表面之第二表面，該開孔係貫穿該金屬墊之第一表面與第二表面以外露出該基板本體，使該導電元件形成於該開孔之側壁及所外露之基板本體上。
  4. 如申請專利範圍第1項所述之半導體裝置，其中，該金屬墊係為銅墊。
  5. 如申請專利範圍第1項所述之半導體裝置，其中，該半導體元件與該基板係分別具有二銲墊及一金屬墊，且該金屬墊具有對應該二銲墊之開孔，該二銲墊藉由該導電元件共同連接至該金屬墊之開孔。
  6. 如申請專利範圍第1項所述之半導體裝置，其中，該半導體元件與該基板係分別具有至少二銲墊及二金屬墊，且該二金屬墊具有對應該二銲墊之開孔，該二銲墊藉由該導電元件各自連接至該二金屬墊之開孔。
  7. 如申請專利範圍第1項所述之半導體裝置，其中，該開孔之形狀係為矩形、圓形、θ字形或Y字形。
  8. 如申請專利範圍第1項所述之半導體裝置，其中，該導電元件係具有導電體與銲料，該導電體形成於該銲墊上，該銲料形成於該導電體與該金屬墊之間及該金屬墊之開孔內。
  9. 如申請專利範圍第8項所述之半導體裝置，其中，該導電體係為凸塊或銅柱。
  10. 一種半導體裝置之製法，其包括：提供基板與半導體元件，該基板係具有基板本體與形成於該基板本體上之至少一金屬墊，且該金屬墊具有第一表面與形成於該第一表面之至少一開孔，該半導體元件並具有至少一銲墊；形成導電元件於該金屬墊與該銲墊之間及該金屬墊之開孔內；以及填充膠體於該基板與該半導體元件之間，以包覆該導電元件。
  11. 如申請專利範圍第10項所述之半導體裝置之製法，其中，該基板復具有形成於該基板本體及金屬墊上之拒銲層，且該拒銲層具有開口以外露出該金屬墊之開孔。
  12. 如申請專利範圍第10項所述之半導體裝置之製法，其中，該金屬墊復具有相對於該第一表面之第二表面，該開孔係貫穿該金屬墊之第一表面與第二表面以外露出該基板本體，使該導電元件形成於該開孔之側壁及所外露之基板本體上。
  13. 如申請專利範圍第10項所述之半導體裝置之製法，其中，該金屬墊係為銅墊。
  14. 如申請專利範圍第10項所述之半導體裝置之製法，其中，該半導體元件與該基板係分別具有至少二銲墊及一金屬墊，且該金屬墊具有對應該二銲墊之開孔，該二銲墊藉由該導電元件共同連接至該金屬墊之開孔。
  15. 如申請專利範圍第10項所述之半導體裝置之製法，其中，該半導體元件與該基板係分別具有二銲墊及二金屬墊，且該金屬墊具有對應該二銲墊之開孔，該二銲墊藉由該導電元件分別連接至該二金屬墊之開孔。
  16. 如申請專利範圍第10項所述之半導體裝置之製法，其中，該開孔之形狀係為矩形、圓形、θ字形或Y字形。
  17. 如申請專利範圍第10項所述之半導體裝置之製法，其中，該導電元件係具有導電體與銲料，該導電體形成於該銲墊上，該銲料形成於該導電體與該金屬墊之間及該金屬墊之開孔內。
  18. 如申請專利範圍第17項所述之半導體裝置之製法，其中，該導電體係為凸塊或銅柱。
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