TW201444086A - Semiconductor device and fabrication method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. The substrate has a first region and a second region. A portion of the horizontal fin structure and the vertical fin structure are disposed in the first region, and the electrical contact structure directly covers the horizontal fin structure and the vertical fin structure within the first region. The gate structure partially overlaps the horizontal fin structure within the second region.

Description

Semiconductor device and method of fabricating the same

The present invention relates to the field of a semiconductor device, and more particularly to a structure in a well connection region of a semiconductor device and a method of fabricating the same.

As the size of field effect transistors (FETs) components continues to shrink, the development of conventional planar field effect transistor components has faced process limitations. In order to overcome the process limitation, the replacement of planar transistor components with non-planar field effect transistor components, such as fin field effect transistor (FinFET) components, has become a mainstream trend.

In the current generation process of sub-lithographic features, the sidewall pattern transfer (SIT) technique is generally used to form the desired fin structure. In general, sidewall pattern transfer techniques are typically implemented by forming a plurality of sacrificial patterns on a substrate. Then, a sidewall is formed on each sidewall of each sacrificial pattern by a deposition and etching process. After removing the sacrificial patterns, the pattern of the sidewalls is further transferred into the substrate by using the sidewall mask as an etch mask of the substrate to form a plurality of fin structures arranged in a flat shape, thereby defining a transistor. The shape and width of the component carrier channel. However, the smaller surface area of the fin structure also limits the contact area between it and the electrical contact structure, and in particular limits the contact area between the fin structure and the electrical contact structure located in the well connection region. Since the resistance value is inversely proportional to the contact area, this structure causes a significant voltage to be generated in the interface between the fin structure/electrical contact structure in the well connection region. Drop, not conducive to the electrical performance of the transistor components.

Therefore, there is still a need for an improved semiconductor device structure and method of fabricating the same to overcome the problem of excessive contact resistance in the well connection region.

In order to achieve the above object, the present invention provides a structure of a semiconductor device and a method of fabricating the same to improve the deficiencies in the prior art.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a first fin structure, an electrical contact structure, and a gate structure, wherein the first fin structure includes a horizontal fin structure extending along the first direction, and a vertical fin structure extending along the second direction . A first region and a second region are defined on the substrate, and a partial segment of the horizontal fin structure and a vertical fin structure are disposed in the first region. The electrical contact structure directly covers the horizontal fin structure and the vertical fin structure in the first region, and the gate structure portion partially overlaps the horizontal fin structure in the second region.

According to another embodiment of the present invention, a method of fabricating a semiconductor device is provided, comprising the steps of: first forming a sacrificial pattern on a substrate, and forming sidewalls on sidewalls of the sacrificial pattern. The pattern of the sidewalls is then transferred to the substrate to form a fin structure, wherein the fin structure includes a horizontal fin structure extending along the first direction and a vertical fin structure extending along the second direction. Then, a gate structure, a source/drain structure and an electrical contact structure are formed in sequence, wherein the gate structure overlaps with a part of the horizontal fin structure, and the source/drain structures are respectively located on each side of the gate structure, and electrical contact The structure directly covers the horizontal fin structure as well as the vertical fin structure.

10‧‧‧Substrate

12‧‧‧Dielectric layer

14‧‧‧sacrificial pattern

16‧‧‧ Sidewall

18‧‧‧ patterned dielectric layer

20‧‧‧Outstanding structure

22‧‧‧Shallow trench insulation

24‧‧‧Fin structure

24a‧‧‧First fin structure

24b‧‧‧second fin structure

24c‧‧‧ Third fin structure

24d‧‧‧Four fin structure

26a‧‧‧Horizontal fin structure

26b‧‧‧Vertical fin structure

28‧‧‧ Well doped area

30‧‧‧ well connected doping area

32‧‧‧ gate structure

34‧‧‧ source/deuterium doped region

38‧‧‧Interlayer dielectric layer

40‧‧‧Contact hole

42‧‧‧Electrical contact structure

60‧‧‧shading structure

62‧‧‧Dielectric layer

64‧‧‧ Conductive layer

66‧‧‧Upper cover

68‧‧‧ Sidewall

80a‧‧‧ side

80b‧‧‧ side

80c‧‧‧ top

100‧‧‧First layout pattern

D1‧‧‧first depth

H1‧‧‧ first height

R1‧‧‧ well connection zone

R2‧‧‧ active area

W1‧‧‧ first width

W2‧‧‧ second width

X‧‧‧ first direction

Y‧‧‧second direction

A-A’‧‧‧ cut line

B-B’‧‧‧ cut line

C-C’‧‧‧ cut line

1 to 7 are schematic views showing a manufacturing method of a semiconductor device according to a first preferred embodiment of the present invention, wherein: FIG. 1 is a top plan view showing a structure of a first preferred embodiment of the present invention; 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1; FIG. 3 is a cross-sectional view showing a pattern transfer process and forming a shallow trench insulation; FIG. 4 is a schematic view showing the formation of a gate A schematic plan view of the rear view of the pole structure; FIG. 5 is a schematic cross-sectional view taken along line A-A' of FIG. 4; FIG. 6 is a schematic plan view of the electrical contact structure; and FIG. A cross-sectional view taken along line B-B' in Fig. 6.

FIG. 8 is a top plan view showing a first variation of the first preferred embodiment of the present invention.

Fig. 9 is a schematic cross-sectional view taken along line C-C' in Fig. 8.

Figure 10 is a top plan view showing a second variation of the first preferred embodiment of the present invention.

Figure 11 is a top plan view showing a third variation of the first preferred embodiment of the present invention.

In the following, specific embodiments of the semiconductor device of the present invention and a method of fabricating the same are set forth to enable those skilled in the art to practice the invention. The specific embodiments may be referred to the corresponding drawings, such that the drawings form part of the embodiments. Although the embodiments of the present invention are disclosed as follows, they are not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention.

First, as shown in Fig. 1 and Fig. 2, Fig. 1 is a plan view showing the structure at the beginning of the process, and Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1. At this stage, a substrate 10 is provided, on which a dielectric layer 12 and a plurality of sacrificial patterns 14 are disposed, and the sidewalls of each of the sacrificial patterns 14 are covered by a side wall 16 which is looped in appearance. . Wherein the substrate 10 defines a first region and a second region, which may respectively correspond to the well connection region of the semiconductor device R1 and active area R2, but are not limited thereto. Each sacrificial pattern 14 may span the well connection region R1 and the active region R2 such that its top view appearance has a first layout pattern 100, such as a matrix layout arranged along the first direction X and the second direction Y, and each The long axis of the sacrificial pattern 14 is parallel to the first direction X, but is not limited thereto. Preferably, each of the sacrificial patterns 14 has a first width W1, and each of the side walls 16 has a second width W2, and the first width W1 is greater than the second width W2.

The substrate 10 is preferably a semiconductor substrate such as a germanium substrate or a germanium (SiGe) substrate, and the substrate 10 preferably does not use a silicon-on-insulator (SOI) substrate. The dielectric layer 12 can be a nitride layer or an oxide layer, such as tantalum nitride, hafnium oxide or other suitable dielectric layer, which can utilize thermal oxidation, high density plasma CVD (HDPCVD). ) or sub-atmosphere CVD (SACVD) and other processes. And according to other embodiments, the dielectric layer can be selectively formed on the substrate. The composition of the sacrificial pattern 14 can be a semiconductor material, such as a polysilicon material, which can be formed by conventional deposition, photolithography, and etching processes. Moreover, limited by the process capability of the machine, the first width W1 of each sacrificial pattern 14 is greater than or equal to the minimum exposure limit of the optical lithography process that can be performed by the machine. The composition of each of the sidewalls 16 may be a dielectric material, such as tantalum nitride, which may be formed in the following steps: First, a dielectric material layer (not shown) is formed to laterally coat the sacrificial patterns 14 And covering the dielectric layer 12. Next, the dielectric material layer is etched comprehensively (without masking) to form sidewall spacers 16 on the sidewalls of each sacrificial pattern 14 to form a top view as shown in FIG. Preferably, the composition of the dielectric layer 12, the sacrificial pattern 14 and the sidewall spacers 16 will be different from one another such that there will be a certain etch selectivity ratio between each other.

Referring to Fig. 3, Fig. 3 is a schematic cross-sectional view showing the pattern transfer process and forming shallow trench isolation, which substantially corresponds to the line A-A' in Fig. 1. As shown in FIGS. 2 and 3, the sacrificial pattern 14 in the well connection region R1 and the active region R2 is completely removed, leaving only the sidewall spacer 16 above the dielectric layer 12. Then perform a pattern transfer process, such as sidewall pattern transfer A (sidewall image transfer, SIT) process is performed to transfer a ring pattern defined by each of the side walls 16 to the surface of the substrate 10 to form a plurality of protruding structures 20 having an annular pattern. Each of the protruding structures 20 has a first height H1, and the patterned dielectric layer 18 and the sidewalls 16 are sequentially stacked thereon.

Specifically, the pattern transfer process described above may include a plurality of etching steps, for example, first, the sacrificial pattern 14 is removed by a general etching process (dry etching or wet etching), leaving only the sidewalls 16 on the dielectric layer 12 on. Under the general etching process conditions, the etching rate of the sacrificial pattern 14 is greater than the etching rate of the sidewalls 16, so that the etching process hardly etches the sidewalls 16. Next, one or more anisotropic etching processes are performed, and the dielectric layer 12 and/or a portion of the substrate 10 are sequentially etched downward with the sidewalls 16 as an etch mask. To this end, the pattern defined by the sidewalls 16 can be transferred into the dielectric layer 12 and/or the substrate 10. It should be noted that the "pattern transfer process" referred to in the full text includes the concept of "sidewall pattern transfer process", that is, the "pattern transfer process" can be regarded as the "sidewall pattern transfer process". .

Still as shown in Figure 3, and with reference to Figure 2. After the pattern transfer process is completed, the dielectric layer deposition process, the dielectric layer planarization process, and the dielectric layer etch process may be sequentially performed to form a first depth D1 around the bottom of each protruding structure 20. Shallow trench insulation layer 22. Therefore, a portion of each of the protruding structures 20 may protrude from the shallow trench insulating layer 22. This portion of the segment that protrudes from the shallow trench insulating layer 22 may also be referred to as a fin structure 24, and the height of the fin structure 24 is approximately 300 to 400 angstroms. It should be noted that in the above pattern transfer process, the width of each sidewall 16 may be slightly etched and reduced. Therefore, the width of each corresponding fin structure 24 may be slightly smaller than that of the original sidewalls 16 The second width W2 is, but not limited to.

Referring to Figures 4 and 5, wherein FIG. 4 is a schematic plan view showing the formation of the gate structure, and FIG. 5 is a schematic cross-sectional view taken along line A-A' of FIG. As shown in Figure 4 and Figure 5 is shown in conjunction with Figure 3. Then, the sidewalls 16 above the fin structure 24 and the patterned dielectric layers 18 are completely removed to expose the fin structures 24, for example, exposing the first fin structures 24a, the second fin structures 24b, and the third. The fin structure 24c and the fourth fin structure 24d are not limited thereto. Preferably, each fin structure 24a, 24b, 24c, 24d can span the well connection region R1 and the active region R2, and its U-shaped end is located in the well connection region R1. In other words, the ends of each of the fin structures 24a, 24b, 24c, 24d will have two horizontal fin structures 26a and one vertical fin structure 26b.

Other related semiconductor processes can then be performed. For example, a plurality of ion implantation processes are sequentially performed to form a well doped region 28 having a first conductivity type, such as a P type, and a well pick-up doped region in the substrate 10. Region)30. Wherein, the well doping region 28 is formed in the well connection region R1 and the active region R2, and the well connection doping region 30 is only formed in the well connection region R1. Further, the well connection doped region 30 can be considered to be a heavily doped region disposed within the well doped region 28. In other words, the doping concentration of well connection doped region 30 will be higher than the doping concentration of well doped region 28. In addition, the ion implantation process of the doping well can also be performed before the formation of each fin structure 24, and the timing points thereof are not limited. Next, at least one gate structure 32 is formed in each active region R2 such that each gate structure 32 can be in direct contact with a plurality of fin structures 24 arranged in parallel at the same time, but the invention is not limited thereto. According to other embodiments, a plurality of gate structures arranged in parallel may be simultaneously disposed in each active region. Preferably, the arrangement of the gate structures 32 will be as shown in FIG. Each of the gate structures 32 covers a portion of each of the fin structures 24, and at least includes a gate dielectric layer (not shown) and a gate conductive layer (not shown) from bottom to top. And an upper cap layer (not shown), and the sidewalls of each of the gate structures 32 are covered by the gate sidewalls (not shown). The material of the gate dielectric layer, the gate conductive layer, and the upper cap layer may correspond to yttrium oxide, polysilicon/metal material, and tantalum nitride, respectively, but is not limited thereto.

Still as shown in Figure 4. Then, a coating and photolithography process can be performed to substrate 10 Forming a patterned mask layer (not shown), such as a photoresist layer, only exposes the structures in each active region R2, such as exposing the shallow trench insulating layer 22 in the active region R2, and each fin structure 24 And each gate structure 32. An ion implantation process is performed under the coverage of the patterned mask layer, the gate structure 32, and the gate sidewalls to form a source/汲 in each of the fin structures 24 on both sides of each gate structure 32. Very doped region 34. Each source/drain doping region 34 can be considered as a heavily doped region disposed within the well doped region 28, and the conductivity type of each source/drain doping region 34 is different from the well doped region. 28 and the well connected conductivity type of the doped region 30. In other words, each source/drain doping region 34 of the present embodiment will have a second conductivity type, such as an N-type. Finally, the patterned mask layer is removed.

It should be noted here that, according to the above embodiment, each fin structure 24a, 24b, 24c, 24d will span the well connection region R1 and the active region R2. However, according to other embodiments, the sections of each fin structure located in the connection zone and the active zone may also be removed before or after the formation of the shallow trench insulation layer, such that the connection zone and the active zone do not have a fin structure.

Referring to Fig. 6 and Fig. 7, Fig. 7 is a schematic cross-sectional view taken along line B-B' in Fig. 6. As shown in FIGS. 6 and 7, after the patterned mask layer is removed, a deposition process can be performed to form an interlevel dielectric layer 38 on the substrate 10. A planarization process is then performed on the interlayer dielectric layer 38 such that the interlayer dielectric layer 38 completely covers the fin structures 24 and the gate structures 32. Next, an etching process is performed to form a plurality of contact holes 40 in the interlayer dielectric layer 38, and expose corresponding portions of the fin structures 34 to the bottom of the contact holes 40. In subsequent processes, the fin structures 34 exposed to the contact holes 40 can serve as contact areas for power supply connections to external circuitry.

It should be noted here that since the present embodiment discloses a gate first process, the conductive material in the gate structure 32 is not replaced after the interlayer dielectric layer 38 is formed, but is not limited thereto. The invention can also be applied to a gate last process, or a replacement metal gate A replacement metal gate (RMG) process to displace conductive material within the gate structure. For example, after forming the interlayer dielectric layer, the interlayer dielectric layer can be continuously polished until the top of the gate structure is exposed, such as exposing the cap layer. Then at least a removal process and a metal deposition process are performed to remove the original gate conductive layer in the gate structure, such as polysilicon, and replace it with a metal material having better conductivity, such as aluminum, tungsten or copper, to complete After that, the gate process.

Still as shown in Figure 6 and Figure 7. After a plurality of contact holes 40 are formed in the interlayer dielectric layer 38, an electrical contact structure 42 such as a strip contact structure may be formed in each of the contact holes 40 to directly contact and cover a portion of each of the fin structures 24. segment. One feature of the present invention is that each electrical contact structure 42 located within the well connection region R1 covers the horizontal fin structure 26a of each fin structure 24, and also covers the vertical fin structure of each fin structure 24. 26b, that is, each of the electrical contact structures 42 located within the well connection region R1 directly covers the U-shaped ends of the fin structures 24a, 24b, 24c, 24d. Specifically, each of the electrical contact structures 42 located in the well connection region R1 may directly contact the two side faces 80a, 80b and the top face 80c of the horizontal fin structure 26a and the vertical fin structure 26b, respectively, thereby increasing the overall Contact area and reduced contact resistance. Under such a structure, if a voltage is applied to the well connection region R1, only a small voltage drop is generated between the electrical contact structure 42 and the horizontal/vertical fin structures 26a, 26b, so that the voltage can be smoothly connected to the doped region via the well. 30 is applied to the well doped region 28. It should be noted that the electrical contact structure 42 may include a barrier layer and/or an adhesive layer, such as titanium nitride or tantalum nitride, and a conductive layer, such as aluminum, tungsten or copper, from bottom to top. Materials, but are not limited to this.

The present invention may include variations of other semiconductor device configurations in addition to the first preferred embodiment described above. The structure and process steps of these variations are generally similar to the first preferred embodiment described above, and only the main differences will be described below, and similar components and structures may be referred to.

As shown in FIG. 8 and FIG. 9, FIG. 8 illustrates a first preferred embodiment of the present invention. A schematic top view of a variation, and Fig. 9 is a schematic cross-sectional view taken along line C-C' of Fig. 8. The first variation of the structure shown in FIG. 8 corresponds to the structure of the first preferred embodiment shown in FIG. 6. The main difference between the two is that the semiconductor device of the first variation further includes a plurality of shielding structures 60. It can be used to prevent the epitaxial layer from growing in a specific region of the fin structure 24. Wherein, a shielding structure 60 is disposed between the two electrical contact structures 42 in the well connection region R1, and the two shielding structures 60 are each directly in contact with the plurality of fin structures 24 in the well connection region R1, especially in direct contact. The horizontal fin structures 26a are, but are not limited to. Therefore, each of the electrical contact structures 42 located in the well connection region R1 can cover and directly contact the corresponding shielding structures 60, but is not limited thereto. According to other embodiments, the shielding structure may also be disposed between the well connection region and the electrical contact structure of the active region, and thus separated from the electrical contact structure. Therefore, even if the shielding structure 60 is provided, the semiconductor device of the first variation type has a vertical fin structure 26b due to the well connection region R1, which reduces the contact resistance and reduces the size of the well connection region R1, thereby improving the semiconductor. The degree of integration of the device.

Specifically, the structure and the formation time of the first variation type shielding structure 60 are substantially the same as the structure and the formation time of the gate structure 32 in the active region R2. For example, when the gate structure of the semiconductor device is completed through the front gate process, each of the shielding structures 60 also covers a portion of each of the fin structures 24, and at least a dielectric is included from bottom to top. The layer 62, a conductive layer 64 and an upper cap layer 66, and the sidewalls of each of the shielding structures 60 are also covered by the sidewalls 68. The materials of the dielectric layer, the conductive layer, and the upper cap layer may respectively correspond to the gate dielectric layer, the gate conductive layer, and the upper cap layer described in the first preferred embodiment, but are not limited thereto. However, the present invention is not limited thereto, and it is also possible to prepare a gate structure and/or a shielding structure by using a back gate process.

In addition to the first variation described above, the present invention also includes a second variation of the first preferred embodiment. As shown in Fig. 10, Fig. 10 is a top plan view showing a second modification of the first preferred embodiment of the present invention. The second variation of the structure and process steps is substantially similar to the structure and process steps of the first preferred embodiment, the main difference between the two being that the variant is located in the third active region R2. The fin structure 24c has only two horizontal fin structures 26a arranged in parallel without the vertical fin structure 26b. The remaining first, second and fourth fin structures 24a, 24b, 24d still have two horizontal fin structures 26a and a vertical fin structure 26b arranged in parallel. Therefore, the electrical contact structure 42 located to the right of the well connection region R1 will only directly cover the two horizontally arranged horizontal fin structures 26a of the third fin structure 24c. The structure or process of the present variation embodiment is substantially similar to the first preferred embodiment and the above-described variations of FIGS. 1 through 9 except that the third fin structure 24c does not have the vertical fin structure 26b. The structure or process of the description will not be repeated here.

In addition to the first and second variations described above, the present invention further includes a third variation of the first preferred embodiment. As shown in Fig. 11, Fig. 11 is a top plan view showing a third modification of the first preferred embodiment of the present invention. The third variation of the structure and process steps is substantially similar to the structure and process steps of the first preferred embodiment. The main difference between the two is that the same electrical contact structure 42 in the well connection region R1 is directly covered at the same time. Vertical fin structures 26b of the first to fourth fin structures 24a, 24b, 24c, 24d. The structure or process of the present variation embodiment is substantially similar to the first preferred embodiment and the above variations, except that the electrical contact structure 42 covers the vertical fin structures 26b of the first to fourth fin structures 24 at the same time. The structure or process shown in Figures 1 to 9 will not be described here.

It should be noted here that the above variations can also be combined with each other according to the process requirements. For example, in the case where the well connection region is provided with the shielding structure, only one electrical contact structure is disposed in the well connection region to simultaneously contact the vertical fin structures of the first to fourth fin structures, but is not limited thereto. .

For the sake of brevity, the horizontal and vertical fin structures 26a, 26b of the above embodiments are used as contact areas for the well connection region R1. However, the horizontal and vertical fin structures 26a, 26b of the present invention are not only applicable to the well joint zone R1, but can be equally applied to other suitable zones. Example In summary, the horizontal and vertical fin structures of the present invention can be applied to the source/drain regions of the transistor element, or to a resistor, a diode element, a photosensitive device, or a bipolar transistor. In a suitable region of a semiconductor element such as a bipolar junction transistor (BJT).

In summary, according to an embodiment of the present invention, both the horizontal fin structure and the vertical fin structure are disposed in the well connection region of the semiconductor device. Therefore, in addition to covering the horizontal fin structure, the electrical contact structure located in the well connection region also covers the vertical fin structure, and has a large contact area and a low contact resistance. Under such a structure, if a voltage is applied to the well connection region, only a small voltage drop is generated between the electrical contact structure and the horizontal/vertical fin structure, so that the voltage can be smoothly applied to the well doping through the well connection doping region. The area, in turn, enhances the performance of the semiconductor device.

22‧‧‧Shallow trench insulation

24‧‧‧Fin structure

24a‧‧‧First fin structure

24b‧‧‧second fin structure

24c‧‧‧ Third fin structure

24d‧‧‧Four fin structure

26a‧‧‧Horizontal fin structure

26b‧‧‧Vertical fin structure

28‧‧‧ Well doped area

30‧‧‧ well connected doping area

32‧‧‧ gate structure

42‧‧‧Electrical contact structure

100‧‧‧First layout pattern

R1‧‧‧ well connection zone

R2‧‧‧ active area

X‧‧‧ first direction

Y‧‧‧second direction

B-B’‧‧‧ cut line

Claims (20)

A semiconductor device includes: a substrate defining a first region and a second region; a first fin structure disposed on the substrate, the first fin structure including at least one extending along a first direction a horizontal fin structure, and a vertical fin structure extending along a second direction, wherein a portion of the horizontal fin structure and the vertical fin structure are disposed in the first region; an electrical contact a structure directly covering the at least one horizontal fin structure and the vertical fin structure in the first region; and a gate structure disposed on the substrate, the gate structure partially overlapping the second region At least one horizontal fin structure. The semiconductor device of claim 1, wherein the first direction is perpendicular to the second direction. The semiconductor device of claim 1, wherein the first fin structure is a loop structure. The semiconductor device of claim 1, wherein the first fin structure is an annular structure having an opening. The semiconductor device of claim 1, wherein the first fin structure comprises another horizontal fin structure extending along the first direction, wherein the electrical contact structure directly contacts the plurality of regions in the first region A horizontal fin structure and the vertical fin structure. The semiconductor device of claim 1, wherein the horizontal fin structure and the vertical fin structure each have opposite side faces, and the electrical contact structure directly contacts the sides. The semiconductor device of claim 1, wherein the first region is a well pick-up region, and the second region is an active region. The semiconductor device of claim 7, further comprising a well connection doping region having a first conductivity type disposed in the well connection region. The semiconductor device of claim 7, further comprising a source/drain doped region having a second conductivity type disposed in the active region. The semiconductor device of claim 9, wherein the source/drain doping region is disposed within the horizontal fin structure and on one side of the gate structure. The semiconductor device of claim 1, further comprising a well connection doping region and a source/drain doping region respectively disposed in the first region and in the second region, wherein the well is coupled The impurity region has a first conductivity type, the source/drain doped region has a second conductivity type, and the first conductivity type is different from the second conductivity type. The semiconductor device of claim 1, further comprising a shielding structure covering a portion of the horizontal fin structure, wherein the electrical contact structure covers a portion of the shielding structure. The semiconductor device of claim 1, further comprising: a second fin structure disposed on the substrate, the second fin structure including at least one horizontal fin structure extending along the first direction, And a vertical fin structure extending along the second direction, wherein the partial segments of the horizontal fin structures and the vertical fin structures are disposed in the first region. The semiconductor device of claim 13, wherein the first direction is perpendicular to the second direction. The semiconductor device of claim 13, wherein the electrical contact structure directly contacts the horizontal fin structures and the vertical fin structures. The semiconductor device of claim 13, wherein the horizontal fin structure and the vertical fin structure each have opposite side faces, and the electrical contact structure directly contacts the sides. The semiconductor device of claim 16, further comprising a well connection doping region and a source/drain doping region respectively disposed in the first region and in the second region, wherein the source/汲The pole doped region is disposed in at least one of the horizontal fin structures and on one side of the gate structure. The semiconductor device of claim 17, wherein the well connection doped region has a first conductivity type, the source/drain doped region has a second conductivity type, and the first conductivity type is different from The second conductivity type. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a sacrificial pattern on the substrate; forming a sidewall on a sidewall of the sacrificial pattern; removing the sacrificial pattern; transferring the pattern of the sidewall to the substrate; Forming a fin structure, wherein the fin structure includes at least one horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction; forming a gate structure, and a portion The horizontal fin structures overlap; forming two source/drain doped regions, each located on each side of the gate structure; An electrical contact structure is formed to directly cover the at least one horizontal fin structure and the vertical fin structure. The method of fabricating a semiconductor device according to claim 19, wherein the vertical fin structure is still present before the electrical contact structure is formed.