TW201401481A - Slope die stack - Google Patents

Abstract

A semiconductor device comprises a substrate and at least two groups of semiconductor dies stacked above the substrate. Each group of semiconductor dies includes at least a bottom and a top semiconductor die. Each semiconductor die comprises at least one bonding pad aligned along a first edge of the semiconductor die. The at least two groups of semiconductor dies comprise an underlying group of semiconductor dies and an overlying group of semiconductor dies. The bottom semiconductor die of the underlying group is disposed on the substrate while the bottom semiconductor die of the overlying group is disposed directly on the top semiconductor die of the underlying group. Within each group, the first edge of the top semiconductor die is offset from the first edge of the bottom semiconductor die by a group offset length in a first direction. The first edge of the bottom semiconductor die of the overlying group is shifted from the first edge of the bottom semiconductor die of the underlying group by a shift length Lshift in the first direction. The group offset length Lgoffset of the underlying group is greater than or equal to the shift length Lshift of the overlying group.

Description

Ramp grain stacking

The present technology is related to semiconductor devices.

Consumer demand for compact products with increased functionality continues to drive the semiconductor industry to provide high density packaging of semiconductor devices. This high density packaging of semiconductor devices can be achieved by stacking a plurality of semiconductor dies on a common substrate, performing wire bonding, and encapsulating them in a single package with a molding compound. Stacked die packages can have a variety of configurations. 1 and 2 are schematic side views showing two simplified structures of such semiconductor devices having a stacked die configuration. In Figs. 1 and 2, the wire bonding structure and the molding compound are not shown for the sake of clarity.

As shown in FIG. 1 , a semiconductor device 100 includes a substrate 110 and four semiconductor dies 120 to 150 stacked on the substrate 110. The semiconductor die 120 includes at least one bond pad 124 disposed along one of the left edges of the semiconductor die 120. Similarly, each of the semiconductor dies 130-150 includes at least one bond pad 134-154 disposed along one of the left edges of the respective semiconductor die 130-150.

As shown in FIG. 1, semiconductor die 120 is directly attached to substrate 110 via a layer of adhesive 160, such as a die attach film. The semiconductor die 130 is attached to the semiconductor die 120 via the adhesive layer 160, and the left edge of the semiconductor die 130 is offset from the left edge of the semiconductor die 120 by an offset length Loffset in a first direction x. Similarly, the semiconductor die 140 is attached to the semiconductor die 130 via the adhesive layer 160, and the semiconductor die 140 The left edge is offset from the left edge of the semiconductor die 130 by a same offset length Loffset along a first direction x. In addition, the semiconductor die 150 is attached to the semiconductor die 140 via the adhesive layer 160, and the left edge of the semiconductor die 150 is offset from the left edge of the semiconductor die 140 by a same offset length Loffset in a first direction x. In this manner, the semiconductor dies 120-150 are sequentially stacked in a generally stepped shape such that the bond pads 124-144 of the semiconductor dies 120-140 are exposed and accessible for subsequent wire bonding procedures. In addition, the respective bonding pads 124 to 154 of the semiconductor dies 120 to 150 are disposed close to each other in order to reduce the overall length of the wiring layout in the semiconductor device 100. However, the configuration shown in Figure 1 occupies a substantially large area on the substrate. For example, assuming that each of the semiconductor dies 120-150 has the same size along one of the first directions x, the semiconductor die 120 projected onto the substrate 110 along the first direction x can be calculated as follows. One of the coverage areas to 150 is Lfootprint: Lfootprint = 3 x Loffset + Ldie, where Ldie is the length of one of the individual semiconductor dies projected on the substrate along the first direction x.

In contrast, the semiconductor device 200 including a substrate 210 and semiconductor dies 220-250 as shown in FIG. 2 is configured in a different configuration than one of the configurations shown in FIG. Similar to semiconductor device 100, each of semiconductor dies 220-250 has at least one bond pad 224-254 disposed along one of the left edges of respective semiconductor dies 220-250, respectively. However, the semiconductor dies 220 to 250 are divided into a first group G1 and a second group G2. The first group G1 includes a bottom semiconductor die 220 and a top semiconductor die 230, wherein a left edge of the semiconductor die 230 is offset from the left edge of the semiconductor die 220 by a offset length Loffset along the first direction x. . Similarly, the second group G2 includes a bottom semiconductor die 240 and a top semiconductor die 250, wherein a left edge of one of the semiconductor die 250 is offset from the left edge of one of the semiconductor die 240 by a same offset in the first direction x. Move the length Loffset. The first group G1 and the second group G2 are stacked and vertically aligned in a vertical stack configuration.

In this manner, the semiconductor dies 220 to 250 of the configuration shown in FIG. 2 occupy the base. The board is smaller than the area of the configured semiconductor die 120 to 150 shown in FIG. For example, assuming that each of the semiconductor dies 220-250 has the same size along one of the first directions x, the semiconductor die 220 projected onto the substrate 210 along the first direction x can be calculated as follows. One of the coverage areas to 250 is Lfootprint: Lfootprint = Loffset + Ldie, which is smaller than the footprint length Lfootprint of the semiconductor dies 120 to 150 projected on the substrate 110 along the first direction x. Therefore, the semiconductor device 200 is compacter than the semiconductor device 100.

3A through 3B are schematic side views showing a method of fabricating one of the semiconductor devices 200. As shown in FIG. 3A, the bottom semiconductor die 220 of the first group G1 is directly attached to the substrate 210 via a layer of adhesive 260, such as a die attach film. The top semiconductor die 230 of the first group G1 is attached to the bottom semiconductor die 220 via an adhesive layer 260. The left edge of the semiconductor die 230 is offset from the left edge of the semiconductor die 220 by an offset length Loffset in a first direction x to expose the bond pads 224 on the semiconductor die 220.

Then, as shown in FIG. 3B, a wire bonding process is performed to electrically connect the corresponding bond pads 224 and bond pads 234 using a bond wire 270. The wire bonding structures formed on the bonding pads 224 and 234 are not shown in detail.

Next, as shown in FIG. 3C, the bottom semiconductor die 240 of the second group G2 is attached to the top semiconductor die 230 of the first group G1 via an adhesive layer 260. The previously formed bond wires 270 may be partially embedded in the adhesive layer 260. The left edge of the semiconductor die 240 is vertically aligned with the left edge of the bottom semiconductor die 220 of the first group G1. The top semiconductor die 250 of the second group G2 is attached to the bottom semiconductor die 240 via an adhesive layer 260. The left edge of the semiconductor die 250 is also offset from the left edge of the semiconductor die 240 by an offset length Loffset that is the same as the offset length of the first group G1 in the first direction x to expose the bond pads 244 on the semiconductor die 240. .

Then, a one-line bonding process is performed to electrically connect the corresponding bonding pads 244 and bonding pads 254 using a bonding wire 270. The wire bonding process can be performed by a needle dispensing tool 290, referred to as a capillary having a central cavity of the feed wire 270. As shown in Figure 3D, the capillary 290 applies a force F to the bond pad 244 during the wire bonding process. Since the bond pad 244 of the semiconductor die 240 extends from the left edge of the semiconductor die 230, this force F induces a bending stress σ on the semiconductor die 240. The stress σ can be expressed by the following equation:

Wherein F is the force applied to the bond pad 240, one of the centers of the L-type bond pads 244 is in a direction opposite to the first direction x (ie, a negative x-direction, as shown in FIG. 3D) from the semiconductor die 230. The left edge offset is one of the overhanging distances Doverhang, t is the thickness of one of the semiconductor dies 240 in the z direction, and b is the width of the semiconductor dies 240 along the y direction perpendicular to the pattern of FIG. 3D. In order to reduce the stress σ which may otherwise cause defects such as grain breakage or grain breakage in the semiconductor die 240, it is necessary to reduce the overhang distance Doverhang in the semiconductor device 200.

In one embodiment, a semiconductor device includes: a substrate; and at least two semiconductor die groups stacked on the substrate, each semiconductor die group including at least one bottom semiconductor die and a top semiconductor a plurality of semiconductor die groups including a sub-semiconductor die group and an overlying semiconductor die group, the overlying semiconductor die group directly placing the bottom semiconductor die on the underlying On the top semiconductor die of the semiconductor die group, each of the at least two semiconductor die groups includes at least one bond pad aligned along a first edge of each of the semiconductor die, The first edge of the top semiconductor die is offset from the first edge of the bottom semiconductor die by a group offset length Lgoffset in a first direction in each semiconductor die group, wherein Between the overlying semiconductor die group and the underlying semiconductor die group, the first edge of the bottom semiconductor die of the overlying semiconductor die group is from the underlying semiconductor die along the first direction The first edge of the bottom semiconductor die of the group of shift The bit shift length Lshift, and wherein the group offset length Lgoffset of the underlying semiconductor die group is greater than or equal to the shift length Lshift of the overlying semiconductor die group.

In another embodiment, a semiconductor device includes: a substrate; and at least two semiconductor die groups stacked on the substrate, each semiconductor die group including at least one bottom semiconductor die and a top semiconductor a plurality of semiconductor die groups including a sub-semiconductor die group and an overlying semiconductor die group, the overlying semiconductor die group directly placing the bottom semiconductor die on the underlying On the top semiconductor die of the semiconductor die group, each of the at least two semiconductor die groups further includes at least one first aligned along a first edge of each of the semiconductor die a bond pad and at least one second bond pad aligned along a second edge of each of the semiconductor dies, the first edge being adjacent to the second edge and the first edge being substantially perpendicular to the second edge, wherein Within each semiconductor die group, the first edge of the top semiconductor die is offset from the first edge of the bottom semiconductor die by a first group offset length Lxgoffset along a first direction The second edge of the top semiconductor die is offset from the second edge of the bottom semiconductor die by a second group offset length Lygoffset in a second direction, the first direction being substantially perpendicular to the second direction Between the overlying semiconductor die group and the underlying semiconductor die group, the first edge of the bottom semiconductor die of the overlying semiconductor die group is along the first direction The first edge of the bottom semiconductor die of the volt semiconductor die group is shifted by a first shift length Lxshift, and the second edge of the bottom semiconductor die of the overlying semiconductor die group is along the second Transmitting a second shift length Lyshift from the second edge of the bottom semiconductor die of the underlying semiconductor die group, and wherein the first group offset length of the underlying semiconductor die group The Lxgoffset is greater than or equal to the first shift length Lxshift of the overlying semiconductor die group, and the second group offset length Lygoffset of the underlying semiconductor die group is greater than or equal to the overlying semiconductor die group The second shift length of the group Ly Shift.

100‧‧‧Semiconductor device

110‧‧‧Substrate

120‧‧‧Semiconductor grains

124‧‧‧Join pad

130‧‧‧Semiconductor grains

134‧‧‧ joint pad

140‧‧‧Semiconductor grain

144‧‧‧ joint pad

150‧‧‧Semiconductor grain

154‧‧‧ joint pad

160‧‧‧Binder layer

200‧‧‧Semiconductor device

210‧‧‧Substrate

220‧‧‧Semiconductor grain

224‧‧‧ joint pad

230‧‧‧Semiconductor grains

234‧‧‧ joint pad

240‧‧‧Semiconductor grain

244‧‧‧ joint pad

250‧‧‧Semiconductor grain

254‧‧‧ joint pad

260‧‧‧Binder layer

270‧‧‧bonding line

290‧‧・Needle dispensing tool/capillary

1000‧‧‧Semiconductor device

1010‧‧‧Substrate

1060‧‧‧Binder layer

1070‧‧‧bonding line

1090‧‧‧Capillary

1100‧‧‧Semiconductor grain

1104‧‧‧Material pads

1200‧‧‧ semiconductor die

1204‧‧‧ Bonding mat

1300‧‧‧Semiconductor grain

1304‧‧‧Material pads

1400‧‧‧Semiconductor grain

1404‧‧‧Material pads

2000‧‧‧Semiconductor device

2010‧‧‧Substrate

2060‧‧‧Binder layer

2070‧‧‧bonding line

2100‧‧‧Semiconductor grains

2200‧‧‧Semiconductor grain

2300‧‧‧Semiconductor grain

2400‧‧‧Semiconductor grains

2500‧‧‧Semiconductor grain

2600‧‧‧Semiconductor grain

2700‧‧‧Semiconductor grain

2800‧‧‧Semiconductor grain

5000‧‧‧Semiconductor device

5010‧‧‧Substrate

5100‧‧‧Semiconductor grain

5200‧‧‧Semiconductor grain

5300‧‧‧Semiconductor grain

5400‧‧‧Semiconductor grain

5404‧‧‧First joint pad

5414‧‧‧Second joint pad

Doverhang‧‧‧External elongation

F‧‧‧ force

G1‧‧‧ under the first group / first group

G2‧‧‧Overlay second group/second group/underline group

G3‧‧‧Overlay group/third group

G4‧‧‧ fourth group

Ldie‧‧‧projects a single semiconductor die on the substrate along the first direction x One length

Lfootprint‧‧‧ Coverage Length

Lgap‧‧‧ gap length

Lgoffset‧‧‧ group offset length

Loffset‧‧‧ offset length

Lshift‧‧‧ shift length

Lxgoffset‧‧‧first group offset length

Lxshift‧‧‧ first shift length

Lygoffset‧‧‧Second group offset length

Lyshift‧‧‧second shift length

T‧‧‧thickness

Figure 1 is a schematic side view showing a conventional semiconductor device.

2 is a schematic side view showing another conventional semiconductor device.

3A through 3D are schematic side views showing a method of fabricating one of the semiconductor devices shown in Fig. 2.

4A and 4B are schematic side views and plan views of a semiconductor device according to a first embodiment of the present technology.

5A through 5E are schematic side views showing a method of fabricating one of the semiconductor devices shown in Figs. 4A and 4B.

Figure 6 is a schematic side view of a semiconductor device in accordance with a second embodiment of the present technology.

Figure 7 is a schematic side view of a semiconductor device in accordance with a third embodiment of the present technology.

Figure 8 is a schematic side view of a semiconductor device in accordance with a fourth embodiment of the present technology.

Figure 9 is a schematic plan view of a semiconductor device in accordance with a fifth embodiment of the present technology.

Embodiments will now be described with reference to Figures 4A through 9 associated with a semiconductor device. It should be understood that the present technology may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, the embodiments are provided so that this disclosure will be thorough and In fact, the present invention is intended to cover alternatives, modifications, and equivalents of the embodiments of the present invention. The alternatives, modifications and equivalents of the embodiments are still included in the scope and spirit of the invention as defined by the scope of the appended claims. Inside. In addition, numerous specific details are set forth in the following detailed description of the embodiments of the invention in order to provide a However, it will be apparent to those skilled in the art that the present invention may be practiced without the specific details.

The terms "left", "right", "top", "bottom", "overlay", "lower", "vertical" and/or "horizontal" are used for convenience and description purposes only. It is not intended to limit the description of the techniques of the present invention, as the items mentioned may be exchanged in the appropriate places. In all of the figures of the present application, wire bonding structures and molding compounds are not shown for clarity and simplicity.

4A and 4B are respectively a schematic side view and a plan view of a semiconductor device 1000 according to a first embodiment of the present technology.

The semiconductor device 1000 includes a substrate 1010 and four semiconductor dies 1100 to 1400. Substrate 1010 has a substantially rectangular outline, for example, as shown in the plan view of Figure 5B. The semiconductor dies 1100 through 1400 can have a substantially identical rectangular profile having long and short sides that are parallel to the long and short sides of the substrate 1010, respectively. Each of the semiconductor dies 1100 through 1400 includes at least one bond pad 1104 through 1404 aligned along a short side of the respective semiconductor die. In the case where a plurality of bond pads are present on the respective semiconductor dies, the bond pads have equal distances relative to the left edge of the respective semiconductor die.

The semiconductor crystal grains 1100 to 1400 may be divided into a first underlying group G1 and a second overlying group G2. The first group G1 includes a bottom semiconductor die 1100 and a top semiconductor die 1200, wherein the bottom semiconductor die 1100 is directly attached to the substrate 1010 via a bonding layer 1060 such as a die attach film. The top semiconductor die 1200 is attached to the bottom semiconductor die 1100 via the adhesive layer 1060, and one of the left edges of the semiconductor die 1200 is offset from the left edge of the semiconductor die 1100 by a group offset length in the first direction x. Lgoffset. The corresponding bonding pads 1104 and bonding pads 1204 are electrically connected by a bonding wire 1070. The second group G2 includes a bottom semiconductor die 1300 and a top semiconductor die 1400, wherein the bottom semiconductor die 1300 is directly attached to the top semiconductor die 1200 of the first underlying group G1 via the adhesive layer 1060. The top semiconductor die 1400 is attached to the bottom semiconductor die 1300 via the adhesive layer 1060, and one of the left edges of the semiconductor die 1400 is offset from the left edge of one of the semiconductor die 1300 by a group offset length in the first direction x. Lgoffset. Corresponding to bonding pad 1304 and Bond pads 1404 are electrically connected by a bond wire 1070.

Since only two semiconductor dies exist in the first group G1 and the second group G2, in the first group G1 and the second group G2, from the left edge of the top semiconductor die to the left of the bottom semiconductor die The group offset length Lgoffset of the edges is equal to the offset length Loffset between two adjacent semiconductor dies within the respective groups.

Unlike the semiconductor device 200 shown in FIG. 2, in the semiconductor device 1000, the first group G1 and the second group G2 are not vertically aligned, but the left semiconductor die 1300 of the second overlying group G2 is left. The edge is offset from the left edge of the bottom semiconductor die 1100 of the first underlying group G1 by a shift length Lshift in the first direction x. As shown in FIG. 4A, the group offset length Lgoffset of the first group G1 is greater than the shift length Lshift of the second group G2. In other embodiments, the group offset length Lgoffset of the first group G1 is equal to the shift length Lshift of the second group G2 such that the left edge of the bottom semiconductor die 1300 of the second overlying group G2 is The left edge of the top semiconductor die 1200 of the lower volt group G1 is vertically aligned. Since the group offset length Lgoffset of the underlying group is greater than or equal to the shift length Lshift of the overlying group, the semiconductor device 1000 according to the present invention is compared to the vertical die stack configuration of the conventional semiconductor device 200. Has a ramp die stack configuration.

In the semiconductor device 1000, the coverage length Lfootprint of one of the first group G1 and the second group G2 projected on the substrate 1010 is centered on the substrate 1010 along the first direction x, wherein the left and right sides of the substrate 1010 have The equal gap length Lgap is promoted to facilitate subsequent molding procedures for one of the semiconductor devices 1000. Further details and advantages of the semiconductor device 1000 in accordance with the first embodiment of the present technology will be discussed with reference to a method of fabricating one of the semiconductor devices 1000 as shown in FIGS. 5A-5E.

As shown in FIG. 5A, the substrate 1010 is provided to be provided in an insulating resin body (especially using a glass-epoxy resin, BT (double-maleimide triazine resin) resin or the like) and both sides thereof. One of the wiring networks (not shown) on the wiring board, such as a printed circuit board (PCB).

Next, as shown in FIG. 5B, the bottom semiconductor die 1100 of the first group G1 is directly attached to the substrate 1010 via one of the adhesive layers 1060 such as a die attach film (DAF). The top semiconductor die 1200 of the first group G1 is attached to the bottom semiconductor die 1100 via an adhesive layer 1060. The left edge of the semiconductor die 1200 is offset from the left edge of the semiconductor die 1100 by a set of offset lengths Lgoffset in a first direction x to expose the bond pads 1104 on the semiconductor die 1100.

Next, as shown in FIG. 5C, a one-line bonding process is performed to electrically connect the corresponding bond pads 1104 and bond pads 1204 using a bond wire 1070. The wire bonding structure formed on the bonding pads 1104 and 1204 is not shown in detail. The wire bond structure can be a ball bond, a wedge bond, or other form of wire bond structure as is known in the art.

Next, as shown in FIG. 5D, the bottom semiconductor die 1300 of the second group G2 is attached to the top semiconductor die 1200 of the first group G1 via an adhesive layer 1060. The previously formed bond wires 1070 can be partially embedded in the adhesive layer 1060, and the adhesive layer 1060 can be a DAF or a film embedded with a wire. The left edge of the semiconductor die 1300 is offset from the left edge of the bottom semiconductor die 1100 of the first group G1 by a shift length Lshift in the first direction x. The top semiconductor die 1400 of the second group G2 is attached to the bottom semiconductor die 1300 via an adhesive layer 1060. The left edge of the semiconductor die 1400 is also offset from the left edge of the semiconductor die 1300 in the first direction x by a group offset length Lgoffset that is the same as the group offset length of the first group G1 to expose the semiconductor die 1300. Bond pad 1304. The group offset length Lgoffset of the first group G1 is greater than or equal to the shift length Lshift of the second group G2.

Next, as shown in FIG. 5E, a one-line bonding process is performed to electrically connect the corresponding bond pads 1304 and bond pads 1404 using a bond wire 1070. The wire bonding process can be performed by the capillary 1090. As shown in Figure 5E, the capillary 1090 applies a force F to the bond pad 1304 during the wire bonding procedure. Since the bonding pad 1304 of the semiconductor die 1300 extends from the left edge of the semiconductor die 1200, the force F induces a bending stress on the semiconductor die 1300. σ. According to equation (1), the bending stress σ is proportional to the overhanging distance Doverhang; therefore, it is desirable to reduce Doverhang in order to reduce the stress σ that would otherwise cause defects such as grain fragmentation or grain cracking in the semiconductor die 1300. Since the second group G2 is shifted by the shift length Lshift in the first direction x with respect to the first group G1, the Doverhang of the semiconductor device 1100 is reduced as compared with the semiconductor device 200. In one aspect, Doverhang may be further reduced as the shift length Lshift increases, as the bottom semiconductor die 1300 overlying the second group G2 is shifted in the first direction x. In the case where the shift length Lshift of the second group G2 is equal to the group offset length Lgoffset of the first group G1, there is no overhang under the bonding pad 1304 of the semiconductor die 1300 and Doverhang is zero, thus the wire bonding There is no bending force applied to the bond pad 1304 during the procedure in order to avoid defects such as chip breakage or cracking. In this way, the yield of a semiconductor device having a stacked configuration can be improved. On the other hand, the area occupied by the semiconductor crystal grains 1100 to 1400 on the substrate 1010 increases as the shift length Lshift increases. For example, the footprint length Lfootprint of the semiconductor dies 1100 through 1400 along the first direction x on the substrate 1010 increases as the shift length Lshift increases. Therefore, the shift length Lshift of the overlying group G2 can be adjusted accordingly to achieve an appropriate compromise.

In the embodiment shown above, a bond line is connected between corresponding bond pads on respective semiconductor dies. As used herein, "corresponding" bonding pads refers to bonding pads on different semiconductor dies that are aligned with each other along one of the edges of the semiconductor die including the bonding pads. However, in a further embodiment, the bond wires can be bonded to the diagonally oriented die bond pads on the respective semiconductor die. Moreover, while the embodiments shown above exhibit bonding wires between adjacent dies, it should be understood that the bonding wires can be used between corresponding die bond pads on non-adjacent dies within the same group or at non- A connection is made between the diagonal die bond pads on the adjacent die.

Figure 6 is a schematic side view of a semiconductor device 2000 in accordance with a second embodiment of the present technology. The semiconductor device 2000 includes a substrate 2010 and eight semiconductor dies 2100 to 2800 divided into four groups G1 to G4. The first group G1 contains the bottom semiconductor The die 2100 and the top semiconductor die 2200, wherein the bottom semiconductor die 2100 is directly attached to the substrate 2010 via a bond layer 2060 such as a die attach film. The top semiconductor die 2200 is attached to the bottom semiconductor die 2100 via the adhesive layer 2060, and one of the left edges of the semiconductor die 2200 is offset from the left edge of the semiconductor die 2100 by a group offset length in the first direction x. Lgoffset. The corresponding bond pads of the semiconductor dies 2100 and 2200 are electrically connected by a bond wire 2070. The second group G2 includes a bottom semiconductor die 2300 and a top semiconductor die 2400, wherein the bottom semiconductor die 2300 is directly attached to the top semiconductor die 2200 of the first group G1 via the adhesive layer 2060. The top semiconductor die 2400 is attached to the bottom semiconductor die 2300 via the adhesive layer 2060, and one of the left edges of the semiconductor die 2400 is offset from the left edge of one of the semiconductor die 2300 by a group offset length in the first direction x. Lgoffset. The corresponding bond pads of the semiconductor dies 2300 and 2400 are electrically connected by a bond wire 2070. The third group G3 includes a bottom semiconductor die 2500 and a top semiconductor die 2600, wherein the bottom semiconductor die 2500 is directly attached to the top semiconductor die 2400 of the second group G2 via the adhesive layer 2060. The top semiconductor die 2600 is attached to the bottom semiconductor die 2500 via the adhesive layer 2060, and one of the left edges of the semiconductor die 2600 is offset from the left edge of the semiconductor die 2500 by a group offset length in the first direction x. Lgoffset. The corresponding bond pads of the semiconductor dies 2500 and 2600 are electrically connected by a bond wire 2070. The fourth group G4 includes a bottom semiconductor die 2700 and a top semiconductor die 2800, wherein the bottom semiconductor die 2700 is directly attached to the top semiconductor die 2600 of the third group G3 via the adhesive layer 2060. The top semiconductor die 2800 is attached to the bottom semiconductor die 2700 via the adhesive layer 2060, and one of the left edges of the semiconductor die 2800 is offset from the left edge of one of the semiconductor die 2700 by a group offset length in the first direction x. Lgoffset. The corresponding bond pads of the semiconductor dies 2700 and 2800 are electrically connected by a bond wire 2070.

In the semiconductor device 2000, the left edge of the bottom semiconductor die 2300 of the second group G2 is offset from the left edge of the bottom semiconductor die 2100 of the first group G1 by a shift length Lshift in the first direction x. In the same way, the bottom semiconductor die 2500 of the third group G3 The left edge is offset from the left edge of the bottom semiconductor die 2300 of the second group G2 by a shift length Lshift along the first direction x, and the left edge of the bottom semiconductor die 2700 of the fourth group G4 is along the first direction x is offset from the left edge of the bottom semiconductor die 2500 of the third group G3 by a shift length Lshift.

For each pair of adjacent overlying groups and underlying groups in the semiconductor device 2000, the group offset length Lgoffset of the underlying group is greater than or equal to the shift length Lshift of the overlying group. For example, the group offset length Lgoffset of the underlying group G2 is greater than or equal to the shift length Lshift of the overlying group G3. Other aspects and details of semiconductor device 2000 are substantially the same as semiconductor device 1000 and are therefore omitted herein to avoid redundancy. It should be noted that for a typical micro SD ^TM package having one of the eight semiconductor dies implemented in accordance with the second embodiment of the present technology, the semiconductor die extensibility Doverhang shown in FIG. 6 can be reduced by up to 25%. Among them, the semiconductor device has a yield improvement of more than 7%.

Figure 7 is a schematic side view of a semiconductor device 3000 in accordance with a third embodiment of the present technology. The semiconductor device 3000 is substantially identical to the semiconductor device 2000, except that each of the first group G1 to the fourth group G4 of semiconductor dies includes three semiconductor dies (ie, a bottom semiconductor die, a middle Except for semiconductor dies and a top semiconductor die). Within each semiconductor die group, the left edge of the top semiconductor die is offset from the left edge of the bottom semiconductor die by a set of offset lengths Lgoffset, which is the adjacent crystal within the group. The sum of the offset lengths between the granules, Loffset. For example, the group offset length of G4 is the sum of the offset length Loffset from the intermediate semiconductor die to the bottom semiconductor die and the offset length Loffset from the top semiconductor die to the intermediate semiconductor die.

For each pair of adjacent overlying groups and underlying groups in the semiconductor device 3000, the group offset length Lgoffset of the underlying group is greater than or equal to the shift length Lshift of the overlying group. For example, the group offset length Lgoffset of the underlying group G2 is greater than or equal to the shift length Lshift of the overlying group G3. Other aspects and details of the semiconductor device 3000 and half Conductor device 2000 is substantially identical and is therefore omitted herein to avoid redundancy. A semiconductor device in accordance with the teachings of the present invention can include two or more semiconductor dies in each group.

Figure 8 is a schematic side view of a semiconductor device 4000 in accordance with a fourth embodiment of the present technology. The semiconductor device 4000 is substantially identical to the semiconductor device 2000 except that the groups G1 to G4 in the semiconductor device 4000 include a different number of semiconductor dies. As shown in FIG. 8, each of the first group G1 and the fourth group G4 includes two semiconductor dies, and each of the second group G2 and the third group G3 includes three Semiconductor die.

For each pair of adjacent overlying groups and underlying groups in the semiconductor device 4000, the group offset length Lgoffset of the underlying group is greater than or equal to the shift length Lshift of the overlying group. For example, the group offset length Lgoffset of the underlying group G2 is greater than or equal to the shift length Lshift of the overlying group G3. In addition, all of the bond pads of the bottom semiconductor die of the overlying semiconductor die group have a uniform distance Doverhang. For example, the Doverhang of the bonding pads of the bottom semiconductor die of the second group G2, the Doverhang of the bonding pads of the bottom semiconductor die of the third group G3, and the bonding pads of the bottom semiconductor die of the fourth group G4 Doverhang is uniform. In this case, a uniform force can be applied to the respective bottom semiconductor dies of the groups G2 to G4 by capillary during the subsequent wire bonding process so that the respective bottom semiconductor dies of the groups G2 to G4 are subjected to a Uniform bending stress. In this way, it is not necessary to adjust the program parameters during the wire bonding process of the semiconductor device 4000, which reduces cost and improves throughput. Other aspects and details of semiconductor device 4000 are substantially the same as semiconductor device 2000 and are therefore omitted herein to avoid redundancy.

Figure 9 is a schematic plan view of a semiconductor device 5000 in accordance with a fifth embodiment of the present technology. For better illustration, the wire joint structure is not shown in FIG. The semiconductor device 5000 includes a substrate 5010 and four semiconductor dies 5100 to 5400 divided into a first underlying group G1 and a second overlying group G2. Each semiconductor die is included along At least one first bond pad of the first edge of each of the semiconductor dies and at least one second bond pad aligned along a second edge of each of the semiconductor dies. The first edge is adjacent to the second edge and the first edge is substantially perpendicular to the second edge. For example, semiconductor die 5400 includes a first bond pad 5404 aligned along one of the left edges of semiconductor die 5400 and a second bond pad 5414 aligned along a lower edge of one of semiconductor die 5400, as shown in FIG. Shown in the middle. The left and lower edges of the semiconductor die 5400 are adjacent edges and are substantially perpendicular to each other.

The first group G1 includes a bottom semiconductor die 5100 and a top semiconductor die 5200, wherein the bottom semiconductor die 5100 is directly attached to the substrate 5010. The top semiconductor die 5200 is attached to the bottom semiconductor die 5100. The left edge of one of the top semiconductor dies 5200 is offset from the left edge of one of the bottom semiconductor dies 5100 by a first group offset length Lxgoffset in the first direction x. The lower edge of the top semiconductor die 5200 is offset from the lower edge of the bottom semiconductor die 5100 by a second group offset length Lygoffset in a second direction y. The second direction y is substantially perpendicular to the first direction x.

The second group G2 includes a bottom semiconductor die 5300 and a top semiconductor die 5400, wherein the bottom semiconductor die 5300 is directly attached to the top semiconductor die 5200 of the first underlying group G1. The top semiconductor die 5400 is attached to the bottom semiconductor die 5300. One of the left edges of the semiconductor die 5400 is offset from the left edge of one of the semiconductor die 5300 by a first group offset length Lxgoffset in the first direction x. The lower edge of the top semiconductor die 5400 is offset from the lower edge of the bottom semiconductor die 5400 by a second group offset length Lygoffset in a second direction y.

As shown in FIG. 9, the first group G2 is offset from the first group G1 along both the first direction x and the second direction y. That is, the left edge of the bottom semiconductor die 5300 overlying the second group G2 is displaced in the first direction x from the left edge of the bottom semiconductor die 5100 of the underlying first group G1 by a first shift length Lxshift And the lower edge of the bottom semiconductor die 5300 overlying the second group G2 is in the second direction y from the bottom semiconductor die of the first group G1 The lower edge is shifted by a second shift length Lyshift. The first group offset length Lxgoffset of the first group G1 is greater than or equal to the first shift length Lxshift of the second group G2, and the second group offset length Lygoffset of the first group G1 is greater than or equal to the second The second shift length of the group G2 is Lyshift. Other aspects and details of semiconductor device 5000 are substantially the same as semiconductor device 2000 and are therefore omitted herein to avoid redundancy.

A semiconductor device having a ramp die stack configuration in accordance with the teachings of the present invention achieves an improvement in yield, particularly during an on-line bonding process.

In one aspect, the present technology is directed to a semiconductor device. The semiconductor device includes a substrate and at least two semiconductor die groups stacked on the substrate. Each semiconductor die group includes at least one bottom semiconductor die and a top semiconductor die. Each of the at least two semiconductor die groups includes at least one bond pad aligned along a first edge of each of the semiconductor die. The at least two semiconductor die groups include a group of underlying semiconductor dies and a group of overlying semiconductor dies. The bottom semiconductor die of the overlying semiconductor die group is disposed directly on the top semiconductor die of the underlying semiconductor die group. Within each semiconductor die group, the first edge of the top semiconductor die is offset from the first edge of the bottom semiconductor die by a group offset length Lgoffset in a first direction. Between the overlying semiconductor die group and the underlying semiconductor die group, the first edge of the bottom semiconductor die of the overlying semiconductor die group is from the underlying semiconductor along the first direction The first edge of the bottom semiconductor die of the die group is shifted by a shift length Lshift. The group offset length Lgoffset of the underlying semiconductor die group is greater than or equal to the shift length Lshift of the overlying semiconductor die group.

In some embodiments, one of the bond pads of the bottom semiconductor die of the overlying group is in the first direction opposite the first direction from the first of the top semiconductor die of the underlying group The edge is offset by an overhanging distance. The extents of all of the bond pads of the bottom semiconductor dies of the overlying semiconductor die group are uniform. The length of the coverage area of one of the at least two semiconductor die groups projected on the substrate is centered along the first direction On the substrate.

In another aspect, the present technology is directed to a semiconductor device. The semiconductor device includes a substrate and at least two semiconductor die groups stacked on the substrate. Each semiconductor die group includes at least one bottom semiconductor die and a top semiconductor die. Each of the at least two semiconductor die groups further includes at least one first bond pad aligned along a first edge of each of the semiconductor die and one along each of the semiconductor die At least one second bond pad aligned with the two edges. The first edge is adjacent to the second edge and the first edge is substantially perpendicular to the second edge. The at least two semiconductor die groups include a group of underlying semiconductor dies and a group of overlying semiconductor dies. The bottom semiconductor die of the overlying semiconductor die group is disposed directly on the top semiconductor die of the underlying semiconductor die group. Within each semiconductor die group, the first edge of the top semiconductor die is offset from the first edge of the bottom semiconductor die by a first group offset length Lxgoffset in a first direction, the top The second edge of the semiconductor die is offset from the second edge of the bottom semiconductor die by a second group offset length Lygoffset in a second direction, the first direction being substantially perpendicular to the second direction. Between the overlying semiconductor die group and the underlying semiconductor die group, the first edge of the bottom semiconductor die of the overlying semiconductor die group is from the underlying semiconductor along the first direction The first edge of the bottom semiconductor die of the die group is shifted by a first shift length Lxshift, and the second edge of the bottom semiconductor die of the overlying semiconductor die group is along the second direction The second edge of the bottom semiconductor die of the underlying semiconductor die group is shifted by a second shift length Lyshift. The first group offset length Lxgoffset of the underlying semiconductor die group is greater than or equal to the first shift length Lxshift of the overlying semiconductor die group, and the underlying semiconductor die group The two group offset length Lygoffset is greater than or equal to the second shift length Lyshift of the overlying semiconductor die group.

In some embodiments, a center of the first bonding pad of the bottom semiconductor die of the overlying group is semi-conductive from the top of the underlying group in a direction opposite to the first direction The first edge of the bulk die is offset by a first overhanging distance, and the center of the second bonding pad of the bottom semiconductor die of the overlying group is in a direction opposite to the second direction The first edge of the top semiconductor die of the volt group is offset by a second overhang distance. The first overhanging distances of all the first bonding pads of the bottom semiconductor dies of the overlying semiconductor die group are uniform, and the bottom semiconductor dies of the overlying semiconductor die group The second overhanging distances of all of the second bonding pads are uniform.

The detailed description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments described herein are chosen to best explain the principles of the invention and its application, and thus, The invention is utilized optimally. The scope of the invention is intended to be defined by the scope of the appended claims.

1000‧‧‧Semiconductor device

1010‧‧‧Substrate

1060‧‧‧Binder layer

1070‧‧‧bonding line

1100‧‧‧Semiconductor grain

1104‧‧‧Material pads

1200‧‧‧ semiconductor die

1204‧‧‧ Bonding mat

1300‧‧‧Semiconductor grain

1304‧‧‧Material pads

1400‧‧‧Semiconductor grain

1404‧‧‧Material pads

G1‧‧‧ under the first group / first group

G2‧‧‧Over the second group/second group

Lfootprint‧‧‧ Coverage Length

Lgap‧‧‧ gap length

Lgoffset‧‧‧ group offset length

Lshift‧‧‧ shift length

Claims (7)

A semiconductor device comprising: a substrate; and at least two semiconductor die groups stacked on the substrate, each semiconductor die group comprising at least one bottom semiconductor die and a top semiconductor die, the at least The two semiconductor die groups include a sub-semiconductor die group and an overlying semiconductor die group, the overlying semiconductor die group directly positioning the bottom semiconductor die in the underlying semiconductor die group On the top semiconductor die, each of the at least two semiconductor die groups includes at least one bond pad aligned along a first edge of each of the semiconductor die, wherein each semiconductor Within the die group, the first edge of the top semiconductor die is offset from the first edge of the bottom semiconductor die by a group offset length Lgoffset along a first direction, wherein the overlying semiconductor die Between the group and the underlying semiconductor die group, the first edge of the bottom semiconductor die of the overlying semiconductor die group is from the underlying semiconductor die group in the first direction The first edge of the semiconductor die is shifted by a shift length Lshift, and wherein the group offset length Lgoffset of the underlying semiconductor die group is greater than or equal to the shift of the overlying semiconductor die group Length Lshift. The semiconductor device of claim 1, wherein a center of the bonding pad of the bottom semiconductor die of the overlying group is in a direction opposite to the first direction from the top semiconductor die of the underlying group The first edge is offset by an overhanging distance. The semiconductor device of claim 2, wherein the overhanging distances of all of the bonding pads of the bottom semiconductor dies of the overlying semiconductor die group are uniform. The semiconductor device of claim 1, wherein the at least two halves projected on the substrate A length of the footprint of one of the group of conductor dies is centered on the substrate along the first direction. A semiconductor device comprising: a substrate; and at least two semiconductor die groups stacked on the substrate, each semiconductor die group comprising at least one bottom semiconductor die and a top semiconductor die, the at least The two semiconductor die groups include a sub-semiconductor die group and an overlying semiconductor die group, the overlying semiconductor die group directly positioning the bottom semiconductor die in the underlying semiconductor die group On the top semiconductor die, each of the at least two semiconductor die groups further includes at least one first bond pad aligned along a first edge of each of the semiconductor die and along Aligning a second edge of each of the semiconductor dies with at least one second bond pad, the first edge being adjacent to the second edge and the first edge being substantially perpendicular to the second edge, wherein each semiconductor crystal The first edge of the top semiconductor die is offset from the first edge of the bottom semiconductor die by a first group offset length Lxgoffset in a first direction, the top semiconductor The second edge of the die is offset from the second edge of the bottom semiconductor die by a second group offset length Lygoffset along a second direction, the first direction being substantially perpendicular to the second direction, wherein Between the overlying semiconductor die group and the underlying semiconductor die group, the first edge of the bottom semiconductor die of the overlying semiconductor die group is from the underlying semiconductor die along the first direction The first edge of the bottom semiconductor die of the grain group is shifted by a first shift length Lxshift, and the second edge of the bottom semiconductor die of the overlying semiconductor die group is along the second direction The second edge of the bottom semiconductor die of the underlying semiconductor die group is shifted by a second shift length Lyshift, and wherein the first group offset length Lxgoffset of the underlying semiconductor die group And greater than or equal to the first shift length Lxshift of the overlying semiconductor die group, and the second group offset length Lygoffset of the underlying semiconductor die group is greater than or equal to the overlying semiconductor die group The second shift length Lyshift. The semiconductor device of claim 5, wherein a center of the first bonding pad of the bottom semiconductor die of the overlying group is in a direction opposite to the first direction from the top semiconductor crystal of the underlying group The first edge of the grain is offset by a first overhanging distance, and a center of the second bonding pad of the bottom semiconductor die of the overlying group is from the underside in a direction opposite to the second direction The first edge of the top semiconductor die of the group is offset by a second overhang distance. The semiconductor device of claim 6, wherein the first overhanging distances of all the first bonding pads of the bottom semiconductor dies of the overlying semiconductor die group are uniform, and the overlying semiconductor die group The second overhangs of all of the second bond pads of the set of bottom semiconductor dies are uniform.