TW201405714A - Nonvolatile memory device - Google Patents

Abstract

Provided is a nonvolatile memory device. The nonvolatile memory device includes: first and second electrodes spaced from each other; at least one nano crystal layer disposed between the first and second electrodes; and first and second material layers respectively disposed between the first electrode and the nano crystal layer and between the second electrode and the nano crystal layer and having a bistable conductive property, wherein the first and second material layers are formed asymmetrical to each other.

Description

Non-volatile memory component

The present invention relates to volatile memory components, and more particularly to a non-volatile memory component using an organic material.

Memory components can be divided into volatile memory and non-volatile memory components. Dynamic random access memory (DRAM) is commonly used as a volatile memory component, and flash memory is commonly used as a non-volatile memory component. The DRAM includes a transistor and a capacitor at one end thereof, and its state is read by charging or discharging a capacitor. However, dynamic random access memory requires continuous recharging of the capacitor. In other words, if no power is supplied, the data in the DRAM will disappear due to the leakage current. Therefore, a large amount of power consumption is required to save the data. Furthermore, the flash memory includes stacked floating gates and control gates. The Fowler-Nordheim tunneling (F-N tunneling) is used to determine the threshold voltage by changing the amount of charge in the floating gate according to the voltage applied to the control gate and the channel region. However, since the flash memory utilizes the Furnohan tunneling, the voltage used is relatively high. Furthermore, since writing and reading data are performed in a predetermined order, data processing becomes slower.

In order to overcome the limitations of dynamic random access memory (DRAM) and flash memory, and to implement valuable next generation memory components, many studies are underway. According to the material constituting the memory battery (ie, the basic unit), The study of multiple generations of memory components leads to different directions. In other words, whether the material is changed to a low-resistance crystalline state or a high-resistance amorphous state, whether based on a current applied to a specific material; or through the iron after the power is applied to the material The ferroelectric property has a spontaneous polarization property whereby the material is used as a memory element; or the N and S pole properties produced by the ferromagnetic material passing through the magnetic field are attempted to store the material. The information is actively in progress. In addition, research using a conductive organic material having two different conductive properties to form a memory element is actively being carried out.

Since the non-volatile memory element utilizes a conductive organic material having a lower driving voltage and excellent bistable property, it is evaluated as a superior element. Moreover, since the data retention time becomes long, and the nature of the repeated data programming and the erased data is less changed, it is evaluated as a superior component. Therefore, research on non-volatile memory using organic materials having the above characteristics has been underway.

In addition, U.S. Patent No. 6,747,321 discloses a memory device having a special layer as a Schottky diode interposed between the memory layer and the electrode layer. In other words, U.S. Patent No. 6,747,321 has a structure in which a memory layer is stacked and a selection device using a Schottky diode is used. However, with regard to a memory element having a selected element, the nature of the memory element may vary depending on the nature of the selected element, thus making, for example, a read voltage margin or a memory tolerance. Features such as (memory margin) are deteriorated. In addition, U.S. Patent No. 7,482,621 discloses an organic memory device that forms an organic layer between an indium tin oxide (ITO) electrode and a copper electrode, and between the organic layer and the copper electrode. A lithium fluoride (Lithium fluoride, LiF) buffer layer is formed. Here, depending on the voltage applied to the two electrodes, a lithium fluoride (Lithium fluoride, LiF) buffer layer acts as a metal ion barrier or a copper ion barrier for the copper electrode.

The disclosure provides a non-volatile memory element that has no selected components.

The present disclosure also provides a non-volatile memory element that has bistable properties through structural changes at low drive voltages.

The present disclosure also provides a non-volatile memory element comprising a buffer layer that facilitates charge transfer when a forward bias is applied and inhibits charge transfer when a reverse bias is applied.

According to an exemplary embodiment, the non-volatile memory element includes a first electrode and a second electrode spaced apart from each other; at least one nano crystal layer disposed between the first electrode and the second electrode; the first material layer and the second The material layers are respectively disposed between the first electrode and the nano crystal layer and disposed between the second electrode and the nano crystal layer, and have bistable conductivity, wherein the first material layer and the second material layer are mutually Asymmetrically formed.

The nanocrystal layer may include a plurality of nanocrystals and a barrier layer, wherein the barrier layer surrounds the nanocrystals.

The first material layer may include at least one conductive organic layer, and the second material layer may include at least one conductive organic layer and at least one buffer layer.

These conductive organic layers can have different thicknesses.

At least one of the conductive organic layers may comprise a low molecular weight material, wherein the low molecular weight material has charge transfer characteristics.

At least one of the conductive organic layers may be formed of at least one of Alq ₃ , AIDCN, α-NPD, PtOEP, TPD, ZnPc, CuPc, C60, PBD, CBP, Pentacene, Balq, and PCBM.

The second material layer may include at least one of the at least one first buffer layer and the second buffer layer, wherein the first buffer layer is between the nano crystal layer and the conductive organic layer of the second material layer, and the second The buffer layer is between the conductive organic layer of the second material layer and the second electrode.

The first buffer layer and the second buffer layer may comprise a metal compound of a metal, wherein the metal has a small work function.

The first buffer layer or the second buffer layer may include a metal compound of an alkali metal or an alkaline earth metal.

The first buffer layer or the second buffer layer may be formed of at least one of LiF, NaCl, CsF, Li ₂ O, BaO, and Liq.

The first buffer layer may have a different thickness than the second buffer layer.

When a high voltage and a low voltage are respectively applied to the first electrode and the second electrode, the buffer layer can promote charge transfer in the forward bias, and when the low voltage and the high voltage are respectively applied to the first electrode and the second electrode, buffering The layer inhibits charge transfer in the forward bias.

The non-volatile memory component may further include a threshold voltage region, wherein the threshold In the voltage region, the amount of current is drastically increased according to a potential difference applied between the first electrode and the second electrode; and a negative differential resistance region in which a current is applied between the first electrode and the second electrode in the negative differential resistance region The potential difference increases and decreases.

Performing a read operation at a first voltage level below a threshold voltage; performing a programmatic operation at a second voltage level of the threshold voltage to the differential resistance region; and a third voltage level at a second voltage level greater than a second voltage level Perform an erase operation.

The non-volatile memory component can be programmed in multiple levels based on the second voltage level.

According to another exemplary embodiment, the non-volatile memory element includes: a first electrode and a second electrode spaced apart from each other; at least a nanocrystal layer disposed between the first electrode and the second electrode; and a first conductive organic layer And the second conductive organic layer is disposed between the first electrode and the nanocrystal layer, and disposed between the second electrode and the nanocrystal layer, and has bistable conductive properties; and at least one buffer layer is disposed at Between an electrode and a second electrode. Wherein, when a high voltage and a low voltage are respectively applied to the first electrode and the second electrode, the buffer layer promotes charge transfer in the forward bias, when a low voltage and a high voltage are respectively applied to the first electrode and the first electrode In the case of the two electrodes, the buffer layer suppresses charge transfer in the forward bias.

The nanocrystal layer may include a plurality of nanocrystals and a barrier layer, wherein the barrier layer surrounds the nanocrystals.

The first conductive organic layer and the second conductive organic layer may be formed of a low molecular weight material, wherein the low molecular weight material has charge transfer characteristics.

At least one of the first conductive organic layer and the second conductive organic layer may be formed of Alq ₃ , AIDCN, α-NPD, PtOEP, TPD, ZnPc, CuPc, C60, PBD, CBP, Pentecene, Balq, and PCBM.

The second conductive organic layer may be thicker than the first conductive organic layer.

The buffer layer may be prepared between the first electrode or the second electrode and the first organic layer or the second organic layer, or between the first conductive organic layer or the second conductive organic layer and the nanocrystalline layer.

The buffer layer may include a metal compound of an alkali metal or an alkaline earth metal.

These buffer layers may include metallic metal compounds having a small work function.

These buffer layers may include at least one of LiF, NaCl, CsF, Li ₂ O, BaO, and Liq.

According to an embodiment, the memory element can perform a rectifying operation as its own storage unit, so that a storage unit that performs a selection function according to the potential difference can be realized, and the storage unit is less like a diode. Additional selection components.

Moreover, the program state and the erase state can be clearly maintained at a low operating voltage, and the ratio Ion/Ioff of the on-current Ion to the off current Ioff is large, and there is no property change according to the repetitive stylization and erasing. Therefore, an excellent non-volatile memory can be realized.

Moreover, since it is not necessary to select an element, a memory element having a simple structure and being easily applied to a three-dimensional structure can be realized.

[Preferred embodiment]

In the following, the detailed implementation will be described in detail with reference to the accompanying drawings. example. However, the invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention will be fully conveyed by those skilled in the art.

1 is a cross-sectional view of a unit of storage unit in a non-volatile memory element, in accordance with an illustrative embodiment.

As shown in FIG. 1, the non-volatile memory element includes a first electrode 120, a second electrode 180, and a nanocrystal layer 140. The material layer between the first electrode 120 and the nanocrystal layer 140 and the material layer between the second electrode 180 and the nanocrystal layer 140 are formed asymmetrically with each other. Here, "asymmetry" means that the thickness of the material layers on both sides of the nanocrystal layer 140 is different, whether or not the intermediate layer such as the buffer layer, and the number of characteristics, positions, or buffer layers are included.

More specifically, the non-volatile memory element includes a first electrode 120 and a second electrode 180 that are respectively spaced apart; and a first conductive organic layer 130 having bistable conductivity between the first electrode 120 and the second electrode 180. And a second conductive organic layer 160; a nanocrystalline layer 140 between the first conductive organic layer 130 and the second conductive organic layer 160, the nanocrystalline layer 140 includes a nanocrystal 141 and an insulating layer 142; The buffer layer 150 is between the nano crystal layer 140 and the second conductive organic layer 160; and the second buffer layer 170 between the second conductive organic layer 160 and the second electrode 180.

The substrate 100 may be an insulating substrate, a semiconductor substrate, or a conductive substrate. That is, the substrate 100 may be an aluminum oxide (Al ₂ O ₃ ) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, a silicon (Si) substrate, or arsenic. Gallium arsenide (GaAs) substrate, gallium phosphide (GaP) substrate, lithium aluminum oxide (LiAl ₂ O ₃ ) substrate, boron nitride (BN) substrate, aluminum nitride At least one of an (aluminum nitride, AlN) substrate, a silicon-on-insulator (SOI) substrate, and a gallium arsenide (GaN) substrate. Here, if the substrate 100 includes a semiconductor substrate and a conductive substrate, it is necessary to form an insulator between the first electrode 120 and the substrate 110 to insulate. Further, the substrate 110 may be a rigid substrate or a flexible substrate. The flexible substrate comprises polyethylene (PE), polyether sulfide (PES) plastic substrate, polyethylene terephthalate (Poly(ethylene terephthalate), PET), or polyethylene naphthalate. Poly (Ethlene 2, 6-Naphthalene Dicarboxylate), PEN).

The first electrode 120 and the second electrode 180 may use all materials having electrical conductivity, but materials having low electrical resistance and excellent interfacial properties for organic materials may also be used. Metals such as aluminum (Aluminum, Al), titanium (Titanium, Ti), zinc (Zinc, Zn), iron (Iron, Fe), nickel (Nickel, Ni), tin (Tin, Sn), lead (Lead, Pb) Copper (Copper, Cu) and its alloy can be used as the first electrode 120 and the second electrode 180. In addition, the respectively spaced first electrodes 120 extend in one direction, and the respectively spaced second electrodes 180 extend toward the other direction perpendicular to the first electrodes 120. The material layers are stacked between the intersections of the first electrode 120 and the second electrode 180 respectively extending in the vertical direction to constitute a basic storage unit.

The first conductive organic layer 130 and the second conductive organic layer 160 may use a low molecular weight material having charge transfer properties, for example, hydroxyquinoline aluminum (Alq ₃ ), AIDCN (2-amino-4, 5-imidazoledicarbonitrile). , at least one of α-NPD (N, N'-bis (1-naphthyl)-N, N'-diphenybenzidine), PtOEP, TPD, ZnPc, CuPc, C60, PBD, CBP, Pentacene, Balq, and PCBM . In addition, the first conductive organic layer 130 and the second conductive organic layer 160 may be formed of high molecular weight polyvinylcarbazole (PVK) and polystyrene (PS). The first conductive organic layer 130 and the second conductive organic layer 160 have a bistable property, that is, have high electrical resistance and low electrical resistance at the same voltage.

Each of the first conductive organic layer 130 and the second conductive organic layer 160 may have a thickness of about 20 nm to about 70 nm, and may be the same thickness or a different thickness. For example, the second conductive organic layer 160 thicker than the first conductive organic layer 130 may be formed. The asymmetric memory is formed in such a manner as to improve the rectification operation and prevent the memory element from being damaged due to an overcurrent caused by a large amount of electric charge flowing when a forward bias is applied.

When a bias voltage is applied, the charge of the nanocrystal layer 140 is charged or discharged, and therefore, the memory element maintains a low resistance state or a high resistance state. That is, depending on the state of the nanocrystal layer 40, the memory element maintains a stylized or erased state. The nanocrystal layer 140 includes a nanocrystal 141 of a crystalline material and an insulating layer 142 (i.e., a tunneling barrier).

The nanocrystal 141 can be formed using aluminum (Al), magnesium (Mg), zinc (Zn), nickel (Ni), iron (Fe), copper (Cu), gold (Au), silver (Ag), and alloys thereof. . The insulating layer 142 may be formed around the nanocrystals 141 and may include an insulator such as an oxide or a dispersion stabilizer. For example, the nanocrystal 141 may be formed of nickel, and the insulating layer 142 may be formed of nickel oxide. The nanocrystal layer 140 can be formed by depositing and oxidizing a metal in an evaporation deposition chamber.

For example, a metal material is deposited on the first conductive organic layer 130 in the evaporation chamber, and then an oxidation process is performed using oxygen plasma therein to form the nanocrystal layer 140. However, the present invention is not limited thereto, and therefore, the nanocrystal layer 140 may be formed in the evaporation chamber via oxidation of a metal. However, in order to form a stable nanocrystal 141 having a predetermined size, a forced oxidation process can be used along the grain boundary through the O ₂ (oxygen) plasma process. The nanocrystal layer 140 includes a nanocrystal 141 formed through a metal deposition process and an oxidation process, and an insulating layer 142 surrounding the same. The quantum well depth increases due to the insulating layer 142. Therefore, the data retention of the memory element can be improved.

Also, the nanocrystal layer 140 may be formed of a single layer or a plurality of layers. The nanocrystal layer 140 having a single layer may have a thickness of from about 1 nm to about 40 nm. The single-layer nanocrystal layer 140 can be stacked one to ten layers. The nanocrystal layer 140 having the above range can maintain an effective energy gap to improve data retention of components. Also, the thickness of the nanocrystal layer 140 formed in each of the stacked layers is uniform.

The first buffer layer 150 and the second buffer layer 170 are formed under the second conductive organic layer 160, respectively. In other words, the first buffer layer is formed between the nano crystal layer 140 and the second conductive organic layer 160, and the second buffer layer 170 is formed between the second conductive organic layer 160 and the second electrode 180. At least one of the first buffer layer 150 and the second buffer layer 170 is formed of a metal compound having a low work function metal. For example, the metal compound may include an alkali metal or an alkaline earth metal. More specifically, the metal compound may be lithium fluoride (LiF), sodium chloride (NaCl), cesium fluoride (CsF), lithium oxide (Li ₂ O), barium oxide (BaO), and lithium hydroxyquinolate (Lithium quinolate). At least one of Liq) is formed. The interface properties of the first electrode 120 or the nanocrystal layer 140 may be improved with the first buffer layer 150 or the second buffer layer 170 formed.

According to an embodiment of the invention, the first buffer layer and the second buffer layer may be formed of the same material, but the invention is not limited thereto. In other words, the first buffer and the second buffer can be formed of different materials.

Each of the first conductive organic layer 150 and the second conductive organic layer 170 is formed to have a thickness of about 0.1 nm to about 1 nm, and may have the same thickness or a different thickness. For example, a second buffer layer 170 thicker than the first buffer layer 150 may be formed. Thus, when a forward bias is applied, that is, a high voltage is applied to the first electrode 120 and a low voltage is applied to the second electrode 180, the first buffer layer 150 and the second buffer layer 170 promote the nanoelectrode 180 to the nanocrystal. The charge injection and transfer of the layer 140; when the reverse bias is applied, that is, a low voltage is applied to the first electrode 120 and a high voltage is applied to the second electrode 180, and the first buffer layer 150 and the second buffer layer 170 serve as barriers. Blocking charge transfer to the second electrode 180. When the first buffer layer 150 and the second buffer layer 170, which promote charge transfer in the forward bias and function as barriers in the reverse bias, are prepared, the memory element has a rectifying function without an additional component such as a diode. And as a battery.

Although the non-volatile memory element includes the first buffer layer 150 and the second buffer layer 170 as described above, the present invention is not limited thereto. Therefore, a non-volatile memory element including at least one of the first buffer layer 150 and the second buffer layer 170 can be fabricated.

2 and 3 are cross-sectional views of a non-volatile memory element in accordance with another exemplary embodiment.

As shown in FIG. 2, the non-volatile memory element includes a first electrode 120 and a second electrode 180 which are respectively spaced apart and disposed on the substrate 110; The first conductive organic layer 130 and the second conductive organic layer 160 are electrically connected between the first electrode 120 and the second electrode 180; the nanocrystalline layer 140 has an oxidized surface and is uniformly distributed to the first conductive organic layer 130 to Between the second conductive organic layer 160; a buffer layer 150 between the nanocrystalline layer 140 and the second conductive organic layer 160.

As shown in FIG. 3, the non-volatile memory device includes a first electrode 120 and a second electrode 180 which are respectively spaced apart and disposed on the substrate 110. The first conductive organic layer 130 and the second conductive organic layer have bistable conductivity. The layer 160 is between the first electrode 120 and the second electrode 180; the nanocrystal layer 140 includes a nanocrystal 141 having an oxidized surface, and is uniformly distributed between the first conductive organic layer 130 to the second conductive organic layer 160. a buffer layer 170 between the second conductive organic layer 160 and the second electrode 180. The non-volatile memory element includes a nanocrystal layer 140 between the first electrode 120 and the second electrode 180. Furthermore, the material layer between the first electrode 120 and the nanocrystal layer 140 and the material layer between the nanocrystal layer 140 and the second electrode 180 are prepared asymmetrically with each other. In other words, the first conductive organic layer 130 is prepared between the first electrode 120 and the nanocrystal layer 140, and at least one of the second conductive organic layer 160 and the buffer layer 150 and the buffer layer 170 is prepared. The rice crystal layer 140 is between the second electrode 180. The buffer layer 150 and the buffer layer 170 promote charge injection and transfer to the nanocrystal layer 140 in the forward bias, and act as a barrier in the reverse bias to suppress charge transfer. Once the buffer layer 150 and the buffer layer 170, which allow the memory element to perform the selection function, are prepared, the memory can provide a storage unit in which the storage unit has a selection function without additional selection elements such as diodes.

Special modifications according to various modifications of non-volatile memory elements will be described hereinafter. Sex.

(Experiment 1) The non-volatile organic memory element includes first and second buffer layers.

A 80 nm first electrode (aluminum, Al), a 35 nm first conductive organic layer (hydroxyquinolinyl aluminum, Alq ₃ ), and 20 nm nanocrystals (nickel, Ni) were stacked on a tantalum substrate. 0.2 nm first buffer layer (lithium fluoride, LiF), 45 nm second conductive organic layer (hydroxyquinolinyl aluminum, Alq ₃ ), 0.6 nm second buffer layer (lithium fluoride, LiF) and a second electrode of 80 nm (aluminum, Al) to make non-volatile memory components. Here, the oxygen plasma treatment of nickel permeation takes 300 seconds to form a nanocrystal layer.

4 is a characteristic diagram of current-voltage (ampere-volt) of a non-volatile memory element according to Experiment 1. Fig. 5 is a graph showing the retention characteristics of a non-volatile memory element according to Experiment 1. Fig. 6 is a graph showing the endurance characteristics of a non-volatile memory stylized and erased memory according to Experiment 1.

As shown in FIG. 4, when the first electrode and the second electrode are respectively connected to the anode and the cathode to apply a forward bias and continue to increase in size, the memory element has a high resistance state, that is, an off state Ioff (where the current is Exponentially and slowly increase until the first level voltage, that is, the threshold voltage Vth). Then, when a voltage higher than the threshold voltage Vth is applied, the current is drastically increased. Until the second potential is Vp, the current increases as the voltage increases. However, in the negative differential resistance region (NDR), after the second level voltage Vp, a current reduction occurs. Then, after the passage of the NDR region, when the applied voltage is higher than the third voltage Ve, the current increases as the voltage increases. For example, when the first electrode is connected to the anode and the second electrode is connected to the cathode, to continuously increase the forward bias to about 8 volts and apply it, at the limit When the voltage Vth is about 2.1 volts, the amount of current increases. Furthermore, from the threshold voltage Vth to the voltage Vp of about 3.4 volts, as the voltage increases, the current continuously increases and reaches a maximum value. Thereafter, until the voltage Ve is about 5 volts, as the voltage increases, the current decreases, that is, the NDR region appears. Then, after the voltage Ve is about 5 volts, the current increases as the voltage increases.

Through this phenomenon, the voltage range of stylization, erasing, and reading operations can be set to non-volatile memory components. For example, the read operation is performed when the voltage is lower than the threshold voltage Vth, and the program operation is performed when the voltage is between the threshold voltage Vth and the voltage Ve of the NDR region, and the erase operation is performed under the voltage Ve exceeding the NDR region. carried out. Thus, the non-volatile memory element performs a read operation when the voltage is less than about 2.1 volts; performs a stylized operation between about 2.1 volts to about 5 volts; (approximately 3.4 volts), and The erase operation is performed with a voltage exceeding approximately 5 volts. Further, the memory element can be programmed by applying a voltage of the NDR region between the second level voltage Vp and the third level voltage Ve. In this case, the current of the memory element when the voltage is programmed in the NDR region is lower than the on-current Ion when the memory cell is programmed at the second level voltage Vp, and is higher than the off current Ioff. Therefore, multi-level stylization can be achieved.

In addition, as shown in FIG. 4, the stylized voltage Vp is applied to the non-volatile memory element to be programmed, and then the forward bias is again increased to about 8 volts and applied, since the charge is charged in the nanocrystal layer, the memory The body element has a low resistance state, that is, a state in which the current Ion is turned on, in which the current is increased compared to before. However, the ratio of the on current Ion to the off current Ioff is about 8.4 × 10 ² . Also, when the first electrode is connected to the cathode and the second electrode to the connection anode to continue to increase the reverse bias, the current slowly increases as the voltage increases at a negative position.

Regarding the non-volatile memory element, current flow is not charged when the electrons are not charged in the nanocrystal layer 140 due to the energy difference between the first conductive organic layer 130 and the second conductive organic layer 160. It can be slightly increased at a predetermined voltage level, but when the voltage applied across the conductive organic layer 130 and the conductive organic layer 160 is higher than the threshold voltage Vth, the current flow is drastically increased while the electrons are in the nanometer. The crystal layer 140 is charged. Therefore, the non-volatile memory element is maintained in a high resistance state and a low resistance state. Also, when electrons are charged in the nanocrystal layer 140, the current flow becomes tens or thousands of times larger than when the electrons are not charged. Since the first buffer layer 150 and the second buffer layer 170 are prepared, electron injection is promoted when the forward bias is applied and is higher than the threshold voltage Vth, so that the stylized voltage is lowered. Furthermore, when a reverse bias is applied, a sharp increase in current can be prevented by limiting electron transfer.

Fig. 5 is a graph showing the retention characteristics of a non-volatile memory element according to Experiment 1. Comparing change A and change B, wherein change A is based on the application of about 3 volts after staging, when a read voltage of 1 volt is applied, and the current Ion is applied; wherein the change B is based on the application of about 10 volts after erasing, when The reading voltage is applied at 1 volt and the current Ioff is turned off. As shown in FIG. 5, it is observed that there is a large current difference between the on current Ion and the off current Ioff. At this time, the on/off current ratio Ion/Ioff is about 2.7 × 10 ² .

In addition, FIG. 6 is a tolerance cycle diagram based on the stylization and erasing amount of the non-volatile memory element according to Experiment 1. It can be observed that there is a big difference between the change A and the change B, wherein the change A is based on the applied voltage of 3 volts after stylization, when the read voltage is applied 1 volt, the number of stylized; wherein the change B is 10 volts according to the applied voltage After erasing, when applying a read voltage of 1 volt, erase the amount. At this time, the on/off current ratio, Ion/Ioff, is about 0.33 × 10 ² .

From this result, it can be observed that, according to the non-volatile memory element of the exemplary embodiment, the first conductive organic layer, the nanocrystal layer, the first buffer layer, the second conductive organic layer, and the second buffer layer are stacked on the first electrode Between the second electrode and the second electrode, it has a low program voltage, an erase voltage, and a read voltage, and has an excellent on/off current ratio Ion/Ioff and excellent data retention and endurance properties. Therefore, the present invention can implement a non-volatile memory element having the above excellent properties.

(Experiment 2) Fabrication of non-volatile memory components on a flexible substrate

80 nm of the first electrode (aluminum, Al), 35 nm of the first conductive organic layer (quinolinyl aluminum, Alq ₃ ), 20 nm of naphthalene were stacked on a polyether sulphones (PES) film. Crystal of rice (nickel, Ni), first buffer layer of 0.2 nm (lithium fluoride, LiF), second conductive organic layer of 45 nm (arqolin aluminum, Alq ₃ ), O.6 nm A second buffer layer (lithium fluoride, LiF) and a second electrode of 80 nm (aluminum, Al) were used to make a non-volatile memory element.

Figure 7 is a graph of current-voltage (ampere-volt) characteristics of a non-volatile memory element according to Experiment 2. Fig. 8 is a graph showing the retention characteristics of a non-volatile memory element according to Experiment 2. Fig. 9 is a characteristic diagram according to the number of bends.

As shown in FIG. 7, when the first electrode and the second electrode are respectively connected to the anode and the cathode to apply a forward bias and sequentially increase the size thereof, the memory element has a high resistance state, that is, an off state Ioff (where the current is indexed) Ground and slowly increase to a threshold voltage Vth of about 2.9 volts). Then, when a voltage of about 2.9 volts above the threshold voltage Vth is applied, as the voltage increases, the current increases until about 4.0 volts. Thereafter, a reduced current NDR region occurs. Then, when the voltage becomes a voltage Ve higher than about 6.2 volts after passing through the NDR region, the current increases again as the voltage increases. Thus, a voltage of less than about 2.9 volts is used as the read voltage; about 2.9 volts to about 6.2 volts, which is about 4.0 volts, can be used as a stylized voltage; and a voltage of more than about 6.2 volts is used as a wipe. In addition to voltage. When a voltage is applied to the memory element, wherein the memory element is programmed by applying an operating voltage, for example, about 4.0 volts, the current is drastically increased and then becomes the state of the on current Ion. The on/off current ratio Ion/Ioff of the memory element is about 0.38 x 10 ² , which is lower than the non-volatile memory element formed on the germanium substrate in FIG. However, since the operating voltage is not greatly increased, the memory element operates as an excellent one. Further, when the reverse bias is applied and sequentially increased, the current is drastically increased in the initial state. However, as the voltage increases in the positive direction, the current slowly increases.

In addition, as shown in FIG. 8, the change A and the change B have a large current difference, wherein the change A is about 4 volts according to the applied voltage to be stylized, and when the read voltage is applied, the volt current is 1 volt; It is a shutdown current Ioff when a read voltage of 1 volt is applied after erasing according to an applied voltage of 8 volts. At this time, the on/off current ratio, Ion/Ioff is about 0.5 × 10 ² .

Fig. 9 is a characteristic diagram according to the number of bends. In order to measure the bending property, a flexible member having a width of 40 nm was bent to have an interval of about 25 mm at one end and the other end thereof, and then the on current Ion and the off current Ioff were measured according to the number of bends.

As shown in FIG. 9, when the change A is compared to the change B, wherein the change A is a stud according to an applied voltage of about 4 volts, the number of bends when the read voltage is applied at 1 volt; wherein the change B is according to the applied voltage 8 After the volt is erased, when the number of bends of the read voltage of 1 volt is applied, even if the number of bends increases, the on current Ion and the off current Ioff maintain a large difference. At this time, the current ratio is turned on/off, and Ion/Ioff is about 1.0 × 10 ² .

(Experiment 3) Non-volatile memory components only include the first buffer layer

A 80 nm first electrode (aluminum, Al), a 35 nm first conductive organic layer (quinolinyl aluminum, Alq ₃ ), a 20 nm nanocrystal (nickel, Ni), 0.2 nm of the first buffer layer (lithium fluoride, LiF), 45 nm of the second conductive organic layer (quinolinyl aluminum, Alq ₃ ) and 80 nm of the second electrode (aluminum, Al) to make non- Volatile memory components. Here, the oxygen plasma treatment of nickel permeation takes 300 seconds to form a nanocrystal layer. In other words, Experiment 1 was the same as Experiment 2 except that the second buffer layer was not formed.

Fig. 10 is a graph showing the current-voltage characteristics of a non-volatile memory element according to Experiment 3. In other words, Fig. 10 shows a current-voltage characteristic diagram of a memory element including a first buffer layer between the nanocrystal layer and the second conductive organic layer.

As shown in FIG. 10, when the first electrode and the second electrode are respectively connected to the anode and the cathode to apply a forward bias and sequentially increase the size thereof, the memory element has a high resistance state, that is, an off state Ioff (where the current is Increase exponentially and slowly until the threshold voltage Vth is about 2.1 volts). Then, when a voltage of about 2.1 volts higher than the threshold voltage Vth is applied, the current is drastically increased. As the voltage increases, the current increases until it is about 3.6 volts. Thereafter, the NDR area where current reduction occurs area. Then, when the voltage becomes a voltage Ve higher than about 5.4 volts after passing through the NDR region, the current increases again as the voltage increases. Further, when a voltage is applied to the memory element, wherein the memory element is programmed by applying about 3.9 volts, the memory element has a conduction current Ion state in which the current is drastically increased. In addition, as the reverse bias voltage increases accordingly, the current increases somewhat at a predetermined voltage, but increases slowly as a whole.

(Experiment 4) Non-volatile memory components only include the second buffer layer

A 80 nm first electrode (aluminum, Al), a 35 nm first conductive organic layer (quinolyl aluminum, Alq ₃ ), and a 20 nm nanocrystal (nickel, Ni) were stacked on a tantalum substrate. , a 45 nm second conductive organic layer (quinolyl aluminum, Alq ₃ ), a 0.6 nm second buffer layer (lithium fluoride, LiF), and a 80 nm second electrode (aluminum, Al) are manufactured. Non-volatile memory components.

Figure 11 is a graph showing the current-voltage characteristics of a non-volatile memory element according to Experiment 4. In other words, Fig. 10 shows a current-voltage characteristic diagram of a memory element including a second buffer layer between the second conductive organic layer and the second electrode. In other words, as shown in FIG. 11, when a forward bias is applied and the voltage is sequentially increased, the memory element has a high resistance state, that is, an off state Ioff (wherein the current increases exponentially and slowly until the threshold voltage Vth is about 2.1 volts). Then, when a voltage of about 2.1 volts higher than the threshold voltage Vth is applied, the current is drastically increased. Up to about 3.5 volts, as the voltage increases, the current increases. Thereafter, a reduced current NDR region occurs. Then, when the voltage becomes a voltage Ve higher than about 7.1 volts after passing through the NDR region, the current increases again as the voltage increases. In addition, when a voltage of about 3.5 volts is applied to the memory device to program it, the memory device has a conduction current Ion state in which the current is severe increase. Furthermore, as the reverse bias continues to increase, the current slowly increases.

(Experiment 5) The organic memory element includes a first buffer layer and a second buffer layer having the same thickness.

A 80 nm first electrode (aluminum, Al), a 35 nm first conductive organic layer (quinolinyl aluminum, Alq ₃ ), a 20 nm nanocrystal (nickel, Ni), 0.6 nm first buffer layer (lithium fluoride, LiF), 45 nm second conductive organic layer (quinolyl aluminum, Alq ₃ ), 0.6 nm second buffer layer (lithium fluoride, LiF) And a second electrode of 80 nm (aluminum, Al) to make a non-volatile memory component.

Figure 12 is a graph showing current-voltage characteristics of a non-volatile memory element according to thickness variation according to Experiment 5.

As shown in FIG. 12, when the forward bias is sequentially increased, the memory element has a high resistance state, that is, an off state Ioff (wherein the current increases exponentially and slowly until the threshold voltage Vth is about 2.1 volts). Then, when a voltage of about 2.1 volts higher than the threshold voltage Vth is applied, the current is drastically increased. Then, as the voltage increases, the current increases to about 4.0 volts, and then the current decreases in the NDR region. Then, when the voltage becomes a voltage Ve higher than about 5.7 volts after passing through the NDR region, the current increases again as the voltage increases. Further, when a voltage is applied to the memory element, wherein the memory element is programmed by applying about 4.0 volts, the memory element has a conduction current Ion state in which the current is drastically increased. In addition, as the reverse bias increases, the current increases dramatically. However, as the reverse bias increases again, the current slowly increases.

Even if the first buffer layer and the second buffer layer have the same thickness, it can be observed that the operational characteristics of the memory element are not greatly changed.

(Experiment 6) Preparation of non-volatile organic memory cells using quinolyllithium (Liq) Pieces.

A 80 nm first electrode (aluminum, Al), a 35 nm first conductive organic layer (quinolyl aluminum, Alq ₃ ), and a 20 nm nanocrystal (nickel, Ni) were stacked on a tantalum substrate. , 0.2 nm first buffer layer (lithium fluoride, LiF), 45 nm second conductive organic layer (quinolyl aluminum, Alq ₃ ), 0.6 nm second buffer layer (lithium fluoride, LiF And a second electrode of 80 nm (aluminum, Al) to make a non-volatile organic memory element.

Figure 13 is a graph showing the current-voltage characteristics of a non-volatile memory element according to Experiment 6. As shown in FIG. 13, when the forward bias is sequentially increased and then applied thereafter, the memory element has a high resistance state, that is, an off state Ioff (its current increases exponentially and slowly until the threshold voltage Vth is about 2.2 volts). Then, when a voltage of about 1.1 volts higher than the threshold voltage Vth is applied, the current is drastically increased. Then, as the voltage increases, the current increases to about 3.5 volts, and then the current decreases in the NDR region. Then, when the voltage becomes higher than about 6.2 volts Ve after passing through the NDR region, the current increases again as the voltage increases. Further, when a voltage is applied to the memory element, wherein the memory element is programmed by applying about 3.5 volts, the memory element has a conduction current Ion state in which the current is drastically increased. Moreover, after the memory component is programmed by applying about 4.5 volts and about 5.5 volts, that is, the voltage of the NDR region, then the same voltage is applied again, which has the state of the intermediate currents Iint1 and Iint2, which is lower than the conduction. The current Ion is higher than the off current Ioff. In other words, when a predetermined voltage is applied to program the memory element to perform a read operation, a current flow higher than the off current Ioff can be observed. Therefore, multi-step programming based on the stylized voltage can be realized. In addition, when a reverse bias is applied, the current is at a predetermined time. There is a large change in voltage, but it slowly increases and flows.

Figure 14 is a data retention characteristic diagram of a non-volatile memory element according to Experiment 6. The change A, the change B, the change C, and the change D are compared with each other, wherein the change A is a time when the on-current Ion is applied when the read voltage is 1 volt after the application of about 3.5 volts is applied; the change B is based on the application 8 volts after erasing, the time to turn off the current Ioff when a read voltage of 1 volt is applied; and the changes C and D are based on the application of about 4.5 volts and about 5.5 volts respectively after stylization, when a read voltage of 1 volt is applied The time between the intermediate currents Iint1 and Iint2. As shown in FIG. 14, as time passes, the on current Ion, the off current Ioff, and the predetermined data of the intermediate currents Iint1 and Iint2 are observed to maintain a large difference.

When quinolinyllithium is used as the material of the first buffer layer and the second buffer layer, similar operational characteristics are shown.

As described above, after a stylized voltage or an erase voltage is applied between the first electrode 110 and the second electrode 180 to have a predetermined potential difference, the non-volatile memory element is charged in the nanocrystal layer 140 by electric charge or Discharge to perform a program or erase operation. Furthermore, when a read voltage is applied, the non-volatile memory element detects a stylized or erased state based on the charge stored in the nanocrystal layer 140. The driving method of such a non-volatile memory element is as follows.

15 is a schematic diagram of a method of driving a non-volatile memory component, in accordance with an illustrative embodiment. In other words, the schematic diagram of FIG. 15 shows a non-volatile memory element stylization method, an erase method, and a reading method.

As shown in FIG. 15, the non-volatile memory element includes a plurality of first conductive lines 10 including 11, 12, and 13 extending in the same direction and spaced apart from each other by a predetermined interval; a plurality of second conductive lines 20 including 21, 22, and 23 extending perpendicular to the first conductive line 10 and spaced apart from each other by a predetermined interval; and a plurality of memory cells 30 disposed on the first conductive lines 10 and The intersection between the two conductive lines 20. In addition, as described above, the storage unit 30 includes at least one of the first electrode 120, the first conductive organic layer 130, the nanocrystal layer 140, the second conductive organic layer 160, the first buffer layer 150, and the second buffer layer 170. First, and the second electrode 180. Here, the first electrode 120 and the second electrode 180 are part of the first conductive line 10 and the second conductive line 20. According to the present embodiment, the stylizing operation, the reading operation, and the erasing operation are performed at potential differences of about 4 volts, about 1 volt, and about 7 volts, respectively. In other words, a method of driving a non-volatile memory element will be described.

In order to select and program the storage unit 31 where the first conductive line 12 and the second conductive line 22 intersect, about 2 volts is applied to the first conductive line 12 passing through the storage unit 31 and about -2 volts is applied to the storage unit 31. The second conductive line 22. Further, about 2 volts is applied to the first conductive line 11 and the first conductive line 13 which are not connected to the memory unit 31, and about 2 volts is applied to the second conductive line 21 and the second conductive line 23. Thus, the selected memory cell 31 between the first conductive line 12 and the second conductive line 22 produces a potential difference of 4 volts to program the memory cell 31 and produce about 0 volts or about -4 in other memory cells. The potential difference of volts. However, since the storage unit 30 includes at least one of the first buffer layer 150 and the second buffer layer 180, charge injection is promoted when a forward bias is applied, and charge transfer is suppressed when a reverse bias is applied. Therefore, other storage cells than the selected storage unit 10 are applied with a reverse bias of about -4 volts and cannot be programmed.

Further, for the reading operation of the storage unit 31, about 0.5 volts is applied The first conductive line 12 of the storage unit 31 is applied with about -0.5 volts to the second conductive line 22 that passes through the storage unit 31. Further, about -0.5 volts is applied to the first conductive line 11 and the first conductive line 13 which are not connected to the memory unit 31, and about 0.5 volts is applied to the second conductive line 21 and the second conductive line 23. Therefore, the selected memory cell 31 between the first conductive line 12 and the second conductive line 22 generates a potential difference of 1 volt to read the state of the memory cell 31, and generates about 0 volts or about -1 in other memory cells. The potential difference of volts. However, since the storage unit 30 includes at least one of the first buffer layer 150 and the second buffer layer 180, it promotes charge injection when a forward bias is applied, and suppresses charge transfer when a reverse bias is applied. The barrier, except for the selected storage unit 31, applies a reverse bias of about -1 volt and cannot be read.

Further, for the erase operation of the storage unit 31, about 3.5 volts is applied to the first conductive line 12 passing through the storage unit 31 and about -3.5 volts is applied to the second conductive line 22 passing through the storage unit 31. Further, about -3.5 volts is applied to the first conductive line 11 and the first conductive line 13 which are not connected to the memory unit 31, and about 3.5 volts is applied to the second conductive line 21 and the second conductive line 23. Thus, the selected memory cell 31 between the first conductive line 12 and the second conductive line 22 produces a potential difference of 7 volts to erase the memory cell 31 and produces about 0 volts or about -7 volts in other memory cells. The potential difference. However, since the storage unit 30 includes at least one of the first buffer layer 150 and the second buffer layer 180, it promotes charge injection when a forward bias is applied, and suppresses charge transfer when a reverse bias is applied. The barrier, except for the selected storage unit 31, applies a reverse bias of about -7 volts and cannot be erased.

Moreover, an embodiment of the present invention and its modifications are descriptions A non-volatile memory cell, wherein the first material layer is formed asymmetrically with the second material layer, wherein the first material layer is between the first conductive layer electrode 110 and the nano crystal layer 140, and the second material The layer is between the nanocrystal layer 140 and the second conductive layer electrode 180. In other words, the first material layer is formed by the first conductive organic layer 130, and the second material is formed by stacking the second conductive organic layer 160 and at least one of the first buffer layer 150 and the second buffer layer 170. . However, as shown in FIGS. 16 to 18. The non-volatile memory element includes a first material layer between the first conductive layer electrode 110 and the nano crystal layer 140, and the non-volatile memory element is composed of a first conductive organic layer 130 and a third buffer layer 152 At least one of the four buffer layers 172 is formed. In other words, as shown in FIG. 16, the first conductive layer 120, the fourth buffer layer 172, the first conductive organic layer 130, the third buffer layer 152, the nano crystal layer 140, and the second conductive layer may be stacked on the substrate 110. The organic layer 160 and the second conductive layer electrode 180. In addition, as shown in FIG. 17, the first conductive layer 120, the fourth buffer layer 172, the first conductive organic layer 130, the nano crystal layer 140, the second conductive organic layer 160, and the second conductive layer may be stacked on the substrate 110. Layer electrode 180. Furthermore, as shown in FIG. 18, the first conductive layer 120, the fourth buffer layer 172, the first conductive organic layer 130, the third buffer layer 152, the nano crystal layer 140, and the second conductive layer may be stacked on the substrate 110. The organic layer 160 and the second conductive layer electrode 180. Here, the third buffer layer 152 and the fourth buffer layer 172 of the same thickness may be formed, but the fourth buffer layer 172 thicker than the third buffer layer 152 may be formed.

Further, at least one buffer layer may be formed in the first material layer, and at least one buffer layer may be formed in the second material layer. In other words, as shown in FIG. 19, the first material layer may include a third buffer layer 152 and a fourth buffer layer 172, and The second material layer may include a first buffer layer 150 and a second buffer layer 170. Further, as shown in FIG. 20, the first material layer may be formed including the third buffer layer 152, and the second material layer may be formed including the second buffer layer 170.

As described above, according to the present invention, at least one buffer layer is formed between at least one first material layer between the first electrode 120 and the nanocrystal layer 140, and between the nanocrystal layer 140 and the second electrode 180. Two layers of material whereby charge injection is promoted in the forward bias and charge transfer is suppressed in the reverse bias.

Hereinafter, different manufacturing methods of non-volatile memory elements are described below in accordance with the present invention.

21 through 25 are continuous cross-sectional views of a method of fabricating a non-volatile memory device, in accordance with an exemplary embodiment. In other words, the cross-sectional view shows a manufacturing method in which the nanocrystal layer is passed through an oxidation process.

As shown in FIG. 21, the first electrode 120 and the first conductive organic layer 130 are formed on the substrate 110. Here, the substrate 110 may be a conductive substrate, an insulating substrate, or a semiconductor substrate, or may be a flexible substrate. Further, when a conductive substrate is used, it is necessary to form an insulating layer thereon. At this time, the insulating layer may include an oxide layer or a nitride layer. Further, the first electrode 120 may use all materials having conductivity, or a material having low electrical resistance and excellent interfacial properties for the conductive organic material. The first electrode 120 may use a metal such as aluminum (Al), titanium (Ti), zinc (Zn), iron (Fe), nickel (Ni), tin (Sn), lead (Pb), copper (Cu), and alloys thereof. . Then, a cleaning process is performed on the substrate 120 having the first electrode 120, and then ultraviolet and ozone treatment is performed thereon. At this time, the cleaning process may use an organic solvent such as isopropanol (IPA) and acetone. Further, under vacuum conditions, a plasma treatment can be performed on the cleaned substrate 110. Then, the first conductive organic layer 130 is formed by evaporating the organic material at a temperature of about 150 ° C to about 400 ° C, a pressure inside the chamber of about 10 ^-6 Pa to about 10 ^-3 Pa, and The deposition rate is from about 0.2 angstroms per second to about 2 angstroms per second. The first conductive organic layer 130 may be formed of quinolyl aluminum (Alq ₃ ), and may be formed to a thickness of about 20 nm to about 50 nm.

As shown in FIG. 22 and FIGS. 27(a) to 27(c), a nanocrystal layer 140 is formed on the first conductive organic layer 130. At this time, in order to make the nanocrystal layer 140 have a uniform thickness distribution of about 1 nm to about 30 nm, after the metal layer 140a is deposited on the first conductive organic layer 130, the oxygen plasma is passed through, and an oxidation process is performed thereon. To form a nanocrystal layer 140. Here, on the first conductive organic layer 130, a metal-deposited material such as nickel is at a temperature of about 800 ° C to about 1500 ° C, and a pressure inside the chamber is about 10 ^-6 Pa to about 10 ^-3 Pa. And a metal layer 140a having a thickness of from about 1 nm to about 30 nm is formed under conditions of a deposition rate of from about 0.1 Å/sec to about 2 Å/sec.

At this time, since the metal layer 140a has a high deposition rate, it cannot be formed in a nanocrystal shape, and a thin metal layer having grain boundaries is formed as shown in Fig. 26(A).

Next, the substrate 110 having the metal layer 140a is loaded into the chamber for oxidation. For example, by applying a radio frequency power source of about 50 watts to about 300 watts, a DC bias of about 100 volts to about 200 volts, and an oxygen injection of about 100 standard conditions in milliliters per minute (sccm) to about 200 standard conditions in milliliters per minute and a pressure of about 0.5. The oxidation process is carried out in the chamber at a condition of about 3.0 Pa. At this time, the process time is about 30 seconds to about 500 seconds.

As shown in Fig. 26(B), through this, the oxygen plasma penetrates into the metal layer 140a along the boundary, and the metal layer 140a oxidizes along the grain boundaries. As shown in Figure 26(C) It is shown that nanocrystals 141 having the same size are formed, and an insulating layer 142, that is, an amorphous layer, is formed on the surface thereof. At this time, the thickness of the nanocrystal layer 140 is formed to be about 1 nm to about 30 nm in accordance with the thickness of the metal layer 140a. Of course, even if a thick metal layer 140a can be formed, if the metal layer 140a is too thick (for example, more than about 50 nm), oxygen may not sufficiently penetrate into the grain boundaries of the metal layer 140a, so the nanocrystal layer 140 cannot be formed effectively. As shown in Fig. 26(D), after the oxidation process is completed, a nanocrystal layer 140 and a nickel oxide (NiO) insulating layer 142 surrounding it are provided.

Here, the deposition and oxidation process of the metal layer 140a may be performed multiple times to form the multilayer nanocrystal layer 140. At this time, according to the deposition thickness of the metal layer 140a, the multilayer nanocrystal layer 150 each having the same thickness or different thickness may be formed. It is effective that the nanocrystal layer 140 has a multilayer structure of one to ten layers of the same thickness.

As shown in FIG. 23, a first layer 150 is formed on the nanocrystal layer 140. The first buffer layer 150 may be formed by vacuum thermal deposition or spin coating, and may be, for example, lithium fluoride (LiF), sodium chloride (NaCl), cesium fluoride (CsF), lithium oxide (Li ₂ O), A material of BaO (yttria) and quinolinyl lithium (Liq) is formed. Here, the first buffer layer 150 is formed to have a thickness of about 0.1 nm to about 1 nm.

As shown in FIG. 24, a second conductive organic layer 160 is formed on the first buffer layer 150. At a temperature of from about 150 ° C to about 400 ° C, a pressure inside the chamber of from about 10 ^-5 Pa to about 10 ^-3 Pa, and a deposition rate of from about 0.2 Å / sec to about 2 Å / sec, by steaming An organic material is plated to form the second conductive organic layer 160. The second conductive organic layer 160 may be formed of Alq ₃ and may be formed to a thickness of about 20 nm to about 50 nm.

As shown in FIG. 25, a second buffer layer 170 is formed on the second conductive organic layer 160, and then a second electrode 180 is formed thereon. The second buffer layer 170 may be formed by a vacuum thermal deposition or a spin coating method, and may be, for example, lithium fluoride (LiF), sodium chloride (NaCl), cesium fluoride (CsF), lithium oxide (Li ₂ O), A material of barium oxide (BaO) and quinolinyl lithium (Liq) is formed. Here, the second buffer layer 170 may be formed to have a thickness of about 0.1 nm to about 1 nm, and may be thicker than the first buffer layer 150. Further, at a temperature of from about 1000 ° C to about 1500 ° C, a pressure inside the chamber of from about 10 ^-6 Pa to about 10 ^-3 Pa, and a deposition rate of from about 2 Å/sec to about 7 Å/sec, The second electrode 180 is formed of a vapor-deposited metal material. The second electrode 180 may be formed of aluminum and may be formed to a thickness of about 20 nm to about 150 nm.

Furthermore, each of the above layers can be formed in-situ in a vacuum atmosphere. In other words, the first electrode 120 and the second electrode 180, the first conductive organic layer 130 and the second conductive organic layer 160, the nanocrystal layer 140, the first buffer layer 150 and the second buffer layer 170 may be deposited in a single manner. Deposited in the system. For example, deposition can be performed in a single system in which a chamber is used to deposit a first electrode 120, a second electrode 180, and a metal layer 140a for the nanocrystal layer 140; a chamber for depositing the first conductive organic layer 130, The second conductive organic layer 160 and the first buffer layer 150 and the second buffer layer 170 use an organic layer; a chamber is used to generate plasma for oxidation; a cooling chamber; a load lock chamber and A shadow mask chamber, the chamber being coupled to a transfer module. In this case, when the substrate is transferred from the electrode deposition chamber to the deposition chamber for the organic layer, it can be transferred using a transfer module in a vacuum state that is not exposed to the air. Of course, the invention is not limited thereto. The chamber can be connected to different systems.

In the above description, the non-volatile memory element can be fabricated by a mask and vacuum evaporation without an etching process. However, the invention is not limited thereto. In other words, non-volatile memory components can be fabricated by different methods. In other words, in addition to the thermal evaporation process, it can be passed through an E-beam deposition process, a sputtering process, or a chemical vapor deposition process (CVD). ), metal organic chemical vapor deposition process (MOCVD), molecular beam epitaxy process (MBE), physical vapor deposition process (PVD) and atomic layer The electrode 120 and the electrode 280, the conductive organic layer 130 and the conductive organic layer 160, the nanocrystal layer 140, and the buffer layer 150 and the buffer layer 170 are formed by an Atomic Layer Deposition Process (ALD). In addition, the electrode 120 and the electrode 180, the conductive organic layer 130 and the conductive organic layer 160, and the buffer layer 150 and the buffer layer 170 may be formed on a unitary structure, and then formed into a shape through a patterning process. For example, after the conductive material is formed on the substrate 110, the first electrode 120 may be formed by removing photoconductive materials other than the first electrode 120 by photolithography and an etching process using a photomask. In addition, the oxidation process can be carried out by a wet and dry oxidation process.

According to the manufacturing method of the non-volatile memory element of the first embodiment, the first conductive organic layer 130 and the second conductive organic layer 160 are formed of a low molecular weight organic material such as quinolinyl aluminum (Alq ₃ ), and The metal layer is oxidized using oxygen plasma to form the nanocrystal layer 140. However, the first conductive organic layer 130 and the second conductive organic layer 160 may be formed of a high molecular weight material. In addition to the method of forming the nanocrystal layer 140 by depositing and oxidizing a metal layer, there are various methods such as a method of forming a nanocrystal layer surrounded by an insulating layer. Hereinafter, another embodiment of a method of manufacturing a non-volatile memory element in which the first conductive organic layer 130 and the second conductive organic layer 160 are formed using a high molecular weight material will be described. Also, the contents of the other embodiments are briefly described.

27(a) through 27(c) are successive cross-sectional views showing a method of fabricating a non-volatile memory element in accordance with another exemplary embodiment. This embodiment describes a method of manufacturing a non-volatile memory element in which a high molecular weight material is used to form a conductive organic layer, and a nanocrystal layer is formed through a deposition and curing process.

As shown in FIG. 27(A), the first electrode 120 is formed on the substrate 110. Then, a first conductive organic layer 130 is formed on the first electrode 120. Here, the first conductive organic layer 130 can be formed by a spin coating method using a polymer material such as PVK or PS.

As shown in FIG. 27(B), a first barrier layer 192, a metal layer 140a, a second barrier layer 194, and a second conductive organic layer 160 are sequentially formed on the first conductive organic layer 130. Here, in the nanocrystal layer, the first barrier layer 192 and the second barrier layer 194 serve as electron tunneling barriers surrounding the nanocrystals, which are completed by subsequent processes. The first barrier layer 192 and the second barrier layer 194 may be formed by an ALD process using a metal oxide such as nickel oxide (NiO), aluminum oxide (Al ₂ O ₃ ), and titanium oxide (TiO ₂ ). Further, the metal layer 140a may be formed of an oxidizable or non-oxidizable metal by a deposition method and formed to a thickness of about 1 nm to about 10 nm. Further, the second conductive organic layer 160 may be formed using a structure similar to the first conductive organic layer 130. For example, it can be formed by a spin coating method using a high molecular weight material such as PVK or PS.

As shown in FIG. 27(C), after the second conductive organic layer 160 is formed, a curing process is performed thereon. Through the curing process, the first barrier layer 192 on the metal layer 140 and the second barrier layer 194 under the metal layer 140 surround the metal nanocrystal layer 141 in the metal layer 140a. Therefore, the nanocrystal layer 140 is formed, and the nanocrystal layer 140 includes the nanocrystal 141 and the barrier 143 surrounding the nanocrystal 141. The curing process can be carried out at a temperature of about 150 ° C and about 300 ° C for about 0.5 to about 4 hours. After the nanocrystal layer 140 is formed, the second buffer layer 170 is formed on the second conductive organic layer 160, and then the second electrode 180 is formed on the substrate 100 having the second buffer layer 170.

In the method of fabricating the non-volatile memory device according to the second embodiment, the curing process is performed on the structures in which the first insulating layer 192, the metal layer 140a, and the second insulating layer 194 are sequentially stacked, thereby forming a surrounding structure including The nanocrystal layer 140 of the insulating layer 143 of the rice crystal layer 141, and the first conductive organic layer 130 and the second conductive organic layer 160 are formed of a high molecular weight material. A nanocrystal layer having a uniform size and distribution can be formed by the above method. Therefore, stable element characteristics can be obtained.

28(a) through 28(b) are successive cross-sectional views showing a method of fabricating a non-volatile memory element in accordance with another exemplary embodiment. That is, the cross-sectional view shows that the conductive organic layer and the nanocrystal layer are formed by depositing an organic material in which nanocrystals are dispersed.

As shown in FIG. 28(A), after the first electrode 120 is formed on the substrate 110, a conductive organic layer in which a plurality of nanocrystals 141 are dispersed is formed on the first electrode 120. 135. Here, the insulating layer 144 may be formed to surround the nanocrystal layer 141. A method of forming an organic material will be described with reference to FIG. 25 in which a nanocrystal 141 surrounded by an insulating layer 144 is interspersed. Further, the conductive organic layer 135 can be formed by a Rotation coating and a thermal treatment process. For example, the substrate 110 can be rotated by rotating the organic material dispersed with the nanocrystals 141 onto the substrate 110 while rotating at about 1,500 revolutions per minute (rpm) to about 3,000 revolutions per minute, and then at about 100 degrees Celsius to about 150 degrees. A heat treatment is performed at a temperature of about 30 minutes to about 90 minutes to form a conductive organic layer 135. Here, after the organic material is dropped, the substrate 110 may be further rotated for about 50 seconds to about 100 seconds to uniformly distribute the organic material.

As shown in FIG. 28(B), after the buffer layer 170 is formed on the conductive organic layer 135, the second electrode 180 is formed on the substrate 110.

According to the method of manufacturing the non-volatile memory element of the third exemplary embodiment, the insulating layer 144 surrounding each of the nanocrystals 141 serves as a tunneling barrier. Of course, the nanocrystal 141 can be disposed into the conductive organic layer 135 without forming the insulating layer 144. If the insulating layer 144 is formed to surround the nanocrystal 141, the reliability and durability of the element can be improved as compared with the case where the insulating layer 144 is not formed.

29(a) to 29(g) illustrate a method of forming the organic layer of Fig. 28(A). An organic material will be described as an example in which the organic material is interspersed with a nanocrystal having a barrier layer.

First, the operations in FIGS. 21(a) to 21(e) are performed to synthesize the nanocrystal 141 surrounded by the barrier layer 144.

In other words, as shown in Fig. 29 (e), an aqueous metal salt solution is prepared by dissolving a metal salt of tetrachloroauric acid (HAuCl ₄ ) in deionized water (DI water) of an aqueous solvent. At this time, the metal salt in the aqueous solution ionizes hydrogen ions (H ⁺ ) and tetrachloroaurate (AuCl ₄ ^- ) and serves as a source of gold (Au). Further, tetraoctyllammonium bromide (TOAB) was dissolved in toluene in a nonaqueous solvent to prepare a toluene solution including ionized tetraoctyl ammonium bromide. TOAB acts as a phase transfer catalyst for the transfer of AuCl ₄ ^- , that is, ions containing metals are moved to a toluene solution during subsequent processes.

Then, as shown in Fig. 29 (b), tetrachloroaurate (AuCl ₄ ^- ) (i.e., metal-containing ions) is transferred to a toluene solution by stirring an aqueous solution of the metal salt and a toluene solution in which TOAB is dissolved. Stirring can be performed at a speed of about 500 rpm or higher at this time.

A carbazole terminated thiol (CB) was added as a dispersion stabilizer to the toluene solution, which uniformly dispersed the subsequent gold nanocrystals, followed by stirring. At this time, stirring may be performed at room temperature for about 5 minutes to about 20 minutes. The molecular formula of CB (i.e., the dispersion stabilizer) is C23H31NS, and its chemical name is 11-carbazolyl dodecane thiol.

Then, as shown in FIG. 29(c), sodium borohydride (NaBH ₄ ) was added to the toluene solution to which CB of FIG. 29(b) was added, wherein the sodium borohydride (NaBH ₄ ) was used as The reducing agent of tetrachloroaurate (AuCl ₄ ^- ) is reduced, and then stirring is performed, and at this time, stirring can be performed at a temperature of about 500 rpm or more at room temperature for about 3 hours to about 10 hours.

As a result, as shown in Fig. 29 (d), a combined material of gold nanocrystals and CB was formed in a toluene solution. At this time, since CB is formed to surround the gold nanocrystal, CB acts as a stabilizer and also acts as a charge tunneling barrier similar to the barrier material.

Then, as shown in Fig. 29 (e), the toluene solution was evaporated, thereby leaving a combination of gold nanocrystals and CB. This evaporation can be carried out in a rotary evaporator at relatively low pressure conditions of about -1 barr or less.

Then, as shown in Fig. 29 (f), the combination of the gold nanocrystals and the CB was dissolved in chloroform. This is used to mix with polymer materials. PVK is mixed as a high molecular weight material (for example, PVK) with a chloroform solution.

Finally, as shown in Fig. 29(g), a final product solution is produced in which the gold nanocrystals surrounded by the CB are mixed with the polymer material. If the final product solution is spin-coated on the substrate, the conductive organic layer 135 shown in Fig. 28(A) is formed. In this exemplary embodiment, the nanocrystals 141 dispersed in the conductive organic layer 135 may be formed of gold, and the barrier 144 surrounding the nanocrystals 141 may be formed of CB.

Nanocrystals having a uniform size and distribution are formed by the method according to the third exemplary embodiment. In particular, the organic layer including the nanocrystals is formed at a time, the manufacturing process is simple, and mass production can be achieved.

While the invention has been illustrated and described with respect to the specific embodiments of the present invention, it will be understood by those skilled in the art Make a variety of forms and changes in detail.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 11, 12, 13‧‧‧ first conductive line

20, 21, 22, 23‧‧‧ second conductive line

30, 31‧‧‧ storage unit

110‧‧‧Substrate

120‧‧‧first electrode, first conductive layer electrode, first conductive layer, electrode

130‧‧‧First conductive organic layer, conductive organic layer

135‧‧‧ Conductive organic layer

140‧‧‧ nano crystal layer

140a‧‧‧metal layer

141‧‧N nm crystal

142‧‧‧Insulation, barrier layer

143‧‧‧Baffles, insulation

144‧‧‧Insulation

150‧‧‧First buffer layer, buffer layer

152‧‧‧ third buffer layer

160‧‧‧Second conductive organic layer, conductive organic layer

170‧‧‧Second buffer layer, buffer layer

172‧‧‧fourth buffer layer

180‧‧‧Second electrode, second conductive layer electrode, electrode

192‧‧‧ first barrier layer, first insulation

194‧‧‧ second barrier layer

Iint1, Iint2‧‧‧Intermediate current

Ioff‧‧‧ Turn off the current

Ion‧‧‧ conduction current

NDR‧‧‧negative differential resistance

Ve‧‧‧ erase voltage

Vp‧‧‧ stylized voltage

Vth‧‧‧ threshold voltage

1 is a cross-sectional view of a non-volatile memory element in accordance with an illustrative embodiment.

2 and 3 are cross-sectional views of a non-volatile memory element in accordance with another exemplary embodiment.

4 and 6 are characteristic diagrams of a non-volatile memory element according to Experiment 1.

7 and 9 are characteristic diagrams of a non-volatile memory element on a flexible substrate according to Experiment 2.

Figure 10 is a graph showing the current-voltage characteristics of a non-volatile memory element according to Experiment 3.

Figure 11 is a graph showing the current-voltage characteristics of a non-volatile memory element according to Experiment 4.

Figure 12 is a graph showing the current-voltage characteristics of a non-volatile memory element according to Experiment 5.

13 and 14 are characteristic diagrams of a non-volatile memory element according to Experiment 6.

15 is a schematic diagram of a method of driving a non-volatile memory component, in accordance with an illustrative embodiment.

16 and 18 are cross-sectional views of another non-volatile memory element, in accordance with another exemplary embodiment.

19 and 20 are cross-sectional views of still another non-volatile memory element, in accordance with another exemplary embodiment.

21 through 25 are continuous cross-sectional views of a method of fabricating a non-volatile memory device, in accordance with an exemplary embodiment.

26(a) to 26(d) are conceptual cross-sectional views showing a method of manufacturing a non-volatile memory element according to an exemplary embodiment.

27(a) to 27(c) are successive cross-sectional views showing a method of fabricating a non-volatile memory element in accordance with another exemplary embodiment.

28(a) to 28(b) are cross-sectional views showing a method of manufacturing a non-volatile memory element according to still another exemplary embodiment.

29(a) to 29(g) are continuous cross-sectional views showing a method of manufacturing a non-volatile memory element according to still another exemplary embodiment.

110‧‧‧Substrate

120‧‧‧first electrode

130‧‧‧Electrically conductive organic layer

140‧‧‧ nano crystal layer

141‧‧N nm crystal

142‧‧ ‧ barrier layer

150‧‧‧First buffer layer

160‧‧‧Electrically conductive organic layer

170‧‧‧Second buffer layer

180‧‧‧second electrode

Claims (24)

A non-volatile memory element comprising: a first electrode and a second electrode spaced apart from each other; at least one nano crystal layer disposed between the first electrode and the second electrode; and a first material layer and a second material a material layer disposed between the first electrode and the nanocrystal layer and disposed between the second electrode and the nanocrystal layer, the first material layer and the second material layer having bistable conductivity a property wherein the first material layer and the second material layer are formed asymmetrically with each other. The non-volatile memory component of claim 1, wherein the nanocrystal layer comprises a plurality of nanocrystals and a barrier layer, wherein the barrier layer surrounds the nanocrystals. The non-volatile memory component of claim 1, wherein the first material layer comprises at least one conductive organic layer, and the second material layer comprises at least one conductive organic layer and at least one buffer layer. The non-volatile memory component of claim 3, wherein the conductive organic layers have different thicknesses. The non-volatile memory component of claim 4, wherein at least one of the conductive organic layers comprises a low molecular weight material, wherein the low molecular weight material has charge transfer characteristics. The non-volatile memory device of claim 5, wherein at least one of the conductive organic layers is composed of Alq ₃ , AIDCN, α-NPD, PtOEP, TPD, ZnPc, CuPc, C60, PBD, At least one of CBP, Pentacene, Balq, and PCBM is formed. The non-volatile memory device of claim 3, wherein the second material layer comprises at least one of a first buffer layer and a second buffer layer, wherein the first buffer layer is in the nano-buffer layer Between the rice crystal layer and the conductive organic layer of the second material layer, and the second buffer layer is between the conductive organic layer of the second material layer and the second electrode. The non-volatile memory component of claim 7, wherein the first buffer layer and the second buffer layer comprise a metal compound of a metal, wherein the metal has a small work function. The non-volatile memory component of claim 8, wherein the first buffer layer or the second buffer layer comprises a metal compound of an alkali metal or an alkaline earth metal. The non-volatile memory element of claim 8, wherein the first buffer layer or the second buffer layer is formed of at least one of LiF, NaCl, CsF, Li ₂ O, BaO, and Liq. The non-volatile memory component of claim 7, wherein the first buffer layer and the second buffer layer have different thicknesses. The non-volatile memory device of claim 3, wherein the buffer layer is promoted in a forward bias when a high voltage and a low voltage are applied to the first electrode and the second electrode, respectively. The charge transfer inhibits charge transfer in the forward bias voltage when a low voltage and a high voltage are applied to the first electrode and the second electrode, respectively. The non-volatile memory component as recited in claim 1 further includes: a threshold voltage region, wherein the amount of current increases sharply according to a potential difference applied between the first electrode and the second electrode; and a negative differential resistance region, wherein the negative differential resistance region The current decreases as the potential difference applied between the first electrode and the second electrode increases. The non-volatile memory device of claim 13, wherein a read operation is performed at a first voltage level lower than a threshold voltage; and the threshold voltage is applied to the differential resistance region a second voltage level, performing a stylization operation; and performing a erase operation at a third voltage level greater than the second voltage level. The non-volatile memory component of claim 14, wherein the non-volatile memory component is multi-level programmed according to the second voltage level. A non-volatile memory component includes: a first electrode and a second electrode spaced apart from each other; at least one nanocrystal layer disposed between the first electrode and the second electrode; a first conductive organic layer and a second a conductive organic layer disposed between the first electrode and the nanocrystal layer and disposed between the second electrode and the nanocrystal layer, the first material layer and the second material layer having a bistable state Conductive properties; and at least one buffer layer disposed between the first electrode and the second electrode Wherein, when a high voltage and a low voltage are respectively applied to the first electrode and the second electrode, the buffer layer promotes charge transfer in a forward bias, when a low voltage and a high voltage are respectively applied to the first The buffer layer suppresses charge transfer in the forward bias voltage when the electrode and the second electrode are used. The non-volatile memory component of claim 16, wherein the nanocrystal layer comprises a plurality of nanocrystals and a barrier layer, wherein the barrier layer surrounds the nanocrystals. The non-volatile memory device of claim 16, wherein the first conductive organic layer and the second conductive organic layer are formed of a low molecular weight material, wherein the low molecular weight material has charge transfer characteristics. The non-volatile memory component of claim 18, wherein the non-volatile memory component, wherein at least one of the first conductive layer and the second conductive organic layer is composed of Alq3, AIDCN, and α-NPD , PtOEP, TPD, ZnPc, CuPc, C60, PBD, CBP, Pentacene, Balq and PCBM formed. The non-volatile memory device of claim 16, wherein the second conductive organic layer is thicker than the first conductive organic layer. The non-volatile memory device of claim 16, wherein the buffer layer is prepared between the first electrode or the second electrode and the first organic layer or the second organic layer or at the first conductive Between the organic layer or the second conductive organic layer and the nanocrystalline layer. The non-volatile memory element of claim 21, wherein the buffer layer comprises a metal compound of an alkali metal or an alkaline earth metal. The non-volatile memory component of claim 21, wherein the buffer layer comprises a metal-based metal compound, wherein the metal has a small work function. The non-volatile memory element of claim 23, wherein the buffer layer comprises at least one of LiF, NaCl, CsF, Li ₂ O, BaO, and Liq.