TW201405587A - Element for conductive film, conductive film laminated body, electronic equipment, and method of manufacturing element for conductive film and conductive film laminated body - Google Patents
Element for conductive film, conductive film laminated body, electronic equipment, and method of manufacturing element for conductive film and conductive film laminated body Download PDFInfo
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Abstract
Description
本發明係有關於一種導電膜用素材、導電膜積層體、電子機器、以及導電膜用素材及導電膜積層體之製造方法。 The present invention relates to a material for a conductive film, a conductive film laminate, an electronic device, a material for a conductive film, and a method for producing a conductive film laminate.
透明導電膜具有導電性及光學透明性,因此可作為透明電極、電磁波遮蔽膜、面狀發熱膜及抗反射膜等使用,近年以觸控面板用電極備受注目。觸控面板存在多樣方式如電阻膜式、靜電容結合式、光學式等。透明導電膜可使用在例如以上下電極接觸來特定觸控位置的電阻膜式、及感應靜電容變化的靜電容結合方式。使用於電阻膜式的透明導電膜在動作原理上係透明導電膜彼此機械性地接觸,因此被要求具有高耐久性。又,使用於靜電容結合方式或一部分的電阻膜式之透明導電膜係藉由蝕刻形成多數個透明電極以成為特定圖案,因此被要求具有良好的蝕刻性。又,透明導電膜係配置在顯示部之前面,因此被要求具有高光穿透率。 Since the transparent conductive film has electrical conductivity and optical transparency, it can be used as a transparent electrode, an electromagnetic wave shielding film, a planar heat generating film, and an antireflection film. In recent years, electrodes for touch panels have attracted attention. There are various ways for the touch panel such as a resistive film type, a static capacitance combined type, an optical type, and the like. As the transparent conductive film, for example, a resistive film type in which a touch position is contacted by the lower electrode described above, and a capacitive coupling method in which a change in electrostatic capacitance is induced can be used. The transparent conductive film used in the resistive film type is mechanically in contact with each other in the principle of operation, and thus is required to have high durability. Further, since the transparent conductive film of the resistive film type or a part of the resistive film type is formed by etching to form a plurality of transparent electrodes to have a specific pattern, it is required to have good etching properties. Further, since the transparent conductive film is disposed on the front surface of the display portion, it is required to have high light transmittance.
作為透明導電膜,可舉如由銦錫氧化物所構成者。藉由使銦錫氧化物結晶化,可提升耐久性。但,有時在成為透明導電膜的銦錫氧化物會藉由蝕刻形成多數個透明電極,一旦結晶化,即難以藉由蝕刻形成多數個透明電極。例如,當銦錫氧化物結晶化時,蝕刻率會降低,因而有透明電極之形成耗費時間或透明電極之形狀無法成為期望形狀之虞。 The transparent conductive film may be composed of indium tin oxide. Durability can be improved by crystallizing indium tin oxide. However, indium tin oxide which is a transparent conductive film may form a plurality of transparent electrodes by etching, and once crystallized, it is difficult to form a plurality of transparent electrodes by etching. For example, when indium tin oxide is crystallized, the etching rate is lowered, so that formation of a transparent electrode takes time or the shape of the transparent electrode cannot become a desired shape.
自上述觀點看來,首先將易於蝕刻的非晶質狀態之銦錫氧化物成膜,對該非晶質狀態之銦錫氧化物進行蝕刻形成多數個透明電極後,再以熱處理使其結晶化為佳。此時,針對非晶質狀態之銦錫氧化物會要求易於以熱處理進行結晶化。又,亦要求使其結晶化後的比電阻低。當比電阻低時,即便減薄膜厚仍可減小片電阻值。又,透明導電膜要求高的穿透率,但藉由減薄膜厚,可提高穿透率。過去基於在熱處理下容易結晶化且使其結晶化後的比電阻亦較低,便使用以氧化物換算計含有3質量%左右之錫的銦錫氧化物(例如參照專利文獻1~3)。 From the above viewpoint, first, an indium tin oxide which is easily etched in an amorphous state is formed into a film, and the indium tin oxide in an amorphous state is etched to form a plurality of transparent electrodes, and then crystallized by heat treatment. good. At this time, it is required that the indium tin oxide in an amorphous state is easily crystallized by heat treatment. Further, it is also required to have a lower specific resistance after crystallization. When the specific resistance is low, the sheet resistance value can be reduced even if the film thickness is reduced. Further, the transparent conductive film requires a high transmittance, but by reducing the film thickness, the transmittance can be improved. In the past, an indium tin oxide containing about 3% by mass of tin in terms of an oxide is used because it has a low specific resistance after being crystallized and is crystallized by heat treatment (see, for example, Patent Documents 1 to 3).
專利文獻1:日本特開2011-65937號公報 Patent Document 1: Japanese Laid-Open Patent Publication No. 2011-65937
專利文獻2:日本特開2011-100749號公報 Patent Document 2: Japanese Laid-Open Patent Publication No. 2011-100749
專利文獻3:日本特開2004-149884號公報 Patent Document 3: Japanese Laid-Open Patent Publication No. 2004-149884
近年伴隨著觸控面板裝置等電子機器的大型化,操作時在透明導電膜之傳達速度的降低令人困擾。為了抑制傳達速度的降低,必須使透明導電膜的片電阻值減低更甚以往。具體而言係要求將透明導電膜之片電阻值減低至150Ω/□以下。 In recent years, with the increase in the size of electronic devices such as touch panel devices, the reduction in the transmission speed of the transparent conductive film during operation has been troublesome. In order to suppress the decrease in the communication speed, it is necessary to reduce the sheet resistance value of the transparent conductive film more recently. Specifically, it is required to reduce the sheet resistance of the transparent conductive film to 150 Ω/□ or less.
針對上述以氧化物換算計含有3質量%左右之錫的銦錫氧化物,雖可藉由使膜厚增加來減低使其結晶化後的片電阻值,但為了製成預定的片電阻值,必須使膜厚充分夠厚。從使穿透率等光學特性佳之觀點看來,膜厚在25nm以下為佳,針對上述以氧化物換算計含有3質量%左右之錫的銦錫氧化物,為了獲得預定的片電阻值,必需製成如超過25nm的膜厚。 In the case of the indium tin oxide containing about 3% by mass of tin in terms of oxide, the sheet resistance value after crystallization is reduced by increasing the film thickness, but in order to obtain a predetermined sheet resistance value, The film thickness must be sufficiently thick enough. In view of the fact that the film thickness is preferably 25 nm or less, the indium tin oxide containing about 3% by mass of tin in terms of oxide is required to obtain a predetermined sheet resistance value. A film thickness of, for example, more than 25 nm is produced.
另一方面,作為透明導電膜之構成材料,周知亦有以氧化物換算計含有10質量%左右之錫的銦錫氧化物,比上述以氧化物換算計含有3質量%左右之錫的銦錫氧化物更可減低使其結晶化後的片電阻值。然而,以氧化物換算計含有10質量%左右之錫的銦錫氧化物未必容易結晶化,且當其處在製成結晶化所需的厚度時,穿透率等光學特性不會良好。 On the other hand, as a constituent material of the transparent conductive film, indium tin oxide containing about 10% by mass of tin in terms of oxide is known, and indium tin containing about 3% by mass of tin in terms of oxide is known. The oxide can further reduce the sheet resistance value after crystallization. However, indium tin oxide containing about 10% by mass of tin in terms of oxide is not necessarily easily crystallized, and when it is at a thickness required for crystallization, the optical characteristics such as transmittance are not good.
本發明係用以解決上述課題而實踐者,目的在於提供一種具有非晶質層之導電膜用素材,且該非晶質層易於以熱處理進行結晶化,使其結晶化後的片電阻值低且膜厚之增加業經抑制。又,本發明目的在於提供一種具有片 電阻值低且膜厚之增加業經抑制之晶質層的導電膜積層體、及具有該導電膜積層體之電子機器。此外,本發明目的在於提供上述導電膜用素材及導電膜積層體之製造方法。 The present invention has been made to solve the above problems, and an object of the invention is to provide a material for a conductive film having an amorphous layer, which is easy to be crystallized by heat treatment, and has a low sheet resistance value after crystallization. The increase in film thickness is suppressed. Moreover, it is an object of the present invention to provide a tablet A conductive film laminate having a low resistance value and an increase in film thickness, which is suppressed by a crystalline layer, and an electronic device having the conductive film laminate. Further, an object of the present invention is to provide a material for a conductive film and a method for producing a conductive film laminate.
本發明之導電膜用素材具有透明基材及非晶質層,該非晶質層係由積層在前述透明基材上之銦錫氧化物所構成。前述非晶質層係由氧化物換算計含有5.5~9質量%之錫的銦錫氧化物所構成,膜厚為15~25nm且使其結晶化後的片電阻值為50~150Ω/□者。 The material for a conductive film of the present invention has a transparent substrate and an amorphous layer, and the amorphous layer is composed of indium tin oxide laminated on the transparent substrate. The amorphous layer is composed of indium tin oxide containing 5.5 to 9% by mass of tin in terms of oxide, and has a sheet thickness of 15 to 25 nm and a sheet resistance of 50 to 150 Ω/□ after crystallization. .
本發明之導電膜積層體具有透明基材及晶質層,該晶質層係由積層在前述透明基材上之銦錫氧化物所構成。前述晶質層係由以氧化物換算計含有5.5~9質量%之錫的銦錫氧化物所構成,膜厚為15~25nm且片電阻值為50~150Ω/□。 The conductive film laminate of the present invention has a transparent substrate and a crystal layer, and the crystal layer is composed of indium tin oxide laminated on the transparent substrate. The crystal layer is composed of indium tin oxide containing 5.5 to 9% by mass of tin in terms of oxide, and has a film thickness of 15 to 25 nm and a sheet resistance of 50 to 150 Ω/□.
本發明之電子機器特徵在於具有上述本發明之導電膜積層體。 The electronic apparatus of the present invention is characterized by having the above-described conductive film laminate of the present invention.
本發明之導電膜用素材之製造方法特徵在於具有成膜步驟,該成膜步驟係使用濺鍍靶材並以濺鍍法於透明基材上使非晶質層成膜者,該濺鍍靶材係由以氧化物換算計含有5.5~9質量%之錫的銦錫氧化物所構成,該非晶質層之膜厚為15~25nm且使其結晶化後的片電阻值為50~150Ω/□。 The method for producing a material for a conductive film of the present invention is characterized by having a film forming step of depositing an amorphous layer on a transparent substrate by sputtering using a sputtering target, which is a sputtering target The material is composed of indium tin oxide containing 5.5 to 9% by mass of tin in terms of oxide, and the film thickness of the amorphous layer is 15 to 25 nm and the sheet resistance after crystallization is 50 to 150 Ω/ □.
本發明之導電膜積層體之製造方法特徵在於具有下述步驟:成膜步驟,係使用濺鍍靶材並以濺鍍法於透 明基材上使非晶質層成膜而製得導電膜用素材,該濺鍍靶材係由以氧化物換算計含有5.5~9質量%之錫的銦錫氧化物所構成,該非晶質層之膜厚為15~25nm且使其結晶化後的片電阻值為50~150Ω/□;及熱處理步驟,係將前述導電膜用素材進行熱處理,使前述非晶質層結晶化而製成晶質層。 The method for producing a conductive film laminate according to the present invention is characterized in that the film forming step is performed by using a sputtering target and sputtering. A material for a conductive film is formed by forming an amorphous layer on a substrate, and the sputtering target is made of indium tin oxide containing 5.5 to 9% by mass of tin in terms of oxide, and the amorphous layer is formed. The film thickness is 15 to 25 nm and the sheet resistance value after crystallization is 50 to 150 Ω/□. In the heat treatment step, the conductive film is heat-treated to crystallize the amorphous layer to form a crystal. Quality layer.
本發明之導電膜積層體之製造方法特徵在於具有下述步驟:成膜步驟,係使用濺鍍靶材並以濺鍍法於透明基材上使非晶質層成膜而製得導電膜用素材,該濺鍍靶材係由以氧化物換算計含有5.5~9質量%之錫的銦錫氧化物所構成,該非晶質層之膜厚為15~25nm且使其結晶化後的片電阻值為50~150Ω/□;藉由蝕刻加工將前述導電膜用素材之非晶質層圖案化之步驟;及熱處理步驟,將業經圖案化之導電膜用素材進行熱處理,使前述非晶質層結晶化而製成晶質層。 The method for producing a conductive film laminate according to the present invention is characterized in that the film forming step is performed by using a sputtering target and forming an amorphous layer on a transparent substrate by a sputtering method to obtain a conductive film. In the material, the sputtering target is made of indium tin oxide containing 5.5 to 9% by mass of tin in terms of oxide, and the thickness of the amorphous layer is 15 to 25 nm and the sheet resistance is crystallized. a value of 50 to 150 Ω/□; a step of patterning the amorphous layer of the material for the conductive film by etching; and a heat treatment step of heat-treating the patterned conductive film with the material to form the amorphous layer Crystallization is carried out to form a crystalline layer.
依據本發明,可提供一種具有非晶質層之導電膜用素材,且該非晶質層易於以熱處理進行結晶化,使其結晶化後的片電阻值低且膜厚之增加業經抑制。又,依據本發明,可提供一具有片電阻值低且膜厚之增加業經抑制之晶質層的導電膜積層體、及一具有該導電膜積層體之電子機器。此外,依據本發明可提供一用以製造上述導電膜用素材及導電膜積層體之製造方法。 According to the present invention, it is possible to provide a material for a conductive film having an amorphous layer, and the amorphous layer is easily crystallized by heat treatment, and the sheet resistance after crystallization is low and the increase in film thickness is suppressed. Further, according to the present invention, it is possible to provide a conductive film laminate having a sheet resistance having a low sheet resistance and an increase in film thickness, and an electronic device having the conductive film laminate. Further, according to the present invention, a method for producing the above-mentioned material for a conductive film and a laminated body of a conductive film can be provided.
10‧‧‧導電膜用素材 10‧‧‧Material for conductive film
11‧‧‧透明基材 11‧‧‧Transparent substrate
12‧‧‧非晶質層 12‧‧‧Amorphous layer
20‧‧‧導電膜積層體 20‧‧‧Conductor laminar body
21‧‧‧晶質層 21‧‧‧The grain layer
圖1係顯示導電膜用素材之一實施形態的剖面圖。 Fig. 1 is a cross-sectional view showing an embodiment of a material for a conductive film.
圖2係顯示導電膜積層體之一實施形態的剖面圖。 Fig. 2 is a cross-sectional view showing an embodiment of a conductive film laminate.
圖3所示者係非晶質層成膜時的氧氣流量與非晶質層熱處理前後的片電阻值之關係一例。 Fig. 3 shows an example of the relationship between the oxygen flow rate at the time of film formation of the amorphous layer and the sheet resistance value before and after heat treatment of the amorphous layer.
圖4所示者係濺鍍靶材中錫以氧化物換算之含量與片電阻值成為最低值時之氧氣流量(最佳流量)之關係一例。 The relationship between the content of tin in the sputtering target and the oxygen flow rate (optimum flow rate) when the sheet resistance value becomes the lowest value is shown in FIG.
以下就本發明詳細說明。 The invention is described in detail below.
圖1係顯示導電膜用素材之一實施形態的剖面圖。 Fig. 1 is a cross-sectional view showing an embodiment of a material for a conductive film.
導電膜用素材10例如具有透明基材11及非晶質層12,該非晶質層12係由積層在該透明基材11上之非晶質狀態之銦錫氧化物所構成。上述導電膜用素材10可使用在透明基材11上積層有結晶性透明導電膜的導電膜積層體之製造,該結晶性透明導電膜係由晶質狀態之銦錫氧化物所構成。即,非晶質層12以熱處理進行結晶化而成為結晶性透明導電膜。 The material 10 for a conductive film has, for example, a transparent substrate 11 and an amorphous layer 12, and the amorphous layer 12 is made of an indium tin oxide in an amorphous state laminated on the transparent substrate 11. The conductive material 10 for a conductive film can be produced by using a conductive film laminate in which a crystalline transparent conductive film is laminated on a transparent substrate 11, and the crystalline transparent conductive film is made of a crystalline indium tin oxide. In other words, the amorphous layer 12 is crystallized by heat treatment to form a crystalline transparent conductive film.
在此,所謂非晶質與晶質係於HCl溶液(濃度1.5mol/L)浸漬3分鐘左右,測定電阻值求出電阻值變化率(浸漬後之電阻值/浸漬前之電阻值),藉由該電阻值變化率來進行評估。該電阻值變化率超過200%之情況評估為非晶質,又電阻值變化率在200%以下之情況則評估為晶質。 Here, the amorphous and crystalline phases are immersed in a HCl solution (concentration: 1.5 mol/L) for about 3 minutes, and the resistance value is measured to obtain a resistance value change rate (resistance value after immersion/resistance value before immersion). The evaluation is made by the rate of change of the resistance value. The case where the resistance value change rate exceeds 200% is evaluated as amorphous, and the case where the resistance value change rate is 200% or less is evaluated as crystal.
透明基材11宜為例如聚乙烯或聚丙烯等聚烯烴;聚對苯二甲酸乙二酯、聚對苯二甲酸丁二酯、聚萘二甲酸乙二酯等聚酯、尼龍6、尼龍66等聚醯胺、聚醯亞胺、聚芳酯、聚碳酸酯、聚丙烯酸酯、聚醚碸、聚碸、及該等 共聚物之無延伸或經延伸之塑膠膜。而,透明基材11亦可使用透明性高的其他塑膠膜。該等中尤以由聚對苯二甲酸乙二酯所構成之塑膠膜為佳。 The transparent substrate 11 is preferably a polyolefin such as polyethylene or polypropylene; polyester such as polyethylene terephthalate, polybutylene terephthalate or polyethylene naphthalate, nylon 6, nylon 66 Polyamide, polyimine, polyarylate, polycarbonate, polyacrylate, polyether, polyfluorene, and the like A stretched or stretched plastic film of the copolymer. Further, as the transparent substrate 11, other plastic films having high transparency can also be used. Among these, a plastic film composed of polyethylene terephthalate is preferred.
亦可於透明基材11其中一面或兩面形成硬塗層等底塗層。又,亦可對透明基材11施行易接著處理、電漿處理及電暈處理等表面處理。從可撓性及耐久性等觀點看來,透明基材11之厚度以10~200μm為佳。 An undercoat layer such as a hard coat layer may be formed on one or both sides of the transparent substrate 11. Further, the transparent substrate 11 may be subjected to surface treatment such as easy subsequent treatment, plasma treatment, and corona treatment. The thickness of the transparent substrate 11 is preferably from 10 to 200 μm from the viewpoints of flexibility and durability.
作為硬塗層,可舉如透明且硬質的有機材料層。硬塗層之厚度以1~15μm為佳,且以1.5~10μm較佳。使硬塗層之膜厚在1μm以上,可藉由硬塗層之形成獲得期待的效果。又,使膜厚在15μm以下,可抑制成膜效率降低,同時亦可抑制裂紋產生。 As the hard coat layer, a transparent and hard organic material layer can be mentioned. The thickness of the hard coat layer is preferably from 1 to 15 μm, and more preferably from 1.5 to 10 μm. When the film thickness of the hard coat layer is 1 μm or more, the desired effect can be obtained by the formation of the hard coat layer. Further, when the film thickness is 15 μm or less, the film formation efficiency can be suppressed from being lowered, and crack generation can be suppressed.
硬塗層係由例如藉由游離輻射線硬化的硬化性樹脂或熱硬化性樹脂構成。藉由游離輻射線硬化的硬化性樹脂材料可含有丙烯酸系材料,可使用如多元醇之丙烯酸或甲基丙烯酸酯的多官能或多官能(甲基)丙烯酸酯化合物,以及如由二異氰酸酯與多元醇及丙烯酸或甲基丙烯酸之羥基酯等合成之多官能胺基甲酸酯(甲基)丙烯酸酯化合物。又,該等以外亦可使用具有丙烯酸酯系官能基之聚醚樹脂、聚酯樹脂、環氧樹脂、醇酸樹脂、螺縮醛樹脂、聚丁二烯樹脂及聚硫醇多烯樹脂等。又,亦可使用熱硬化型聚矽氧烷樹脂等。 The hard coat layer is composed of, for example, a curable resin or a thermosetting resin which is cured by free radiation. The curable resin material hardened by the free radiation may contain an acrylic material, a polyfunctional or polyfunctional (meth) acrylate compound such as a polyacrylic acid or a methacrylate, and a diisocyanate and a poly A synthetic polyfunctional urethane (meth) acrylate compound such as an alcohol and a hydroxy ester of acrylic acid or methacrylic acid. Further, a polyether resin having an acrylate functional group, a polyester resin, an epoxy resin, an alkyd resin, a acetal resin, a polybutadiene resin, a polythiol polyene resin, or the like may be used. Further, a thermosetting polydecane resin or the like can also be used.
作為硬化性樹脂之塗佈方法,以濕式成膜法為佳,且以使用輥塗器、反向輥塗器、凹板塗佈器、微凹板 塗佈器、刀塗器、桿塗器、繞線桿塗器、模塗器、浸塗器之塗佈方法為佳。 As a coating method of the curable resin, a wet film formation method is preferred, and a roll coater, a reverse roll coater, a concave plate coater, and a micro-concave plate are used. The coating method of the applicator, the knife coater, the rod coater, the wire rod coater, the die coater, and the dip applicator is preferred.
作為游離輻射線,例如可使用紫外線或電子射線。在紫外線硬化的情況下可利用高壓水銀燈、低壓水銀燈、超高壓水銀燈、金屬鹵素燈、碳弧、氙弧等光源。又,在電子射線硬化的情況下可利用由柯克勞夫-沃耳吞型、凡德格拉夫型、共振變壓型、絕緣核心變壓器型、直線型、高頻高壓(Dynamitron)型、高頻型等各種電子射線加速器釋出之電子射線。 As the radical radiation, for example, ultraviolet rays or electron rays can be used. In the case of ultraviolet curing, a high-pressure mercury lamp, a low-pressure mercury lamp, an ultra-high pressure mercury lamp, a metal halide lamp, a carbon arc, a xenon arc or the like can be used. In addition, in the case of electron beam hardening, it can be used by Krakow-Worthon type, Van de Graaff type, resonance transformer type, insulated core transformer type, linear type, high frequency high voltage (Dynamitron) type, high Electron rays emitted by various electron ray accelerators such as frequency type.
為了促進非晶質層12在熱處理時之結晶化,亦可於透明基材11與非晶質層12之間設置底層(未圖示)。底層只要可促進非晶質層12之結晶化即無特別限制,可舉例如金屬、其金屬之氧化物、硫化物或氟化物等由無機化合物所構成者。該等中又以氧化矽或氧化鋁為佳,以氧化矽較佳,尤以SiOx(x為1.5~2)為佳。 In order to promote crystallization of the amorphous layer 12 during heat treatment, a primer layer (not shown) may be provided between the transparent substrate 11 and the amorphous layer 12. The underlayer is not particularly limited as long as it can promote crystallization of the amorphous layer 12, and examples thereof include those made of an inorganic compound such as a metal, an oxide of a metal, a sulfide, or a fluoride. Among them, ruthenium oxide or aluminum oxide is preferred, and ruthenium oxide is preferred, and SiOx (x is 1.5 to 2) is preferred.
底層之厚度只要可促進非晶質層12在熱處理時之結晶化即無必要限制,惟以1nm以上為佳,且以3nm以上較佳。使底層之厚度在1nm以上可有效地促進非晶質層12之結晶化。底層之厚度若有5nm左右,即可充分地促進非晶質層12之結晶化,使其在10nm以下則可有良好的生產性及透明性。 The thickness of the underlayer is not particularly limited as long as it can promote crystallization of the amorphous layer 12 during heat treatment, and is preferably 1 nm or more, and more preferably 3 nm or more. The thickness of the underlayer is 1 nm or more, and the crystallization of the amorphous layer 12 can be effectively promoted. When the thickness of the underlayer is about 5 nm, the crystallization of the amorphous layer 12 can be sufficiently promoted, and when it is 10 nm or less, good productivity and transparency can be obtained.
非晶質層12在導電膜用素材10之階段為非晶質狀態,以熱處理進行結晶化而成為晶質層(即結晶性透明導電膜)。非晶質層12係由銦及錫之氧化物即銦錫氧化物所構 成,銦錫氧化物中以氧化物換算(SnO2的錫氧化物換算,以下皆同)計含有5.5~9質量%之錫。作為構成銦錫氧化物的氧化物,可舉例如氧化銦、氧化錫、及氧化銦與氧化錫之複合氧化物。 The amorphous layer 12 is in an amorphous state at the stage of the material 10 for a conductive film, and is crystallized by heat treatment to form a crystal layer (that is, a crystalline transparent conductive film). The amorphous layer 12 is composed of indium tin oxide which is an oxide of indium and tin, and the indium tin oxide is 5.5 to 9 mass% in terms of oxide (in terms of SnO 2 in terms of tin oxide). Tin. Examples of the oxide constituting the indium tin oxide include indium oxide, tin oxide, and a composite oxide of indium oxide and tin oxide.
如此一來藉由將非晶質層12設為由以氧化物換算計含有5.5~9質量%之錫的銦錫氧化物所構成者,可使之成為易於以熱處理進行結晶化,使其結晶化後的片電阻值低且膜厚之增加業經抑制者。具體而言,可使之成為膜厚為15~25nm且使其結晶化後的片電阻值為50~150Ω/□,又易於以熱處理進行結晶化者。又,依此設定可與習知同樣地亦使蝕刻性佳。從以熱處理進行結晶化之容易性及使其結晶化後的片電阻值之觀點看來,銦錫氧化物中錫以氧化物換算計之含量在5.8質量%以上為佳,超過6質量%較佳,且在6.5質量%以上更佳。又,在8.9質量%以下為佳,在8.5質量%以下較佳,且在8.3質量%以下更佳。而,以下有時會將銦錫氧化物中錫以氧化物換算計之錫氧化物含量僅表記為錫氧化物含量。 When the amorphous layer 12 is made of indium tin oxide containing 5.5 to 9% by mass of tin in terms of oxide, it is easy to crystallize by heat treatment and crystallize it. The sheet resistance after the reduction is low and the increase in film thickness is suppressed. Specifically, it can be made into a film thickness of 15 to 25 nm and the sheet resistance value after crystallization is 50 to 150 Ω/□, and it is easy to crystallize by heat treatment. Further, in the same manner as described above, the etching property can be improved as well. The content of tin in the indium tin oxide in terms of oxide is preferably 5.8 mass% or more, and more than 6% by mass, from the viewpoint of easiness of crystallization by heat treatment and sheet resistance value after crystallization. Good, and more preferably 6.5 mass% or more. Further, it is preferably 8.9 mass% or less, more preferably 8.5 mass% or less, and still more preferably 8.3% by mass or less. In the following, the tin oxide content of tin in the indium tin oxide in terms of oxide is sometimes expressed as the tin oxide content.
非晶質層12之膜厚只要在15~25nm即無特別限制,從以熱處理進行結晶化之容易性及穿透率等光學特性之觀點看來則以20~25nm為佳。又,非晶質層12在結晶化後之片電阻值只要在50~150Ω/□即無特別限制,但從對觸控面板等電子機器大型化所致之操作時傳達速度降低之抑制及以熱處理進行結晶化之容易性的觀點看來,則以80~150Ω/□為佳,且以100~150Ω/□較佳。 The thickness of the amorphous layer 12 is not particularly limited as long as it is 15 to 25 nm, and is preferably 20 to 25 nm from the viewpoints of easiness of crystallization by heat treatment and optical properties such as transmittance. In addition, the sheet resistance value of the amorphous layer 12 after crystallization is not particularly limited as long as it is 50 to 150 Ω/□, but the transmission speed is suppressed from the operation of an electronic device such as a touch panel. From the viewpoint of easiness of crystallization by heat treatment, it is preferably 80 to 150 Ω/□, and more preferably 100 to 150 Ω/□.
非晶質層12宜僅由銦錫氧化物所構成,惟可因應 需求且在不違反本發明主旨之限度下含有銦錫氧化物以外之成分。作為銦錫氧化物以外之成分,可舉例如鋁、鋯、鎵、矽、鎢、鋅、鈦、鎂、鈰、鍺等之氧化物。非晶質層12中銦錫氧化物以外之成分含量在非晶質層12全體中佔10質量%以下,以5質量%以下為佳,以3質量%以下較佳,且以1質量%以下尤佳。 The amorphous layer 12 should be composed only of indium tin oxide, but it can be adapted It is required and contains components other than indium tin oxide without departing from the gist of the present invention. Examples of the component other than the indium tin oxide include oxides of aluminum, zirconium, gallium, germanium, tungsten, zinc, titanium, magnesium, lanthanum, cerium, and the like. The content of the component other than the indium tin oxide in the amorphous layer 12 is 10% by mass or less, preferably 5% by mass or less, preferably 3% by mass or less, and preferably 1% by mass or less. Especially good.
導電膜用素材10可藉由熱處理而成為透明基材11上積層有由晶質狀態之銦錫氧化物所構成之結晶性透明導電膜的導電膜積層體。即,可藉由以熱處理使非晶質層12結晶化製成晶質層(即結晶性透明導電膜)而成為導電膜積層體。 The conductive film material 10 can be a conductive film laminate in which a crystalline transparent conductive film made of a crystalline indium tin oxide is laminated on the transparent substrate 11 by heat treatment. In other words, the amorphous layer 12 can be crystallized by heat treatment to form a crystalline layer (that is, a crystalline transparent conductive film) to form a conductive film laminate.
熱處理例如宜在大氣中,在100~150℃下進行30~180分鐘。藉由將熱處理溫度設在100℃以上並將熱處理時間設在30分以上,可有效地使非晶質層12結晶化。又,藉由將熱處理溫度設為150℃且將熱處理時間設為180分,可充分地進行結晶化,而設在150℃以下及180分以下則可抑制透明基材11等之損傷,又亦可抑制生產性之降低。 The heat treatment is preferably carried out in the atmosphere at 100 to 150 ° C for 30 to 180 minutes. By setting the heat treatment temperature to 100 ° C or higher and setting the heat treatment time to 30 minutes or more, the amorphous layer 12 can be effectively crystallized. In addition, by setting the heat treatment temperature to 150 ° C and setting the heat treatment time to 180 minutes, crystallization can be sufficiently performed, and when it is 150 ° C or less and 180 minutes or less, the damage of the transparent substrate 11 or the like can be suppressed. It can suppress the decrease in productivity.
圖2係顯示將導電膜用素材10進行熱處理而製得之導電膜積層體20之一實施形態的剖面圖。導電膜積層體20例如具有透明基材11及積層在該透明基材11上之晶質層21。如既已說明,晶質層21係使非晶質層12經熱處理而結晶化所形成者,以作為結晶性透明導電膜之用。 FIG. 2 is a cross-sectional view showing an embodiment of the conductive film laminate 20 obtained by heat-treating the conductive material 10 for a conductive film. The conductive film laminate 20 has, for example, a transparent substrate 11 and a crystal layer 21 laminated on the transparent substrate 11. As described above, the crystal layer 21 is formed by crystallizing the amorphous layer 12 by heat treatment, and is used as a crystalline transparent conductive film.
欲製得形成有由透明導電膜經蝕刻加工進行圖案化而成之多數個透明電極的導電膜積層體時,亦可對導電膜用 素材10之非晶質層12在非晶質階段藉由蝕刻加工施行期望的圖案化,並以熱處理使該已施行圖案化之非晶質層(即多數個非晶質狀態之透明電極)結晶化,而製成結晶性透明導電膜、亦即晶質層21(即多數個晶質狀態之透明電極)。如此一來,首先形成蝕刻加工不會耗費時間之非晶質狀態的銦錫氧化物之膜,並對該非晶質狀態之銦錫氧化物之膜進行蝕刻加工而形成多數個透明電極後,以熱處理使其結晶化,藉此即不會在用以形成透明電極之蝕刻加工上耗費多餘的時間,又可製得多數個透明電極之圖案形狀形成期望形狀之良好的導電膜積層體。 When a conductive film laminate having a plurality of transparent electrodes formed by etching a transparent conductive film is formed, it is also possible to use a conductive film for a conductive film. The amorphous layer 12 of the material 10 is subjected to a desired patterning by an etching process in an amorphous phase, and the patterned amorphous layer (i.e., a plurality of transparent electrodes in an amorphous state) is crystallized by heat treatment. The crystalline transparent conductive film, that is, the crystalline layer 21 (i.e., a plurality of transparent electrodes in a crystalline state) is formed. In this manner, first, a film of an indium tin oxide in an amorphous state which does not require time for etching is formed, and a film of the indium tin oxide in an amorphous state is etched to form a plurality of transparent electrodes, and then a plurality of transparent electrodes are formed. The heat treatment causes crystallization, whereby no excessive time is required for the etching process for forming the transparent electrode, and a pattern of a plurality of transparent electrodes can be obtained to form a favorable conductive film laminate having a desired shape.
而,亦可藉由熱處理使非晶質層結晶化而形成結晶性透明導電膜後,對該結晶性透明導電膜藉由蝕刻加工施行期望的圖案化而形成多數個透明電極等。 Alternatively, a crystalline transparent conductive film may be formed by crystallization of an amorphous layer by heat treatment, and then a plurality of transparent electrodes or the like may be formed by performing a desired patterning on the crystalline transparent conductive film by etching.
晶質層21係由銦及錫之氧化物即銦錫氧化物所構成,銦錫氧化物中以氧化物換算計含有5.5~9質量%之錫。銦錫氧化物中錫以氧化物換算計之錫氧化物含量在5.8質量%以上為佳,超過6質量%較佳,且在6.5質量%以上更佳。又,在8.9質量%以下為佳,在8.5質量%以下較佳,且在8.3質量%以下更佳。而,銦錫氧化物宜具有氧化銦(In2O3)之結晶結構,且於銦側經錫取代。 The crystal layer 21 is composed of indium tin oxide which is an oxide of indium and tin, and the indium tin oxide contains 5.5 to 9% by mass of tin in terms of oxide. The tin oxide content of tin in the indium tin oxide is preferably 5.8% by mass or more, more preferably 6% by mass, and more preferably 6.5 mass% or more. Further, it is preferably 8.9 mass% or less, more preferably 8.5 mass% or less, and still more preferably 8.3% by mass or less. Further, the indium tin oxide preferably has a crystal structure of indium oxide (In 2 O 3 ) and is substituted with tin on the indium side.
晶質層21之膜厚只要在15~25nm即無特別限制,從其製造時以熱處理進行結晶化之容易性及穿透率等光學特性之觀點看來,則以15~25nm為佳,且以20~25nm較佳。又,晶質層21之片電阻值只要在50~150Ω/□即無特 別限制,但從對觸控面板等電子機器大型化所致之操作時傳達速度降低之抑制及結晶化之容易性的觀點看來,則以80~150Ω/□為佳,且以100~150Ω/□較佳。 The film thickness of the crystal layer 21 is not particularly limited as long as it is 15 to 25 nm, and it is preferably 15 to 25 nm from the viewpoints of easiness of crystallization by heat treatment and optical characteristics at the time of production. It is preferably 20 to 25 nm. Moreover, the sheet resistance of the crystal layer 21 is not particularly high as long as it is 50 to 150 Ω/□. It is not limited, but it is preferably 80 to 150 Ω/□ and 100 to 150 Ω from the viewpoint of suppressing the decrease in speed and the ease of crystallization in the operation of an electronic device such as a touch panel. /□ is better.
上述導電膜積層體20適合使用於電子機器。尤其從結晶性透明導電膜、亦即晶質層21的片電阻值低至150Ω/□以下且大型化後傳達速度之降低少的觀點看來,適合使用於大型化的電子機器。 The above-mentioned conductive film laminate 20 is suitably used in an electronic device. In particular, from the viewpoint that the sheet-like transparent conductive film, that is, the sheet layer 21 has a sheet resistance value as low as 150 Ω/□ or less and a small decrease in the conveyance speed after the enlargement, it is suitable for use in an enlarged electronic apparatus.
就電子機器而言,可舉如液晶顯示器裝置、電漿顯示器裝置、觸控面板裝置等,尤以觸控面板裝置為佳。觸控面板裝置例如具有顯示部及配置在該顯示部前面的觸控面板部。導電膜積層體20在此種觸控面板部中可作為具有透明電極之透明電極基板使用。作為觸控面板部,可為藉由上下電極接觸來特定觸控位置的電阻膜式及感應靜電容變化的靜電容結合方式中任一者。 The electronic device may be, for example, a liquid crystal display device, a plasma display device, a touch panel device, or the like, and particularly a touch panel device. The touch panel device includes, for example, a display unit and a touch panel unit disposed on the front surface of the display unit. The conductive film laminate 20 can be used as a transparent electrode substrate having a transparent electrode in such a touch panel portion. The touch panel portion may be any one of a resistive film type in which a touch position is specified by a contact between upper and lower electrodes, and a capacitive coupling method in which an electrostatic capacitance changes.
接下來就導電膜用素材10及導電膜積層體20之製造方法加以說明。 Next, a method of manufacturing the conductive film material 10 and the conductive film laminate 20 will be described.
於透明基材11上因應需求形成底層後將由非晶質狀態之銦錫氧化物所構成之非晶質層12成膜,藉此可製造導電膜用素材10。成膜方法無需限定,惟以濺鍍法、離子電鍍法或真空蒸鍍法為佳,尤以濺鍍法為佳。 After the underlayer is formed on the transparent substrate 11 as needed, the amorphous layer 12 made of an indium tin oxide in an amorphous state is formed, whereby the conductive film material 10 can be produced. The film formation method is not limited, but a sputtering method, an ion plating method, or a vacuum evaporation method is preferred, and a sputtering method is preferred.
應用濺鍍法時,宜使用由銦錫氧化物之燒結物所構成的濺鍍靶材,該燒結物係將氧化錫(SnO2)與氧化銦(In2O3)混合燒結而成。又,濺鍍靶材在銦錫氧化物中以氧化物換算含有5.5~9質量%之錫為佳。銦錫氧化物中錫以氧 化物換算計之錫氧化物含量在5.8質量%以上較佳,超過6質量%更佳,且以在6.5質量%以上尤佳。又,在8.9質量%以下較佳,在8.5質量%以下更佳,且在8.3質量%以下尤佳。 When the sputtering method is applied, it is preferable to use a sputtering target composed of a sintered body of indium tin oxide, which is obtained by mixing and sintering tin oxide (SnO 2 ) and indium oxide (In 2 O 3 ). Further, it is preferable that the sputtering target contains 5.5 to 9% by mass of tin in terms of oxide in the indium tin oxide. The tin oxide content of tin in the indium tin oxide is preferably 5.8% by mass or more, more preferably 6% by mass or more, and particularly preferably 6.5% by mass or more. Further, it is preferably 8.9 mass% or less, more preferably 8.5 mass% or less, and particularly preferably 8.3 mass% or less.
非晶質層12之成膜宜例如一邊將氬氣中混合有0.5~10體積%且理想為0.8~6體積%之氧氣的混合氣體導入濺鍍裝置內,一邊進行濺鍍。一邊導入上述混合氣體一邊進行濺鍍,藉此可成膜形成非晶質且易於以熱處理進行結晶化、又使其結晶化後的片電阻值低之非晶質層12。 The film formation of the amorphous layer 12 is preferably performed by, for example, introducing a mixed gas of 0.5 to 10% by volume and preferably 0.8 to 6% by volume of oxygen in argon gas into the sputtering apparatus. By performing sputtering while introducing the mixed gas, it is possible to form an amorphous layer 12 which is amorphous and which is easily crystallized by heat treatment and crystallized to have a low sheet resistance value.
又,非晶質層12之成膜前,環境條件宜如下:先將濺鍍裝置內之真空度排氣至5×10-4Pa以下且理想在9×10-5Pa以下,並已除去濺鍍裝置內之水分或由透明基材11等產生之水分或有機氣體等的雜質。減低成膜中之水分或有機氣體之存在,容易製得易於以熱處理進行結晶化且使其結晶化後的片電阻值低者。 Further, before the film formation of the amorphous layer 12, the environmental conditions are preferably as follows: first, the degree of vacuum in the sputtering apparatus is evacuated to 5 × 10 -4 Pa or less and desirably 9 × 10 -5 Pa or less, and removed. Moisture in the sputtering apparatus or impurities such as moisture or organic gas generated by the transparent substrate 11 or the like. When the presence of moisture or an organic gas in the film formation is reduced, it is easy to obtain a sheet having a low sheet resistance value which is easily crystallized by heat treatment and crystallized.
圖3所示者係非晶質層12在成膜時之氧氣流量與非晶質層12在熱處理前後之片電阻值之關係一例(靶材中錫氧化物含量為5質量%)。 Fig. 3 shows an example of the relationship between the oxygen flow rate at the time of film formation of the amorphous layer 12 and the sheet resistance value of the amorphous layer 12 before and after the heat treatment (the tin oxide content in the target is 5% by mass).
而,非晶質層12係於作為透明基材11之厚度100μm的PET膜上形成作為底層之厚度50埃的SiOx(x為1.5~2)膜後,於該作為底層之SiOx膜上以厚度255埃成膜。 On the other hand, the amorphous layer 12 is formed by forming a film of SiOx (x is 1.5 to 2) having a thickness of 50 Å as a bottom layer on a PET film having a thickness of 100 μm as a transparent substrate 11, and then using a thickness of SiOx film as a bottom layer. 255 angstroms were formed into a film.
具體而言,SiOx膜係使用硼摻雜多晶矽靶材,導入氬氣中混合有11體積%之氧氣的混合氣體,並在3.7Pa之壓力下進行AC磁控管濺鍍而成膜。又,非晶質層12係使用由銦錫氧化物所構成之濺鍍靶材,導入氬氣與氧氣之混合 氣體,變更氧氣流量,並在0.8Pa之壓力下進行DC磁控管濺鍍而成膜,該銦錫氧化物以氧化物換算計含有5.0質量%之錫。 Specifically, the SiOx film was a boron-doped polycrystalline ruthenium target, and a mixed gas of 11% by volume of oxygen mixed with argon gas was introduced, and an AC magnetron sputtering was performed under a pressure of 3.7 Pa to form a film. Further, the amorphous layer 12 is formed by using a sputtering target composed of indium tin oxide to introduce a mixture of argon gas and oxygen gas. The gas was changed in oxygen flow rate and subjected to DC magnetron sputtering at a pressure of 0.8 Pa, and the indium tin oxide contained 5.0% by mass of tin in terms of oxide.
從圖3可知,片電阻值在非晶質層成膜時的氧氣流量達特定值時為最低值。而且,與片電阻值為最低值時的流量相比,流量愈少或流量愈多,片電阻值愈大。又,雖未圖示,但與片電阻值為最低值時的流量相比,流量愈少,愈難以熱處理進行結晶化。另一方面,與片電阻值為最低值時的流量相比,流量愈多,熱處理後片電阻值愈容易隨著以年單位計的時間經過而增加。 As is apparent from Fig. 3, the sheet resistance value is the lowest value when the oxygen flow rate at the time of film formation of the amorphous layer reaches a specific value. Moreover, the smaller the flow rate or the more the flow rate, the larger the sheet resistance value is compared with the flow rate when the sheet resistance value is the lowest value. Further, although not shown, the flow rate is smaller as compared with the flow rate when the sheet resistance value is the lowest value, and the more difficult it is to heat-treat and crystallize. On the other hand, the more the flow rate is compared with the flow rate when the sheet resistance value is the lowest value, the easier the sheet resistance value after heat treatment increases with the passage of time in units of years.
由此可知,相對於結晶化後片電阻值為最低值時的流量,使非晶質層12成膜時的氧氣流量在0.6~1.4倍之範圍為佳,在0.7~1.3倍之範圍較佳,且尤以在0.8~1.2倍之範圍為佳。因此,實際在非晶質層12之成膜時,宜預先以上述方法求出結晶化後片電阻值為最低值時的氧氣流量,並調整氧氣流量使其相對於該氧氣流量在上述範圍內。從最佳流量亦依成膜裝置而有些微不同而言,尤以上述方法可有效地形成結晶化後片電阻值低的膜。 From this, it is understood that the oxygen flow rate at the time of film formation of the amorphous layer 12 is preferably in the range of 0.6 to 1.4 times, preferably in the range of 0.7 to 1.3 times, with respect to the flow rate when the sheet resistance value at the crystallization is the lowest. And especially in the range of 0.8 to 1.2 times. Therefore, in actual film formation of the amorphous layer 12, it is preferable to determine the oxygen flow rate when the resistance value of the crystallized sheet is the lowest value by the above method, and adjust the oxygen flow rate so as to be within the above range with respect to the oxygen flow rate. . In view of the fact that the optimum flow rate is slightly different depending on the film forming apparatus, the film having a low resistance value after crystallization can be effectively formed by the above method.
圖4所示者係濺鍍靶材中錫以氧化物換算計之錫氧化物含量與非晶質層12在結晶化後之片電阻值為最低值時的氧氣流量之關係一例。而,圖4中顯示出錫以氧化物換算計之錫氧化物含量為2質量%、3質量%、5質量%、7質量%、8.8質量%、10質量%及12質量%之情況。又,成膜條件基本上設與上述條件相同。例如,在錫以氧化物換算計之 錫氧化物含量為3質量%的情況下,結晶化後之片電阻值為最低值時的流量為1.0體積%。又,在10質量%的情況下,該流量為1.4體積%。 FIG. 4 shows an example of the relationship between the tin oxide content in terms of oxide in terms of oxide in the sputtering target and the oxygen flow rate when the sheet resistance value of the amorphous layer 12 after crystallization is the lowest. In addition, FIG. 4 shows a case where the tin oxide content of tin in terms of oxide is 2% by mass, 3% by mass, 5% by mass, 7% by mass, 8.8% by mass, 10% by mass, and 12% by mass. Further, the film formation conditions are basically set to be the same as the above conditions. For example, in tin in terms of oxide When the tin oxide content is 3% by mass, the flow rate when the sheet resistance value after crystallization is the lowest value is 1.0% by volume. Further, in the case of 10% by mass, the flow rate was 1.4% by volume.
導電膜積層體20可藉由將上述導電膜用素材10進行熱處理而製造。即,以熱處理使非晶質層12結晶化,可製得結晶性透明導電膜、亦即晶質層21。熱處理例如宜在大氣中,在100~150℃下進行30~180分鐘。將熱處理溫度設在100℃以上又將熱處理時間設在30分以上,可有效地使非晶質層12結晶化。又,將熱處理溫度設在150℃以下又將熱處理時間設在180分以下,可充分地進行結晶化,設在150℃以下及180分以下,則可抑制透明基材11等之損傷,亦可提升生產性。 The conductive film laminate 20 can be produced by heat-treating the above-mentioned conductive film material 10. That is, the amorphous layer 12 is crystallized by heat treatment, whereby a crystalline transparent conductive film, that is, a crystalline layer 21 can be obtained. The heat treatment is preferably carried out in the atmosphere at 100 to 150 ° C for 30 to 180 minutes. When the heat treatment temperature is set to 100 ° C or higher and the heat treatment time is set to 30 minutes or more, the amorphous layer 12 can be effectively crystallized. In addition, when the heat treatment temperature is set to 150° C. or less and the heat treatment time is set to 180 minutes or less, crystallization can be sufficiently performed, and when it is 150° C. or less and 180 minutes or less, damage to the transparent substrate 11 or the like can be suppressed. Improve productivity.
以下列舉實施例來具體說明本發明之實施形態。試料No.6、8、10~12為本發明之實施例,試料No.1~5、7、9、13~18為本發明之比較例。而,本發明不受該等實施例限定。 The embodiments of the present invention will be specifically described below by way of examples. Sample Nos. 6, 8, and 10 to 12 are examples of the present invention, and Sample Nos. 1 to 5, 7, 9, and 13 to 18 are comparative examples of the present invention. However, the invention is not limited by the embodiments.
非晶質層之膜厚係從光學特性或濺鍍成膜率與濺鍍時間求出之值。即,藉由膜厚計測出在試料製作中採用之以相同濺鍍成膜率及濺鍍條件所製作的非晶質層膜厚,並預先求出在濺鍍時間之每單位時間下成膜的膜厚,從試料製作中之濺鍍時間計算求出膜厚之值。而,膜厚為幾何厚度。 The film thickness of the amorphous layer is a value obtained from optical characteristics, sputtering deposition rate, and sputtering time. In other words, the thickness of the amorphous layer produced by the same sputtering deposition rate and sputtering conditions used in the preparation of the sample was measured by a film thickness meter, and film formation per unit time at the sputtering time was determined in advance. The film thickness was calculated from the sputtering time in the preparation of the sample. However, the film thickness is a geometric thickness.
試料No.1~No.18之製作係以如以下方法進行。 The production of samples No. 1 to No. 18 was carried out as follows.
於透明基材之厚度100μm的PET膜上形成作為底層之 厚度32埃的SiOx(x為1.5~2)膜。SiOx膜係使用硼摻雜多晶矽靶材,一邊導入氬氣中混合有11體積%之氧氣的混合氣體,一邊在3.7Pa之壓力下進行AC磁控管濺鍍而成膜。而,SiOx膜之厚度調整係以調整電力密度與濺鍍時間而進行。 Formed as a bottom layer on a PET film having a thickness of 100 μm on a transparent substrate A film of SiOx (x is 1.5 to 2) having a thickness of 32 angstroms. In the SiOx film, a boron-doped polycrystalline ruthenium target was used, and a mixed gas of 11% by volume of oxygen mixed with argon gas was introduced, and an AC magnetron sputtering was performed under a pressure of 3.7 Pa to form a film. Further, the thickness adjustment of the SiOx film is performed by adjusting the power density and the sputtering time.
作為非晶質層之成膜步驟,於形成有該SiOx膜之PET膜上使用由銦錫氧化物所構成之靶材,一邊導入以預定比率混合有氬氣與氧氣的混合氣體,一邊在0.8Pa之壓力下進行DC磁控管濺鍍,形成非晶質層而製造出導電膜用素材,該銦錫氧化物係以氧化物換算計含有預定量之錫。 In the film formation step of the amorphous layer, a target material composed of indium tin oxide is used on the PET film on which the SiOx film is formed, and a mixed gas of argon gas and oxygen gas is introduced at a predetermined ratio while being 0.8. DC magnetron sputtering is performed under a pressure of Pa to form an amorphous layer, and a material for a conductive film is produced. The indium tin oxide contains a predetermined amount of tin in terms of oxide.
非晶質層之成膜條件詳細如表1所示。靶材係使用將氧化錫(SnO2)與氧化銦(In2O3)混合燒結而成之燒結物,且錫以氧化物換算計之含量(錫氧化物含量)為3~12質量%。氧氣流量係預先求出結晶化後之片電阻值為最低值時的流量並進行調整使其可成為該流量。非晶質層之膜厚調整係以調整電力密度與濺鍍時間進行。而,可推測非晶質層中錫以氧化物換算計之含量與靶材中錫以氧化物換算計之含量相同。 The film formation conditions of the amorphous layer are shown in detail in Table 1. The target is a sintered product obtained by mixing and sintering tin oxide (SnO 2 ) and indium oxide (In 2 O 3 ), and the content of tin (tin oxide content) in terms of oxide is 3 to 12% by mass. The oxygen flow rate is obtained by previously obtaining the flow rate when the sheet resistance value after crystallization is the lowest value, and adjusting the flow rate. The film thickness adjustment of the amorphous layer is performed by adjusting the power density and the sputtering time. On the other hand, it is presumed that the content of tin in the amorphous layer in terms of oxide is the same as the content of tin in the target in terms of oxide.
作為非晶質層之熱處理步驟,針對製得之導電膜用素材在大氣中進行145℃且60分鐘的熱處理而製造出導電膜積層體。 In the heat treatment step of the amorphous layer, a conductive film laminate was produced by subjecting the obtained material for a conductive film to heat treatment at 145 ° C for 60 minutes in the air.
針對使用以如表1記載之含有比率含有錫氧化物的靶材所製出之試料No.1~No.18的各導電膜積層體,將其片電阻值(Ω/□)、非晶質層之膜厚(Å)測定結果、及非晶質層的結晶性評估顯示於表1。 For each of the conductive film laminates of Sample Nos. 1 to No. 18 produced by using a target containing tin oxide as described in Table 1, the sheet resistance (Ω/□) and amorphous were measured. The measurement results of the film thickness (Å) of the layer and the evaluation of the crystallinity of the amorphous layer are shown in Table 1.
(片電阻值) (sheet resistance value)
將各導電膜積層體切成100mm×100mm之尺寸,使用Lorester(三菱化學公司製、商品名)藉由四探針法來測定片電阻值(Ω/□、即Ω/square)。 Each of the conductive film laminates was cut into a size of 100 mm × 100 mm, and a sheet resistance value (Ω/□, that is, Ω/square) was measured by a four-probe method using Lorester (manufactured by Mitsubishi Chemical Corporation).
(結晶性) (crystallinity)
在將各導電膜積層體浸漬於25℃之HCl溶液(濃度1.5mol/L)中3分鐘左右,測定電阻值,並求出電阻值變化率(浸漬後之電阻值/浸漬前之電阻值)。而,如既已說明,電阻值變化率為結晶性之指標,電阻值變化率在200%以下者具有結晶性。表中,電阻值變化率在200%以下者以「○」表示,超過200%者以「×」表示。 Each of the conductive film laminates was immersed in a HCl solution (concentration: 1.5 mol/L) at 25 ° C for about 3 minutes, and the resistance value was measured, and the resistance value change rate (resistance value after immersion/resistance value before immersion) was determined. . Further, as described above, the rate of change in resistance value is an index of crystallinity, and the rate of change in resistance value is 200% or less. In the table, those whose resistance value change rate is 200% or less are indicated by "○", and those exceeding 200% are indicated by "×".
錫以氧化物換算計之含量低於5.5質量%時,即使將膜厚減薄至25nm(250埃)以下,熱處理時的結晶性仍佳,但熱處理後(結晶化後)的片電阻值會衝高超過150Ω/□。另一方面,錫以氧化物換算計之含量超過9質量%時,膜厚超過25nm者熱處理時的結晶性佳且熱處理後的片電阻值亦可獲得在150Ω/□以下之充分夠低的值,但穿透率低;膜厚在25nm以下者熱處理時的結晶性不夠充分,且熱處理後之片電阻值亦衝高超過150Ω/□。錫以氧化物換算計之含量為5.5~9質量%時,膜厚即使減薄至25nm以下,熱處理時之 結晶性仍佳,且熱處理後的片電阻值亦可獲得在150Ω/□以下之充分夠低的值。 When the content of tin is less than 5.5% by mass in terms of oxide, even if the film thickness is reduced to 25 nm (250 angstroms) or less, the crystallinity during heat treatment is good, but the sheet resistance value after heat treatment (after crystallization) The punching height is over 150Ω/□. On the other hand, when the content of tin is more than 9% by mass in terms of oxide, the film thickness is more than 25 nm, and the crystallinity at the time of heat treatment is good, and the sheet resistance value after heat treatment can be sufficiently low enough to be 150 Ω/□ or less. However, the transmittance is low; the crystallinity of the film thickness of 25 nm or less is insufficient when heat treatment, and the sheet resistance after heat treatment is also higher than 150 Ω/□. When the content of tin in terms of oxide is 5.5 to 9% by mass, the film thickness is reduced to 25 nm or less, and heat treatment is performed. The crystallinity is still good, and the sheet resistance value after the heat treatment can also obtain a sufficiently low value of 150 Ω/□ or less.
依據本發明,可製得具有片電阻值低且膜厚之增加業經抑制之晶質層的導電膜積層體,該導電膜積層體可作為電子機器用,尤其可有效地作為使用在大型觸控面板裝置的導電膜積層體使用。 According to the present invention, a conductive film laminate having a sheet resistance having a low sheet resistance and an increased film thickness can be obtained, and the conductive film laminate can be used as an electronic device, and can be effectively used as a large touch. The conductive film laminate of the panel device is used.
而,在此係引用已於2012年5月15日提出申請之日本專利申請案2012-111677號之說明書、申請專利範圍、圖式及摘要之全部內容,並納入作為本發明之揭示。 The entire disclosure of Japanese Patent Application No. 2012-111677, filed on-
10‧‧‧導電膜用素材 10‧‧‧Material for conductive film
11‧‧‧透明基材 11‧‧‧Transparent substrate
12‧‧‧非晶質層 12‧‧‧Amorphous layer
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JP7058581B2 (en) * | 2018-09-26 | 2022-04-22 | 日東電工株式会社 | Radio wave absorber and laminated body for radio wave absorber |
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