TW201340327A - Top drain LDMOS, semiconductor power device and method of manufacturing the same - Google Patents

Abstract

In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite side of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

Description

Top-dip lateral diffusion metal oxide semiconductor, semiconductor power device and preparation method thereof

The invention is primarily concerned with semiconductor power components. More specifically, the present invention relates to a reverse grounded source laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) structure and a method of fabricating the same.

Further reducing the source inductance of the semiconductor power device (including Field Effect Transistor (FET), Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Junction Field Effect Transistor (Junction Field) The traditional process of the source transistor in the Effect Transistor (JFET) component is limited and challenged by many technical problems. In particular, those skilled in the art are faced with the technical challenges of reducing source inductance. At the same time, as more and more power components must have high efficiency, high gain, and high frequency, the need to reduce the source inductance of semiconductor power components is increasing. In general, source inductance can be reduced by eliminating bond leads in a semiconductor power device package. It is possible to attempt to configure the semiconductor substrate as a source electrode for connecting the semiconductor power device and eliminating the bonding wires. Some of the difficulties in these methods stem from the typical vertical semiconductor power components that place the connection electrodes on the substrate. A vertical power component (a trench gate or a double gated double-diffused metal-oxy-semiconductor (DMOS) device) uses a gate as a drain electrode and a current from a source region disposed above the substrate Initially, it flows vertically down to the drain region disposed at the bottom of the substrate. During component packaging, the top source electrode typically needs to be bonded to the leads for electrical connection, thereby increasing the source inductance.

Conventional techniques have proposed a number of lateral DMOS with bottom sources. The lateral DMOS component typically contains a deep P+ sinker (injection or trench settle) in the source junction to connect the top source to the P+ substrate, but the area occupied by the settling region creates a large cell spacing. Or the deep P+ settling zone is outside the unit cell, but this produces a higher source resistance. In August 2004, G. Cao et al. proposed a Polarized Dffused Metal Oxide Semiconductor (LDMOS) in IEEE Electronic Components (pp. 1296-1303) "Comparative Study of Drift Region Design Schemes in RF LDMOSFETs". The component, as shown in Figure 1A, includes a deep sinker that diffuses in the source connector.

Ishiwaka O et al., December 1 - December 4, 1985, at the International Electronic Components Conference, Technical Digest (pp. 166-169), Washington, DC, "Reducing Power of 2.45 GHz by V-Gap Connections" - Source Derivation of MOSFETs, a lateral double-diffused MOS field effect transistor (LD-MOSFET) with V-groove connection is proposed to reduce source inductance, gate capacitance and channel length. The V-groove penetrates the P-type epitaxial layer and touches the P+ type substrate, and is formed in the SiO ₂ region, immediately outside the active region. The N+ source region of the LD-MOSFET is connected directly to the V-groove with metal, eliminating the bond leads of the source.

U.S. Patent 6,372,557 (April 16, 2002, Leong), which proposes a bottom-source lateral LDMOS device, attempts to use a buried layer at the interface of the P+ and P- epitaxial layers to reduce lateral diffusion and thereby reduce the unit cell. spacing. U.S. Patent No. 5,821,144 (Dr. et al., issued Oct. 13, 1998), and U.S. Patent No. 5,869,875 (Hebert, Feb. 9, 1999) also discloses a lateral DMOS component which has a deep settling on the peripheral region of the structure. Zone (an injection settling or trench settling) to reduce cell spacing.

However, the components in these specifications use a single metal instead of the source or body contact area and the gate masking area. The individual metal is very thick (3 um or thicker), which will make the source metal The capacitance to the N-drifting bungee becomes higher, generating more stress on the gate, and the distance to the drain metal is also increased, thereby increasing the cell pitch. On the other hand, some of the components use the first metal for the source or body contact regions, the second metal for the drain and gate shield regions, and then the first metal is thinner so that the gate can be wound and the gate is protected from Low capacitance and small stress effects without affecting cell pitch. However, the use of two metals requires two additional masks, one for the through hole and one for the top metal, which adds cost. This structure is diffused from the top down, usually forming a P+ sinker, which results in a large inter-cell diffusion due to the lateral diffusion of the deep sinker for connecting the top source down to the heavily doped substrate. The overall size of the unit cell on the horizontal plane is increased. The on-resistance is a function of the resistance and the area of the component, so the cell pitch assembly also increases the on-resistance. An increase in component size and an increase in package size due to large cell pitch also increases component cost. Furthermore, reducing the cell pitch of the bottom-source elements of these prior art techniques can cause drift in the electrical performance of the elements. For example, placing a diffusion sinker (doped P+) close to the source side of the gate shown in Figure 1A produces a higher threshold voltage because the diffused p+ sinker is used to connect the top source. To the bottom substrate, its lateral diffusion will encroach on the channel region under the gate, and the channel region is also p-type, which increases the doping concentration in the channel, thereby increasing the threshold voltage, which is what we do not want to see. result.

Patent 7,554,154 proposes a modified reverse ground-source FET on a heavily doped substrate, such as a heavily doped P+ substrate, as shown in Figure 1B, with a self-aligned body-source connector for Reduce the cell spacing. The improved FET includes an integrated body-source shorting structure, P+ sinker, that diffuses toward the drain at the lower portion below the channel. The P+ sinker extends below the surface channel to compensate for the drain extension doping, thereby reducing Cgd and reducing the cell pitch. In addition, the doping concentration of the accumulation region is appropriately adjusted to minimize the peak Cgd*Rdson image. With this top-dole LDMOS structure, an embedded gate shield is provided for the body-source junction to reduce the gate capacitance Cgd, and the element cells are arranged in a closed structure, which can further reduce the termination requirements. Extra space. However, the deep P+ sinker used to connect the top source down to the heavily doped substrate occupies a large space for significant lateral diffusion, which cannot further reduce and reduce the cell pitch.

Therefore, it is highly desirable to propose a novel component structure and a new preparation method of a power semiconductor component, thereby solving the above difficulties and limitations.

Accordingly, one aspect of the present invention is directed to a new and improved top-drain laterally diffused MOS (TD-LDMOS) semiconductor power device with a trench source-body interconnect that passes through the body from the top surface Zone, extending down to the bottom source electrode. The cell pitch of the component structure is small, which reduces the cost of the wafer, thereby solving the above technical problems and limitations.

Specifically, an aspect of the present invention is to provide an improved top-drain laterally diffused MOS (TD-LDMOS) semiconductor power device having a trench source-body interconnection with a bottom substrate source connection, thereby substantially Reduce the source inductance to achieve high efficiency, high gain and high frequency of use.

Another aspect of the present invention is to provide an improved top-drain laterally diffused MOS (TD-LDMOS) semiconductor power device with a trench source-body interconnect starting from the top surface through the body region, down Extending to the bottom source electrode with a narrow opening and high aspect ratio, which significantly reduces cell spacing and masking requirements, further reduces the cost of manufacturing high quality, reliable semiconductor power components.

Another aspect of the present invention is to provide an improved top-drain laterally diffused MOS (TD-LDMOS) semiconductor power device with a trench source-body interconnect starting from the top surface through the body region, down Extends to the bottom source electrode with trenches filled with SEG P++ or SEG P++ SiGe or metal fill material. The trench is further surrounded by a P++ pad implant region below the bottom surface of the trench, further reducing the interconnect resistance between the body and the source on the bottom surface.

Another aspect of the present invention is to provide an improved top-drain laterally diffused MOS (TD-LDMOS) semiconductor power device with a trench source-body interconnect starting from the top surface through the body region, down Extending to the bottom source electrode, the formed gate shielding Ti/TiN layer and the self-aligned polycrystalline germanide layer cover the insulating layer above the gate insulating layer and the top surface of the body region, thereby further reducing the gate capacitance. Therefore, the components described in the present invention are robust and highly reliable, and the component structure is more suitable for use in high voltage and low voltage components.

A preferred embodiment of the present invention primarily provides a top-dip laterally diffused metal oxide field effect semiconductor (TD-LDMOS) device formed on a semiconductor substrate. The top drain LDMOS includes a source electrode formed on a bottom surface of the semiconductor substrate. The top drain LDMOS further includes a source and a drain region disposed on two opposite sides of the planar gate, the planar gate is disposed on a top surface of the semiconductor substrate, wherein the source region is enclosed in the body region, and the The drift zone acts as a lateral current path between the source and drain regions below the planar gate. The top drain LDMOS further includes at least one trench filled with a conductive material extending vertically downward from the body region near the top surface to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

Furthermore, the present invention proposes a method of fabricating a semiconductor power device on a semiconductor substrate. The method comprises: 1) preparing a body region surrounding the source region and the drain region, the gate being on the top surface of the semiconductor substrate for controlling the body region between the source region and the drain region near the top surface of the substrate The lateral current path; 2) the through trench, extending from the body region down to the source electrode on the bottom surface of the substrate, and filling the trench with a conductive material as a body-source interconnect. In one embodiment, the step of filling the trench with a conductive material includes filling the trench with a conductive material comprising a Selective Epitaxial Growth (SEG) or a SiGe SEG. In another embodiment, the method further includes implanting a heavily doped linear region below the bottom of the trench and around the sidewall of the trench.

These and other features and advantages of the present invention will become apparent to those skilled in the <RTIgt;

101. . . N++ substrate

105. . . P+ substrate

110. . . P-epitaxial layer

115. . . Body area

120. . . Deep trench

125. . . Bungee drifting area

128. . . P++ linear injection area

129. . . Metal liner

130. . . Field oxide

135. . . Gate oxide

140. . . Stacked planar gate

160. . . Source area

165. . . Gate gasket

170-G. . . Gate shielding metal

170-S. . . Polycrystalline telluride moiety

180. . . BPSG layer

185. . . Passivation layer

190. . . N+ doped region

198. . . Ti/TiN linear barrier

199. . . Top bungee metal

205. . . Boron doped P+ substrate

210. . . P-epitaxial layer

212. . . Pad oxide layer

215. . . Deep buffer

220. . . Local area interconnection

225. . . N-drift zone

230. . . Field oxidation zone

235. . . Gate oxide layer

240. . . Polycrystalline telluride layer

245. . . Oxidation mask

250. . . P-body area

255. . . Trench

260. . . N+ source region

265. . . Gasket oxide

275. . . Ti/TiN layer

275’. . . Co layer

280. . . Insulation

285. . . Bungee contact opening

290. . . Contact area

295. . . Bungee metal

298. . . Metal layer

Figure 1A shows a cross-sectional view of a laterally diffused MOS (LDMOS) device with a bottom source for an RF base station amplifier.
Figure 1B shows a cross-sectional view of a bottom source LDMOS with a diffusion settling zone, as taught in U.S. Patent No. 7,554,154.
Figure 2A shows a cross-sectional view of a top drain LDMOS device with a trench body-source shorting structure in accordance with one embodiment of the present invention.
Figure 2B shows a cross-sectional view of the entire top drain LDMOS cell unit arranged in a closed cell structure.
Figure 2C shows a top view of the entire top drain LDMOS cell unit arranged in a closed cell structure.
Figure 3 is a cross-sectional view showing another top drain LDMOS device in accordance with another embodiment of the present invention.
4A through 4L are cross-sectional views showing a series of processes for preparing the top drain LDMOS device of the present invention.

Referring to Figure 2A, there is shown a cross-sectional view of an N-channel inverted top-drain and ground-source trench FET device with top and bottom sources of the present invention. The inverted top-drain-ground-source N-channel FET component is located on the P+ substrate 105 as the bottom source electrode. Alternatively, the P-channel component is formed over the N+ germanium (Si) substrate. The P- epitaxial layer 110 is located above the substrate 105. The active cell region and the termination region are configured for the substrate, typically disposed on the periphery of the substrate. The high aspect ratio deep trenches 120 are opened through the epitaxial layer 110 and extend down to the substrate 105. Selective Epitaxial Growth (SEG) or SEG (SiGe), heavy P-doped P++, filled deep trenches 120, form a self-aligned source or body joint, as a local part of ultra-low resistance Area interconnects, from source to body and substrate. To improve the joint, a P++ linear implant region 128 is prepared prior to filling the trench with a P++ conductive trench fill material, with angled P++ implanted below the trench bottom and around the sidewalls of the source-body interconnect trench 120. The body region 115 is formed on the upper portion of the epitaxial layer 110, and the epitaxial layer 110 extends laterally to the drain drift region 125. The P-dopant in the body region 115 surrounds a portion of the N-dopant in the transistor accumulation to accommodate the dopant structure of the N-drift region 125, minimizing the gate capacitance while maintaining a low source resistance. Rdson. The deep trench source-body interconnect 120 extends more vertically downward to the bottom P+ substrate 105 and extends up to the body region 115. A portion of the body region 115 forms a channel at the top surface below the gate oxide 135. The deep trench source-body interconnect 120 has a narrow opening and a high aspect ratio, eliminating the need for a settling zone to reduce the cell pitch, since the formation of the settling zone with lateral diffusion extension can extend the settling zone to a greater depth, reaching Bottom source region 105.

The stacked planar gate 140 is disposed over the gate oxide layer 135, the gate pad 165 surrounds the stacked planar gate 140, the gate shielding metal 170-G covers the stacked planar gate 140, and the gate oxide layer 135 is formed in the source region. The top surface between the 160 and the bungee drift zone 125. Thus, the gate 140 controls the current between the source region 160 and the drain drift region 125, through the channel formed by the body region 115, below the gate 140, as a lateral MOS device. The bungee drift region 125 is disposed under the field oxide 130, and a Boron Phosphorus Silicon Glass (BPSG) layer 180 and a passivation layer 185 (optional) cover the field oxide 130. The drain contact opening is etched by the passivation layer 185 and the BPSG layer 180 such that the top drain metal 199 contacts the drain region 125 by contacting the N+ doped region 190 to reduce the contact resistance. As shown, the stacked gates 140 can be fabricated using different methods with oxides 130, 135 under the stacked gates 140. The method includes growing or depositing an oxide and etching the oxide in the channel region, or utilizing an oxidation process of the LOCOS type. Stack gate 140 has a longer gate length and a field plate above the drain extension without increasing cell pitch. Stack gate 140 controls the path of current between the channel and gate oxide 135 and the drain below field oxide 130, with a lower gate capacitance. The insulating spacer 165 and the buried gate shield 170-G surround the stack gate 140, and the stack gate 140 further includes a self-aligned poly germanide portion 170-S for the body-source junction to further reduce the gate capacitance Cgd, Gate shielding layer 170-G protects the drain metal 199 overlying the top surface. In order to achieve better mechanical and electrical properties, a Ti/TiN linear barrier layer 198 is formed between the drain contact region 190 and the drain metal 199. Since the trench interconnect 120 is selectively epitaxially grown (SEG) P++ Si or SEGP++ SiGe, thereby eliminating the need for settling diffusion, the resulting self-aligned source-body interconnects substantially reduce the cell pitch by half.

Figure 2B is a cross-sectional view showing the entire cell of the top drain LDMOS device of the present invention arranged in a closed cell structure. As shown in Figure 2B, since the source in half of the cell pitch is grounded, it is not necessary to provide additional space for the termination region of the top drain LDMOS device, thereby saving space. Figure 2C shows a top view of the entire unit cell of the top drain LDMOS device of the present invention arranged in a closed cell structure.

Figure 3 shows another embodiment of a top drain LDMOS device similar to that shown in Figure 2. The only difference is that the components are formed on the heavily doped N++ substrate 101, which greatly reduces the series resistance. The P+ epitaxial layer 105 is used as a bottom source electrode, formed over the N++ substrate 101, and shorted to the N++ substrate, reducing the resistance of the substrate. In addition, it is further selected that a deep buffer layer 115 is formed at a predefined depth in the P- epitaxial layer 110 above the P+ source layer 105 in order to adjust the breakdown voltage (BV) and utilize the preparation process. The thermal cycle prevents the surface from penetrating. In the present embodiment, the deep trenches 120 are opened, pass through the P- epitaxial layer 110 and the P+ source layer 105, and extend down to the N++ substrate 101. As shown in FIG. 2A, the deep trenches 120 have a high aspect ratio, and the deep trenches 120 are filled with a heavy P-doped P++ conductive material such as selective epitaxially grown (SEG) germanium or SEG germanium telluride (SiGe). Alternatively, the deep trenches 120 are filled with a metal such as P++ polysilicon or tungsten, and a metal pad 129 (e.g., a self-aligned polysilicon telluride) is formed between the drain and the source to form an ultra low resistance local interconnect. In this element structure, the passivation layer 185 can be omitted.

4A to 4L are a series of cross-sectional views showing a preparation method for preparing the element structures shown in Figs. 2A and 3. By the description of the preparation process, it can be understood that with the self-aligned structure, the process requires only six mask steps. As shown in Fig. 4A, the process starts from the initial ruthenium substrate, which includes a boron-doped P+ substrate 205 having a resistivity of 3 to 5 mOhm-cm or less. Substrate 205 is preferably oriented along the <100> crystal as a standard initial direction. P- epitaxial layer 210 is formed on substrate 205, having a thickness of 2 to 7 microns, typically doped with a dose of 5E14 to 5E15 for 20-60 V devices. In another embodiment, epitaxial layer 210 can be an N-doped layer.

In Figure 4B, a pad oxide layer 212 is grown for subsequent nitride setup processes. An optional processing step is to fully implant a deep buffer layer with an implant dose of 1E14 at an implantation energy of 600 KEV to prepare a deep buffer layer 215 for subsequent breakdown to adjust the breakdown voltage (BV) and prevent The sub-surfaces between the N-drift layers are punched through, and when a subsequent preparation process is performed, the P+ substrate 205 is further prepared since thermal cycling is required. The full P implant can be lightly doped to increase P-doping, avoid punchthrough, or use a lightly doped N- implant for the N- epitaxial layer.

Above the pad oxide layer 212, nitride deposition is performed, and then an active mask, a first mask (not shown) is used for etching to protect the channel region, and the drain region is exposed in a subsequent process. come out. At a zero degree tilt angle, N-drift implantation is performed in a region not protected by nitride to form an N-drift region 225 as shown in Fig. 4C. The N-drift zone 225 can be prepared by implanting phosphorus in the range of 60 Kev to 200 Kev at a dose ranging from 5E11 to 2E13. In practical applications, a suitable dose at 30 V is 3E12. This step creates a self-aligned n-type drift implant (for NMOS) in the drifting drain extension, region 225 of the LDMOS device. Field oxide zone 230 is then formed over N-drift zone 225 using a standard field oxidation process (referred to as Local Oxidation of Silicon, LOCOS), an optional N2 drive process. The temperature is in the range of 900 to 1100 ° C, and an oxide having a thickness of 0.3 to 1 μm is grown, and a suitable thickness is about 0.55 μm.

The nitride (not shown) and the pad oxide 212 are stripped, and then the sacrificial oxide layer is grown and stripped (not shown) to clean the surface of the structure. In Fig. 4D, a gate oxide layer 235 is grown, and then a polysilicon layer is deposited, or a polycrystalline germanide layer 240, most suitably a thickness of 2000 to 6000 angstroms, to form a gate. Subsequently, N+ doping ions are implanted into the polysilicon layer, and a WSix layer may be optionally prepared above to prepare a contact layer having a very low gate resistance. Note that the polysilicon may be doped in situ or may be doped with phosphorus oxychloride (POCl ₃ ). Oxidation hood deposition is performed using a High Temperature Oxidation (HTO) or Low Temperature Oxidation (LTO) process to deposit an oxidized cap layer 245 over the polysilicon layer 240. Above the polysilicon layer 240, the oxide cap layer 245 has a thickness of about 500 to 4500 angstroms. Etching is performed using a gate mask (ie, a second mask (not shown)) and a pattern of oxide cap layer 245 and gate layer 240 is formed. First, an oxide etch is performed to form a pattern of the oxide cap layer 245, followed by polysilicon or polymorph etch. As shown, the polysilicon or poly germanide etch terminates over the gate oxide layer 235 and the field oxide 230.

In Fig. 4E, a full shallow bulk high angle implant of boron (high angle implant to introduce channels under the gate) is performed, with a dose ranging from 1E12 to 1E14, and an optimum dose of 1E13, to prepare a P-body region 250. Alternatively, a full shallow body implant is performed at a zero degree angle and higher energy bulk implant to produce a P-body region 250. With the stacked structure of field oxide 230, gate 240 and oxide cap 245, boron ions are only implanted into the source edge of the gate. Then, in a high temperature range of 950 to 1150 degrees Celsius (the optimum temperature is 1050 degrees Celsius), the body is driven for about 60 minutes. In Figure 4F, a full shallow source-injection is performed, for example, at a dose ranging from 1E15 to 1E16 (the most suitable dose is 4E15), and As dopant ions are implanted to prepare an N+ source region 260. Then, in a high temperature range of 850 to 1000 degrees Celsius (the optimum temperature is 950 degrees Celsius), a source annealing operation is performed for about 30 minutes. In the source anneal process, depending on the gate stack, a portion of the oxygen may be used to form polysilicon oxide sidewalls on the edges of the stacked gate 240.

In FIG. 4G, a pad oxide layer 265, preferably a conformal oxide layer, having a thickness in the range of 1000 to 4000 angstroms, preferably more than 3,000 angstroms, is used as a thick mask for bulk trench etching. Selective epitaxial growth (SEG) provides insulation and provides passivated gate sidewalls in subsequent fabrication processes. Then, using a source-body local area interconnect trench mask (ie, a third mask (not shown)), performing an oxide etch and a germanium etch, opening the trench 255 to make the trench 255 have a narrow The opening and the high aspect ratio, the groove depth extends downward to access the P+ substrate 205. Then, the photoresist is removed (not shown). At a 7° tilt implant angle, a full P++ implant can be selected for implantation of heavily doped P++ at the bottom of the trench and trench sidewalls (not shown) to form a pad implant region 258 for better contact. . In Figure 4H, selective epitaxial growth (SEG) Si or SiGe, preferably P++ boron doped SEG SiGe, from source 260 to body layer 250 and deep buffer layer 215, and to the substrate are performed with heavily doped P++. 205, forming an ultra-low resistance local area interconnect 220. In Figure 4I, oxide pad etching is performed by reactive ion etching (RIE) to form a gate pad 265, with minimal over-etching, to passivate the gate sidewalls to ensure polysilicon gates. Oxides 230, 245 are retained on the bottom of the pole 240 and on the drain extension.

In Figure 4J, a slight wet oxide etch is performed to remove the oxide above the N+ source region 260. Then, Ti or Co is deposited on the top surface of the crucible to form a Ti or Co layer 275'. Then, a first self-aligned polycrystalline germanide preparation process is performed using a first Rapid Thermal Annealing (RTA) process to expose the top surface of the tantalum and Ti/TiN layer 275 over the oxide layers 265, 245, and 230. Forming a TiSi or CoSi layer 275'. The gate mask 275 is prepared using a gate mask (i.e., a fourth mask (not shown)) and a Ti/TiN wet etch. This mask is not needed if gate shielding is not required. Then, the photoresist is removed by RTA, and a second self-aligned polycrystalline germanide is used to form a TiSi ₂ or CoSi ₂ layer 275' on the top surface of the crucible. The self-aligned body-source interconnects prepared by the deuteration process have good joints, low electrical resistance, and excellent gate shielding metal to provide excellent insulation.

In Figure 4K, an interlayer dielectric (ILD) material containing oxide, nitride or oxide-nitride is deposited to form an insulating layer 280, which is then masked with a drain and gate (ie, fifth A mask (not shown) is opened to open the gate contact opening (not shown) over the insulating layer 280 and the drain contact opening 285. Low-energy contact implantation is performed with an implantation dose of phosphorus ions in the range of 5E14 to 1E16 to form a low-resistance contact region 290, and then an annealing process (preferably using RTA) is performed in N2 at 700-900 ° C for 20 seconds. 5 minutes (preferably 1 minute). In Figure 4L, a gate metal 295 with a barrier metal layer 298 is formed by thick metal deposition with a Ti/TiN liner. Then, using a metal mask (ie, a sixth mask (not shown)), metal etching is performed to form a gate metal and a gate metal on the top surface, and then the photoresist is removed and cleaned. Finally, the alloy process is completed to complete the preparation process.

In another embodiment not shown, a P+ source epitaxial layer is formed on the N++ substrate starting from the heavily doped N++ germanium substrate, and then a P- epitaxial layer is grown on the P+ source epitaxial layer. The following steps remove the trench 255 extending downward through the P- epitaxial layer and the P+ source epitaxial layer, touching the N++ substrate, and the others are similar to the process steps shown in FIGS. 4B-4K.

According to the above-mentioned component structure, since a small wafer is used, the trench source body is interconnected without lateral diffusion of the sinker contact region, the cell pitch is reduced, thereby obtaining a lower effective wafer cost and reducing the preparation. cost. This reduced cost can compensate for higher manufacturing costs. More importantly, the substrate source connector is used, and the source-body interconnect structure surrounded by the P++ pad implant region is configured to minimize the source resistance and achieve a very low source inductance. In addition, the small pitch of the components as described above further reduces the specific on-resistance (Rsp) at a given operating voltage. The component structure can be easily adjusted to suit its design and operation for components requiring high and low voltage ranges.

Thus, the top-drain LDMOS device with reverse ground-source as described above allows vertical current to pass through the vertical channel, and the controlled drift length of the drift region of the vertical channel is configured so that a small, measurable unit cell can be prepared spacing. The source resistance is reduced by direct contact of the source tab at the bottom of the trench with the heavily doped substrate. Therefore, it is no longer necessary to configure a deep resistance sinking zone or a trench joint like a conventional bottom source FET component.

105. . . P+ substrate

110. . . P-epitaxial layer

115. . . Body area

120. . . Deep trench

125. . . Bungee drifting area

128. . . P++ linear injection area

130. . . Field oxide

135. . . Gate oxide

140. . . Stacked planar gate

160. . . Source area

165. . . Gate gasket

170-G. . . Gate shielding metal

170-S. . . Polycrystalline telluride moiety

180. . . BPSG layer

185. . . Passivation layer

190. . . N+ doped region

198. . . Ti/TiN linear barrier

199. . . Top bungee metal

Claims (19)

A top-dip laterally diffused metal oxide field effect semiconductor (TD-LDMOS) device formed on a semiconductor substrate, comprising:
a source electrode disposed on a bottom surface of the semiconductor substrate;
a source region and a drain region are disposed on two opposite sides of a planar gate on a top surface of the semiconductor substrate, wherein the source region is enclosed in a body region, and the body region is at the planar gate Between the lower source region and the drain region, as a lateral current channel; and at least one trench is filled with a conductive material, and extends vertically downward from the body region near the top surface of the semiconductor substrate, and is disposed The source electrode on the bottom surface of the semiconductor substrate is in electrical contact. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 1, wherein:
The semiconductor substrate includes a P+ substrate carrying a P epitaxial layer, and a source and a drain region of an N-type dopant are formed in the vicinity of a top surface of the semiconductor substrate. The top bungee laterally diffused metal oxide field effect semiconductor device according to claim 1 or 2, wherein:
The trench filled with a conductive material includes selectively epitaxially growing SEG 矽 or SEG 矽 矽 SiGe. The top bungee lateral diffusion metal oxide field effect semiconductor device as described in claim 1 of the patent application, further comprising:
A heavily doped pad implant region is disposed below the bottom of the trench and around the sidewall of the trench. The top bungee laterally diffused metal oxide field effect semiconductor device as described in claim 2, further comprising:
A P++ pad implant region is disposed below the bottom of the trench and around the sidewall of the trench. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 1, wherein:
A trench filled with metal, the metal acts as a conductive material in the trench. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 6, wherein:
Tungsten filled with tungsten, which acts as a conductive material in the trench. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 7, wherein:
The trench further includes a metal liner layer formed on the bottom surface of the trench. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 1, wherein:
The trench is a narrow, deep trench with a high depth to width ratio from 10 to 25. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 1, wherein:
The top drain laterally diffused metal oxide field effect semiconductor device is configured in a closed cell layout. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 1, wherein:
The semiconductor substrate further includes a heavily doped layer having a conductivity type opposite to that of the body region. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 1, wherein:
The semiconductor substrate further includes a deep buffer layer implanted with a dopant, the conductivity type of the dopant being the same as the conductivity type of the semiconductor region. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 1, wherein:
The top drain laterally diffused metal oxide field effect semiconductor includes a P-channel element formed in the N+ germanium substrate. The top bungee laterally diffused metal oxide field effect semiconductor device of claim 1, wherein:
The planar gate further comprises a stacked planar gate, the lower pad has a gate oxide layer, is covered by a gate cover oxide, and is surrounded by a sidewall spacer layer. The top bungee lateral diffusion metal oxide field effect semiconductor device according to claim 14 of the patent application scope, further comprising:
a gate shielding layer composed of a metal layer overlying the gate cap oxide and the sidewall spacer layer, wherein the gate shielding layer extends further to a top surface above the source region, and is processed to be self-aligned A polycrystalline germanide layer for electrically conductively interface between the source region and a top metal source. A semiconductor power device includes:
a gate disposed on a top surface of a semiconductor substrate for controlling a current path between a source region and a drain region, the source region and the drain region being disposed adjacent to a top surface of the semiconductor substrate And a trench filled with a conductive material extending downward for shorting the source region to a source electrode disposed on a bottom surface of the semiconductor substrate. A method of fabricating a semiconductor power device on a semiconductor substrate, comprising:
Forming a body region and a drain region surrounding a source region, and having a gate on a top surface of the semiconductor substrate for controlling the source region and the drain region near the top surface of the semiconductor substrate a lateral current path in the body region; and opening a trench extending downward from the body region to the source electrode on the bottom surface of the semiconductor substrate, and filling the trench with a conductive material for use as a body - Source interconnection. The method of claim 17, wherein the step of filling the trench with a conductive material comprises:
The trench is filled with a conductive material containing selective epitaxial growth (SEG) germanium or selective epitaxial growth of germanium telluride (SiGe). For example, the method described in claim 17 includes:
A heavily doped pad region is implanted under the bottom of the trench and around the sidewall of the trench.