TW201312763A - Die package - Google Patents

Abstract

A die package includes a circuit board, a pad formed on the circuit board, an adhesive layer adhered to the pad, and a die adhered to the adhesive layer. The circuit board includes a substrate and a circuit layer formed on the substrate. The pad includes an electrical connection area electrically connected to the circuit layer, and an extending area extending outward the electrical connection area and located within the substrate. The die includes two spaced die areas and an enlarging area extending from each of the die areas and extending along a direction away from the circuit layer. Each of the die areas has a light-emitting element or a light-receiving element electrically connected to the electrical connection area.

Description

Chip package

This invention relates to wafer packaging, and more particularly to a chip package for use in a fiber optic connection transmission system.

Light Peak is Intel's next generation transmission interface, and the program will become USB 4.0. Its advantages are many, the most important is its high transmission rate.

Each light-emitting or light-receiving wafer used by Light Peak, such as a laser diode (LD) or a photodiode (PD), has a very small area, such as a commonly used LD size. It is about 200um × 200um. In the process of chip packaging, it is necessary to use glue. When the wafer is small, the pad under the wafer (PAD) will be small, so it will be very difficult to apply glue. It will be quite difficult to control, and the problem of overflowing glue will be quite serious. In addition, the fluidity of the glue may cause the wafer position to shift or cause a serious tilt during the curing process of the glue. This is very serious because Light Peak requires very high precision, so the problem of glue can cause a serious drop in the yield of the entire product.

In view of this, it is necessary to provide a chip package.

A chip package comprising: a circuit board, a pad formed on the circuit board, a glue layer adhered to the pad, and a wafer adhered to the glue layer. The circuit board includes a substrate and a circuit layer formed on the substrate. The pad includes an electrical connection region electrically connected to the circuit layer, and an extension region extending from the periphery of the electrical connection region and falling within the range of the substrate. The wafer includes two spaced apart wafer regions, and an expansion region extends from a periphery of each of the wafer regions and extends away from the circuit layer, each of the wafer regions including a light-emitting element or a light-emitting element. It is connected to the electrical connection zone.

Compared with the prior art, the extended area of the wafer provided by the invention increases the overall area of the wafer, and the area of the pad also increases, so that the wafer is glued and fixed on the pad, that is, the difficulty of coating is reduced, and the control is facilitated. Apply glue to avoid spillage. The expansion region extends away from the circuit layer so as not to affect the wiring arrangement of the entire chip package and the high frequency characteristics of the wafer.

Referring to FIG. 1 to FIG. 3, a chip package 100 according to a first embodiment of the present invention includes a circuit board 10, a pad 20 formed on the circuit board 10, and a glue layer 30 adhered to the pad. And a wafer 40 adhered to the glue layer 30.

The circuit board 10 has a substrate 11 and a circuit layer 12 formed on the substrate 11. The circuit layer 12 can be plated with copper wires on the substrate 11. The gasket 20 can be formed on the circuit board 10 by soldering. The wafer 40 can be connected to the pad 20 by wire bonding to be electrically connected to the circuit board 10.

The pad 20 includes an electrical connection region 22 electrically connected to the circuit layer 12, and an extension region 24 extends from the periphery of the electrical connection region 22 and falls within the range of the substrate 11. The material of the extension region 24 may be the same as or different from the material of the electrical connection region 22. In order to electrically connect to the circuit board 10, the electrical connection region 22 is made of a metallic material or made of a metallic material.

The wafer 40 includes two spaced apart wafer regions 44 and an expanded region 42. Each of the wafer areas 44 contains a light-emitting element or a light-receiving element. The light emitting element may be a laser diode (LD), and the light receiving element may be a photodiode (PD). In this embodiment, the two wafer regions 44 each contain a light-emitting element, and each of the light-emitting elements is an LD having a size of about 200 um x 200 um. The expansion region 42 extends from the periphery of each of the wafer regions 44 by a colloidal filler or a metallic filler and further extends away from the circuit layer 12.

The wafer region 44 is electrically connected to the electrical connection region 22 of the gasket 20. Due to the extended area 42 and the extended area 24, the length and width of the wafer 40 can be substantially the same as the length and width of the spacer 20, and the wafer 40 is placed in line with the length and width of the spacer 20.

Each PD or LD has a bandwidth of about 10 Gb/s. The two PDs or LDs work side by side to achieve a transmission speed of 17 Gb/s or more, which can meet Intel's Light Peak design requirements. In other embodiments, more than two PDs or LDs may be operated side by side to achieve higher transmission speeds.

The expansion area 42 of the wafer 40 increases the overall area of the wafer 40, and the area of the gasket 20 also increases. This facilitates the adhesive bonding of the wafer 40 to the liner 20, that is, the difficulty of coating the glue, and the control of the coating. Quantity, avoid spillage. The extension region 42 extends away from the circuit layer 12 such that it does not affect the line arrangement of the entire chip package 100 and the high frequency characteristics of the wafer 40.

In the case of increasing the area of the wafer 40 and the spacer 20, the area of the adhesive layer 30 may be substantially the same as the area of the wafer 40 or slightly smaller than the area of the wafer 40.

Referring to FIG. 4, the wafer package 200 provided by the second embodiment of the present invention is different from the wafer 100 provided by the first embodiment in that the overall area of the wafer 40 is smaller than the area of the spacer 20, and the wafer 40 is coated with an appropriate amount. The sealant 50 is more securely packaged on the liner 20. The increased area of the wafer 40 and liner 20 also facilitates application of the surrounding sealant 50.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100,200. . . Chip package

10. . . Circuit board

20. . . pad

30. . . Glue layer

40. . . Wafer

11. . . Substrate

12. . . Circuit layer

44. . . Wafer area

42. . . Expansion area

twenty two. . . Electrical connection zone

twenty four. . . Extended area

50. . . Plastic closures

1 is a perspective view of a chip package provided by a first embodiment of the present invention.

Figure 2 is a cross-sectional view taken along line II-II of Figure 1.

Figure 3 is a cross-sectional view taken along line III-III of Figure 1.

4 is a cross-sectional view of a chip package provided by a second embodiment of the present invention.

100. . . Chip package

20. . . pad

30. . . Glue layer

40. . . Wafer

11. . . Substrate

12. . . Circuit layer

44. . . Wafer area

42. . . Expansion area

twenty two. . . Electrical connection zone

twenty four. . . Extended area

Claims (9)

A chip package comprising:
a circuit board;
a pad formed on the circuit board;
a glue layer adhered to the liner; and a wafer adhered to the adhesive layer; the improvement is that the circuit board comprises a substrate and a circuit layer formed on the substrate, the gasket comprising an electrical connection Electrically connected to the circuit layer, and an extension region extending from the periphery of the electrical connection region and falling within the range of the substrate, the wafer includes two spaced apart wafer regions, and an extended region from each of the wafers The periphery of the region extends and extends away from the circuit layer, and each of the wafer regions includes a light-emitting element or a light-emitting element electrically connected to the electrical connection region. The chip package of claim 1, wherein the two wafer regions each comprise the light-emitting element or both comprise the light-receiving element. The chip package of claim 2, wherein the light-emitting element is a laser diode, and the light-receiving element is a photodiode. The chip package of claim 1, wherein the expansion region is filled with a filler. The chip package of claim 4, wherein the filler is selected from a colloidal material or a metallic material. The chip package of claim 1, wherein: the length and width dimensions of the wafer are the same as the length and width of the liner, and the wafer is placed in alignment with the liner. The chip package of claim 1, wherein: the area of the wafer is smaller than the area of the pad. The chip package of claim 6 or 7, wherein the area of the glue layer is equal to or smaller than the area of the wafer. The chip package of claim 7, wherein the wafer is coated with a sealant.