TW201314848A - Semiconductor package with heat dissipation structure and manufacturing method thereof - Google Patents
Semiconductor package with heat dissipation structure and manufacturing method thereof Download PDFInfo
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- TW201314848A TW201314848A TW100133648A TW100133648A TW201314848A TW 201314848 A TW201314848 A TW 201314848A TW 100133648 A TW100133648 A TW 100133648A TW 100133648 A TW100133648 A TW 100133648A TW 201314848 A TW201314848 A TW 201314848A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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Abstract
Description
本發明係關於一種半導體封裝及其製造方法,特別係關於一種具有散熱結構之半導體封裝及其製造方法。The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having a heat dissipation structure and a method of fabricating the same.
圖1A顯示習知半導體封裝之剖視圖。該半導體封裝60為了提昇散熱效能,係會在一晶粒61上設置一散熱件62,而該晶粒61與該散熱件62之間亦會設置一導熱膠63,以利該晶粒61的熱傳導至該散熱件62,惟,該導熱膠63係受限於自身材料特性,其導熱效果仍然有限。1A shows a cross-sectional view of a conventional semiconductor package. In order to improve the heat dissipation performance, the semiconductor package 60 is provided with a heat dissipating member 62 on the die 61, and a thermal conductive paste 63 is disposed between the die 61 and the heat sink 62 to facilitate the die 61. The heat is conducted to the heat sink 62. However, the heat conductive paste 63 is limited by its own material properties, and its heat conduction effect is still limited.
另外,習知半導體封裝60之該散熱片62主要是透過一散熱膠64黏合於一散熱環65,藉由控制該散熱膠64壓合後之寬度可將翹曲程度控制在適當範圍內,惟,習知點膠方法通常只能控制該散熱膠64壓合後之覆蓋面積,無法有效控制該散熱膠64壓合後之寬度,其接合效果控制不易。In addition, the heat sink 62 of the conventional semiconductor package 60 is mainly bonded to a heat dissipation ring 65 through a heat dissipation adhesive 64. By controlling the width of the heat dissipation adhesive 64 after pressing, the degree of warpage can be controlled within an appropriate range. The conventional dispensing method generally only controls the coverage area of the heat-dissipating adhesive 64 after pressing, and cannot effectively control the width of the heat-dissipating adhesive 64 after pressing, and the joint effect is difficult to control.
如上所述,為符合高散熱需求之半導體封裝,近年來開始使用金屬導熱材料,例如銦片,因其具有絕佳之導熱性及延展性,可大幅提升導熱效果。銦片在使用上必須與具有鍍金層之介質在經過特定溫度,使銦片表面熔融後,才能與鍍金層形成金屬鍵結,達到有效接合效果。As described above, in order to meet the high heat dissipation requirements of semiconductor packages, metal heat conductive materials such as indium sheets have been used in recent years, and since they have excellent thermal conductivity and ductility, the heat conduction effect can be greatly improved. Indium flakes must be used in combination with a medium having a gold plating layer to melt the surface of the indium flakes to form a metal bond with the gold plating layer to achieve an effective bonding effect.
圖1B顯示一銦片使用於習知半導體封裝60之高溫狀態示意圖。一銦片I在高溫接合過程中,係會因熔融態而具有流動性,而該銦片I的流動意味著其無法有效黏合於該散熱片62,導熱效果將大幅降低,此外,四處流動的銦片I亦可能造成半導體封裝60的內部電性短路。FIG. 1B shows a schematic view of a high temperature state of an indium wafer used in a conventional semiconductor package 60. The indium sheet I has fluidity due to the molten state during the high-temperature bonding process, and the flow of the indium sheet I means that it cannot be effectively bonded to the heat sink 62, and the heat conduction effect is greatly reduced, and in addition, the flow is everywhere. The indium sheet I may also cause an internal electrical short circuit of the semiconductor package 60.
另外,上述半導體封裝的翹曲程度亦會嚴重影響銦片與鍍金層之接合效果,因此,使用銦片之半導體封裝必須將翹曲程度控制在適當範圍內。In addition, the degree of warpage of the above semiconductor package may also seriously affect the bonding effect between the indium sheet and the gold plating layer. Therefore, the semiconductor package using the indium sheet must control the degree of warpage within an appropriate range.
有鑑於此,有必要提供一創新且具進步性之半導體封裝及其製造方法,以解決上述問題。In view of this, it is necessary to provide an innovative and progressive semiconductor package and its manufacturing method to solve the above problems.
本發明係於一半導體封裝之散熱件上形成一攔壩,圍繞一金屬導熱件,確保該金屬導熱件在經過高溫後製程時,能被限位在該攔壩內,進而防止該金屬導熱件之流動,避免半導體封裝內部的電性短路。The invention forms a dam on a heat sink of a semiconductor package, and surrounds a metal heat conductive member to ensure that the metal heat conductive member can be restrained in the dam when the process is subjected to high temperature, thereby preventing the metal heat conductive member. The flow prevents electrical shorts inside the semiconductor package.
本發明在於提供一種半導體封裝,包括一第一基板、一第一晶粒、一金屬導熱件以及一散熱件,該第一基板具有一上表面,該第一晶粒設置於該第一基板之上表面,該第一晶粒具有一頂面及一第一接合層,該第一接合層設置於該頂面,該金屬導熱件設置於該第一晶粒之第一接合層上,該散熱件設置於該金屬導熱件上,該散熱件具有一內表面、一第二接合層及一攔壩,該第二接合層及該攔壩設置於該內表面,該第二接合層抵接該金屬導熱件,該攔壩圍繞該金屬導熱件,且該攔壩可限位該金屬導熱件。The present invention provides a semiconductor package including a first substrate, a first die, a metal heat spreader, and a heat sink. The first substrate has an upper surface, and the first die is disposed on the first substrate. On the upper surface, the first die has a top surface and a first bonding layer. The first bonding layer is disposed on the top surface, and the metal heat conducting member is disposed on the first bonding layer of the first die. The component is disposed on the metal heat conducting member, the heat sink has an inner surface, a second bonding layer and a dam, the second bonding layer and the dam are disposed on the inner surface, and the second bonding layer abuts the a metal heat conducting member, the dam surrounding the metal heat conducting member, and the dam can limit the metal heat conducting member.
本發明另提供一種半導體封裝之製造方法,該方法包括:(a)提供一第一基板及一第一晶粒,該第一基板具有一上表面,該第一晶粒設置於該第一基板之上表面,該第一晶粒具有一頂面及一第一接合層,該第一接合層形成於該頂面;(b)設置一金屬導熱件於該第一晶粒之第一接合層上;以及(c)設置一散熱件於該金屬導熱件上,該散熱件具有一內表面、一第二接合層及一攔壩,該第二接合層及該攔壩形成於該內表面,該第二接合層抵接該金屬導熱件,該攔壩圍繞該金屬導熱件,且該攔壩可限位該金屬導熱件。The present invention further provides a method of fabricating a semiconductor package, the method comprising: (a) providing a first substrate and a first die, the first substrate having an upper surface, the first die disposed on the first substrate On the upper surface, the first die has a top surface and a first bonding layer, the first bonding layer is formed on the top surface; (b) a metal heat conducting member is disposed on the first bonding layer of the first die And (c) providing a heat dissipating member on the metal heat conducting member, the heat dissipating member having an inner surface, a second bonding layer and a dam, the second bonding layer and the dam being formed on the inner surface The second bonding layer abuts the metal heat conducting member, the dam surrounds the metal heat conducting member, and the dam can limit the metal heat conducting member.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
請參閱圖2及圖2A、2B,其係分別顯示本發明一實施例之半導體封裝的結構示意圖及局部放大圖。一半導體封裝10係包括一第一基板11、一第一晶粒12、一第二晶粒13、一第二基板14、一散熱環15、一金屬導熱件20、一散熱件30以及一散熱膠40。2 and 2A and 2B are respectively a schematic structural view and a partial enlarged view of a semiconductor package according to an embodiment of the present invention. A semiconductor package 10 includes a first substrate 11, a first die 12, a second die 13, a second substrate 14, a heat sink 15, a metal heat conductor 20, a heat sink 30, and a heat sink. Glue 40.
第一基板11係為電性中介板(Interposer),具有一上表面11a以及至少一導通孔111做為對外電性連接結構。The first substrate 11 is an electrical interposer having an upper surface 11a and at least one via hole 111 as an external electrical connection structure.
第一晶粒12係為邏輯晶粒(Logical Die),具有一頂面12a及一相對於頂面12a之背面12b,在本實施例中,該背面12b具有至少一第一凸塊122做為對外電性連接結構及一第一底膠123可包覆該第一凸塊122,該第一晶粒12以覆晶方式,即該背面12b朝下之方式,設置於該第一基板11之上表面11a,且該第一晶粒12具有一第一接合層121,該第一接合層121形成於該頂面12a,且該第一接合層121係由複數個金屬層堆疊形成。The first die 12 is a logic die having a top surface 12a and a back surface 12b opposite to the top surface 12a. In this embodiment, the back surface 12b has at least one first bump 122 as An external electrical connection structure and a first primer 123 can cover the first bump 122. The first die 12 is disposed on the first substrate 11 in a flip chip manner, that is, the back surface 12b faces downward. The upper surface 11a, and the first die 12 has a first bonding layer 121 formed on the top surface 12a, and the first bonding layer 121 is formed by stacking a plurality of metal layers.
第二晶粒13係為記憶體晶粒(Memory Die),具有一上端面13a及一相對於該上端面13a之一下端面13b,在本實施例中,該下端面13b具有至少一第二凸塊131做為對外電性連接結構及一第二底膠132可包覆該第二凸塊131,該第二晶粒13以覆晶方式,即該下端面13b朝下之方式,設置於該第一基板11之上表面11a,且位於該第一晶粒12之一側。The second die 13 is a memory die having an upper end surface 13a and a lower end surface 13b opposite to the upper end surface 13a. In the embodiment, the lower end surface 13b has at least one second convex portion. The block 131 is used as an external electrical connection structure and a second primer 132 can cover the second bump 131. The second die 13 is disposed on the flip chip, that is, the lower end surface 13b faces downward. The upper surface 11a of the first substrate 11 is located on one side of the first die 12.
第二基板14係具有一中間區塊141及一周邊區塊142,在本實施例中,該第一基板11係設置於該第二基板14之中間區塊141。The second substrate 14 has an intermediate block 141 and a peripheral block 142. In the embodiment, the first substrate 11 is disposed in the middle block 141 of the second substrate 14.
散熱環15具有一第一表面15a、一相對之第二表面15b及一溝槽結構151,該第二表面15b係固定於該第二基板14之周邊區塊142,而該溝槽結構151係凹設於該第一表面15a,較佳地,該溝槽結構151係具有至少二溝槽U。The heat dissipation ring 15 has a first surface 15a, an opposite second surface 15b, and a groove structure 151. The second surface 15b is fixed to the peripheral block 142 of the second substrate 14. The groove structure 151 is The recessed structure is preferably recessed on the first surface 15a. Preferably, the trench structure 151 has at least two trenches U.
金屬導熱件20設置於該第一晶粒12之第一接合層121上,在本實施例中,該金屬導熱件20係可為銦片(Indium)或其它導熱性佳之金屬材料,且該金屬導熱件20之表面積至少不小於該第一晶粒12之表面積。The metal heat conducting member 20 is disposed on the first bonding layer 121 of the first die 12, and in the embodiment, the metal heat conducting member 20 can be an indium plate or other metal material with good thermal conductivity, and the metal The surface area of the heat conducting member 20 is at least not less than the surface area of the first die 12.
散熱件30設置於該散熱環15及該金屬導熱件20上,在本實施例中,為使該散熱件30固定於該散熱環15上,該散熱件30具有一內表面30a、一第二接合層31及一攔壩32,該內表面30a係為粗糙表面,該第二接合層31及該攔壩32形成於該內表面30a,且該第二接合層31抵接該金屬導熱件20,在本實施例中,該第二接合層31係為金(Au),且較佳地,該第二接合層31的表面積至少不小於該金屬導熱件之表面積,且該第二接合層31的表面係為粗糙表面,用以增加該第二接合層31與該金屬導熱件20之接合強度。該攔壩32圍繞該第二接合層31及該金屬導熱件20,不會影響該金屬導熱件20與該第二接合層31接觸之面積,亦即不會影響該金屬導熱件之導熱效果,且該攔壩32可限位該金屬導熱件20,在本實施例中,該金屬導熱件20係位於該攔壩32內,且該攔壩32與該金屬導熱件20之間係具有一間隙Y,較佳地,該間隙Y係介於50至250微米之間,該攔壩32的高度H係大於該第二接合層31的厚度,且該攔壩32的高度H係不小於該金屬導熱件20之一半厚度,較佳地,該攔壩32的高度H係介於100至650微米之間,而該攔壩32的寬度W係介於100至600微米之間。另外,在本實施例中,該攔壩32係由膠材形成。或者,在另一實施例中,該散熱件30係可一體形成該攔壩32。The heat dissipating member 30 is disposed on the heat dissipating ring 15 and the metal heat conducting member 20. In the embodiment, the heat dissipating member 30 has an inner surface 30a and a second portion. The bonding layer 31 and a dam 32 are rough surfaces, the second bonding layer 31 and the dam 32 are formed on the inner surface 30a, and the second bonding layer 31 abuts the metal heat conducting member 20 In this embodiment, the second bonding layer 31 is made of gold (Au), and preferably, the surface area of the second bonding layer 31 is at least not less than the surface area of the metal heat conducting member, and the second bonding layer 31 The surface is a rough surface for increasing the bonding strength of the second bonding layer 31 and the metal heat conductive member 20. The dam 32 surrounds the second bonding layer 31 and the metal heat conducting member 20, and does not affect the contact area of the metal heat conducting member 20 with the second bonding layer 31, that is, does not affect the heat conduction effect of the metal heat conducting member. The dam 32 can be limited to the metal heat conducting member 20. In the embodiment, the metal heat conducting member 20 is located in the dam 32, and the dam 32 has a gap between the metal heat conducting member 20 and the metal heat conducting member 20. Y, preferably, the gap Y is between 50 and 250 microns, the height H of the dam 32 is greater than the thickness of the second bonding layer 31, and the height H of the dam 32 is not less than the metal One half of the thickness of the heat conducting member 20, preferably, the height H of the dam 32 is between 100 and 650 microns, and the width W of the dam 32 is between 100 and 600 microns. Further, in the present embodiment, the dam 32 is formed of a rubber material. Alternatively, in another embodiment, the heat sink 30 can integrally form the dam 32.
散熱膠40可另設置於該散熱環15與該散熱件30之間,在本實施例中,該散熱膠40係具有一第一部份41及一第二部分42,該散熱膠40之第一部份41係位於該散熱環15之溝槽結構151內,而該散熱膠40之第二部份42係位於該散熱環15之第一表面15a與該散熱件30之間。此外,由於該溝槽結構151具有該二溝槽U,因此,可將該散熱膠40壓合後之寬度控制在所需範圍內。The heat dissipating adhesive 40 can be disposed between the heat dissipating ring 15 and the heat dissipating member 30. In the embodiment, the heat dissipating adhesive 40 has a first portion 41 and a second portion 42. A portion 41 is located in the trench structure 151 of the heat dissipating ring 15 , and a second portion 42 of the heat dissipating adhesive 40 is located between the first surface 15 a of the heat dissipating ring 15 and the heat sink 30 . In addition, since the trench structure 151 has the two trenches U, the width of the heat-dissipating adhesive 40 after pressing can be controlled within a desired range.
圖3顯示本發明第一接合層121之多種實施態樣圖。請參閱圖3,在本實施例中,該第一接合層121係有以下幾種實施態樣:態樣A:該些金屬層由下至上依序為鈦(Ti)/銅(Cu)/銅(Cu)/鎳(Ni)/鈀(Pd)/金(Au)。其中鈦(Ti)層係為阻障層,第一銅(Cu)層係為種子層,第二銅(Cu)層係為緩衝層,鎳(Ni)層係為銅擴散阻障層,鈀(Pd)層係為黏著層,金(Au)層係為銲層,較佳地,鈦(Ti)層的厚度係介於0.1至0.5微米之間,第一銅(Cu)層的厚度係介於0.1至0.5微米之間,第二銅(Cu)層的厚度係介於3至50微米之間,鎳(Ni)層的厚度係介於1至3微米之間,鈀(Pd)層的厚度係介於0.1至0.5微米之間,金(Au)層的厚度係介於0.1至0.5微米之間;態樣B:該些金屬層由下至上依序為鈦(Ti)/銅(Cu)/銅(Cu)/鎳(Ni)/鈀(Pd)。態樣B基本上與態樣A相同,其差異處僅在於態樣B省略金(Au)層(銲層);態樣C:該些金屬層由下至上依序為鈦(Ti)/銅(Cu)/鎳(Ni)/鈀(Pd)/金(Au)。態樣C基本上與態樣A相同,其差異處僅在於態樣C省略第二銅(Cu)層(緩衝層);態樣D:該些金屬層由下至上依序為鈦(Ti)/銅(Cu)/鎳(Ni)/鈀(Pd)。態樣D基本上與態樣C相同,其差異處僅在於態樣D省略金(Au)層(銲層);態樣E:該些金屬層由下至上依序為鈦(Ti)/銅(Cu)/銅(Cu)/鎳(Ni)/錫銀(SnAg)。態樣E基本上與態樣B相同,其差異處僅在於態樣E係以錫銀(SnAg)層取代鈀(Pd)層;態樣F:該些金屬層由下至上依序為鈦(Ti)/銅(Cu)/鎳(Ni)/金(Au)。態樣F基本上與態樣D相同,其差異處僅在於態樣F係以金(Au)層取代鈀(Pd)層;及態樣G:該些金屬層由下至上依序為鈦(Ti)/銅(Cu)/銅(Cu)/鎳(Ni)/金(Au)。態樣G基本上與態樣B相同,其差異處僅在於態樣G係以金(Au)層取代鈀(Pd)層。Fig. 3 shows various embodiments of the first bonding layer 121 of the present invention. Referring to FIG. 3, in the embodiment, the first bonding layer 121 has the following implementations: Aspect A: The metal layers are sequentially Ti(Ti)/Copper (Cu) from bottom to top. Copper (Cu) / nickel (Ni) / palladium (Pd) / gold (Au). The titanium (Ti) layer is a barrier layer, the first copper (Cu) layer is a seed layer, the second copper (Cu) layer is a buffer layer, and the nickel (Ni) layer is a copper diffusion barrier layer, palladium. The (Pd) layer is an adhesive layer, and the gold (Au) layer is a solder layer. Preferably, the thickness of the titanium (Ti) layer is between 0.1 and 0.5 μm, and the thickness of the first copper (Cu) layer is Between 0.1 and 0.5 micron, the thickness of the second copper (Cu) layer is between 3 and 50 microns, and the thickness of the nickel (Ni) layer is between 1 and 3 microns, palladium (Pd) layer The thickness of the gold (Au) layer is between 0.1 and 0.5 microns; the aspect B: the metal layer is titanium (Ti) / copper in order from bottom to top ( Cu) / copper (Cu) / nickel (Ni) / palladium (Pd). The aspect B is basically the same as the aspect A, and the difference is only in the case B, the gold (Au) layer (welding layer) is omitted; the aspect C: the metal layers are sequentially ordered from titanium (Ti)/copper from bottom to top. (Cu) / nickel (Ni) / palladium (Pd) / gold (Au). The aspect C is basically the same as the aspect A, and the difference is only that the second copper (Cu) layer (buffer layer) is omitted from the aspect C; the aspect D: the metal layers are sequentially titanium (Ti) from bottom to top. / copper (Cu) / nickel (Ni) / palladium (Pd). The aspect D is basically the same as the aspect C, the difference is only in the case D omitting the gold (Au) layer (welding layer); the aspect E: the metal layers are sequentially ordered from the bottom to the top (Ti) / copper (Cu) / copper (Cu) / nickel (Ni) / tin silver (SnAg). The aspect E is basically the same as the state B, and the difference is only in the case that the E is replaced by a tin-silver (SnAg) layer instead of the palladium (Pd) layer; the aspect F: the metal layers are sequentially titanium from bottom to top ( Ti) / copper (Cu) / nickel (Ni) / gold (Au). The aspect F is substantially the same as the aspect D, and the difference is only in the fact that the F-type replaces the palladium (Pd) layer with a gold (Au) layer; and the aspect G: the metal layers are sequentially titanium from bottom to top ( Ti) / copper (Cu) / copper (Cu) / nickel (Ni) / gold (Au). The aspect G is substantially the same as the aspect B, and the difference is only in the case where the G system replaces the palladium (Pd) layer with a gold (Au) layer.
圖4顯示本發明一實施例之攔壩之結構示意圖。攔壩32係可為方框體。4 is a schematic view showing the structure of a dam according to an embodiment of the present invention. The dam 32 series can be a box body.
圖5顯示本發明另一實施例之攔壩之結構示意圖。攔壩32係具有四個條狀體321,該些條狀體321係彼此分離,且排列成一方框形狀。Fig. 5 is a schematic view showing the structure of a dam according to another embodiment of the present invention. The dam 32 has four strips 321 which are separated from each other and arranged in a square shape.
圖6顯示本發明又一實施例之攔壩之結構示意圖。攔壩32係具有複數個點狀體32a,該些點狀體32a係間隔排列成一方框形狀。Fig. 6 is a schematic view showing the structure of a dam according to still another embodiment of the present invention. The dam 32 has a plurality of dot-shaped bodies 32a which are arranged in a square shape at intervals.
圖7A至7D顯示依據本發明一實施例之半導體封裝之製造流程圖。7A through 7D are diagrams showing the fabrication of a semiconductor package in accordance with an embodiment of the present invention.
如7A圖所示,提供一第一基板11、一第一晶粒12、一第二晶粒13、一第二基板14及一散熱環15,在本實施例中,該第一基板11係為電性中介板(Interposer),該第一晶粒12係為邏輯晶粒(Logical Die),而該第二晶粒13係為記憶體晶粒(Memory Die)。該第一基板11具有一上表面11a,該第一晶粒12設置於該第一基板11之上表面11a,且該第一晶粒12具有一頂面12a及一第一接合層121,在本實施例中,該第一接合層121形成於該頂面12a,且該第一接合層121係由複數個金屬層堆疊形成。As shown in FIG. 7A, a first substrate 11, a first die 12, a second die 13, a second substrate 14, and a heat dissipation ring 15 are provided. In this embodiment, the first substrate 11 is provided. For the electrical interposer, the first die 12 is a logic die, and the second die 13 is a memory die. The first substrate 11 has an upper surface 11a. The first die 12 is disposed on the upper surface 11a of the first substrate 11. The first die 12 has a top surface 12a and a first bonding layer 121. In this embodiment, the first bonding layer 121 is formed on the top surface 12a, and the first bonding layer 121 is formed by stacking a plurality of metal layers.
該第二晶粒13係設置於該第一基板11之上表面11a,且位於該第一晶粒12之一側,該第二基板14係具有一中間區塊141及一周邊區塊142,在本實施例中,該第一基板11係設置於該第二基板14之中間區塊141,而該散熱環15係固定於該第二基板14之周邊區塊142。此外,該散熱環15係具有一第一表面15a、一相對之第二表面15b及一溝槽結構151,該第二表面15b係固定於該第二基板14之周邊區塊142,而該溝槽結構151係凹設於該第一表面15a,較佳地,該溝槽結構151係具有至少二溝槽U。The second die 13 is disposed on the upper surface 11a of the first substrate 11 and is located on one side of the first die 12, and the second substrate 14 has an intermediate block 141 and a peripheral block 142. In this embodiment, the first substrate 11 is disposed on the middle block 141 of the second substrate 14 , and the heat dissipation ring 15 is fixed to the peripheral block 142 of the second substrate 14 . In addition, the heat dissipation ring 15 has a first surface 15a, an opposite second surface 15b, and a groove structure 151. The second surface 15b is fixed to the peripheral block 142 of the second substrate 14. The groove structure 151 is recessed on the first surface 15a. Preferably, the groove structure 151 has at least two grooves U.
如圖7B所示,設置一金屬導熱件20於該第一晶粒12之第一接合層121上,在本實施例中,該金屬導熱件20係可為銦片(Indium)或其它導熱性佳之金屬材料。As shown in FIG. 7B, a metal heat conducting member 20 is disposed on the first bonding layer 121 of the first die 12. In the embodiment, the metal heat conducting member 20 can be an indium plate or other thermal conductivity. Good metal materials.
如圖7C所示,設置一散熱件30於該金屬導熱件20上,在此步驟中,更包括設置該散熱件30於該散熱環15上,且為使該散熱件30固定於該散熱環15上,另可設置一散熱膠40於該散熱環15與該散熱件30之間,在本實施例中,該散熱膠40係具有一第一部份41及一第二部分42,該散熱膠40之第一部份41係位於該散熱環15之溝槽結構151內,而該散熱膠40之第二部份42係位於該散熱環15之第一表面15a與該散熱件30之間。此外,由於該溝槽結構151具有該二溝槽U,因此,可將該散熱膠40壓合後之寬度控制在所需範圍內。As shown in FIG. 7C, a heat dissipating member 30 is disposed on the metal heat conducting member 20, and in this step, the heat dissipating member 30 is further disposed on the heat dissipating ring 15, and the heat dissipating member 30 is fixed to the heat dissipating ring. In the embodiment, the heat dissipating adhesive 40 is disposed between the heat dissipating ring 15 and the heat dissipating member 30. In the embodiment, the heat dissipating adhesive 40 has a first portion 41 and a second portion 42. The first portion 41 of the adhesive 40 is located in the trench structure 151 of the heat dissipating ring 15 , and the second portion 42 of the heat dissipating adhesive 40 is located between the first surface 15 a of the heat dissipating ring 15 and the heat sink 30 . . In addition, since the trench structure 151 has the two trenches U, the width of the heat-dissipating adhesive 40 after pressing can be controlled within a desired range.
如圖7C所示,該散熱件30具有一內表面30a、一第二接合層31及一攔壩32,該內表面30a係為粗糙表面,在本實施例中,該粗糙表面係可以電漿表面處理方法或噴砂方法形成。該第二接合層31及該攔壩32形成於該內表面30a,且該第二接合層31抵接該金屬導熱件20,在本實施例中,該第二接合層31係為金(Au),且較佳地,該第二接合層31的表面係為粗糙表面,用以增加該第二接合層31與該金屬導熱件20之接合強度。該攔壩32圍繞該第二接合層31,且該攔壩32可限位該金屬導熱件20,在本實施例中,該金屬導熱件20係位於該攔壩32內。另外,在本實施例中,該攔壩32係由膠材形成。或者,在另一實施例中,該散熱件30係可一體形成該攔壩32。As shown in FIG. 7C, the heat dissipating member 30 has an inner surface 30a, a second bonding layer 31 and a dam 32. The inner surface 30a is a rough surface. In the embodiment, the rough surface can be plasma. A surface treatment method or a sandblasting method is formed. The second bonding layer 31 and the dam 32 are formed on the inner surface 30a, and the second bonding layer 31 abuts the metal heat conducting member 20. In the embodiment, the second bonding layer 31 is gold (Au And preferably, the surface of the second bonding layer 31 is a rough surface for increasing the bonding strength of the second bonding layer 31 and the metal heat conducting member 20. The dam 32 surrounds the second joint layer 31, and the dam 32 can limit the metal heat conducting member 20. In the embodiment, the metal heat conducting member 20 is located in the dam 32. Further, in the present embodiment, the dam 32 is formed of a rubber material. Alternatively, in another embodiment, the heat sink 30 can integrally form the dam 32.
圖7D所示,另包括進行一回銲步驟,以使該金屬導熱件20熔融接合於該第一晶粒12之第一接合層121及該散熱件30之第二接合層31,由於該攔壩32係圍繞該金屬導熱件20,因此,可確保該金屬導熱件20在高溫回銲過程中能被限位在該攔壩32內,進而可防止該金屬導熱件20之流動。As shown in FIG. 7D, the method further includes performing a reflow step to fuse the metal heat conducting member 20 to the first bonding layer 121 of the first die 12 and the second bonding layer 31 of the heat sink 30, due to the barrier The dam 32 surrounds the metal heat conducting member 20, thereby ensuring that the metal heat conducting member 20 can be restrained in the dam 32 during high temperature reflow, thereby preventing the metal heat conducting member 20 from flowing.
圖8及圖8A顯示依據本發明另一實施例之半導體封裝之狀態示意圖及局部放大圖。膠體50係用以填補該攔壩32因該散熱件30的貼合容許度所產生的間距,在本實施例中,該膠體50係包覆部分該攔壩32,且該膠體50係具有一包覆寬度X及一包覆高度Z,該包覆寬度X至少不小於攔壩32寬度和攔壩32與金屬導熱件20之間隙的總和,該包覆高度Z至少不小於第一晶粒12之一半厚度。在本實施例中,較佳地,包覆寬度X係介於450微米至700微米之間,而該包覆高度Z係介於250微米至400微米之間。8 and 8A are schematic diagrams and partial enlarged views of a semiconductor package in accordance with another embodiment of the present invention. The colloid 50 is used to fill the gap of the dam 32 due to the tolerance of the heat sink 30. In the embodiment, the colloid 50 covers a portion of the dam 32, and the colloid 50 has a a coating width X and a coating height Z, the coating width X being at least not less than a sum of a width of the dam 32 and a gap between the dam 32 and the metal heat conducting member 20, the cladding height Z being at least not less than the first crystal grain 12 Half the thickness. In this embodiment, preferably, the cladding width X is between 450 micrometers and 700 micrometers, and the cladding height Z is between 250 micrometers and 400 micrometers.
另外,在本實施例中,該第二接合層31之粗糙表面的形成步驟係可有下列幾種方式:圖9顯示本發明第二接合層之粗糙表面的第一種形成步驟示意圖。第二接合層31之粗糙表面的第一種形成步驟包括:粗化該散熱件30之內表面30a;以及形成該第二接合層31於粗化後之該內表面30a。Further, in the present embodiment, the step of forming the rough surface of the second bonding layer 31 may be in the following manners: Fig. 9 is a view showing the first forming step of the rough surface of the second bonding layer of the present invention. The first forming step of the rough surface of the second bonding layer 31 includes: roughening the inner surface 30a of the heat sink 30; and forming the inner surface 30a of the second bonding layer 31 after roughening.
圖10顯示本發明第二接合層之粗糙表面的第二種形成步驟示意圖。第二接合層31之粗糙表面的第二種形成步驟包括:形成該第二接合層31於該內表面30a;以及粗化該第二接合層31的表面及該內表面30a。Figure 10 is a view showing a second forming step of the rough surface of the second bonding layer of the present invention. The second forming step of the rough surface of the second bonding layer 31 includes: forming the second bonding layer 31 on the inner surface 30a; and roughening the surface of the second bonding layer 31 and the inner surface 30a.
圖11顯示本發明第二接合層之粗糙表面的第三種形成步驟示意圖。第二接合層31之粗糙表面的第三種形成步驟包括:形成該第二接合層31於該內表面30a;以及粗化該第二接合層31的表面。Figure 11 is a view showing a third forming step of the rough surface of the second bonding layer of the present invention. The third forming step of the rough surface of the second bonding layer 31 includes: forming the second bonding layer 31 on the inner surface 30a; and roughening the surface of the second bonding layer 31.
上述實施例僅為說明本發明之原理及其功效,並非限制本發明,因此習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the scope of the present invention. The scope of the invention should be as set forth in the appended claims.
10...半導體封裝10. . . Semiconductor package
11...第一基板11. . . First substrate
11a...上表面11a. . . Upper surface
12...第一晶粒12. . . First grain
12a...頂面12a. . . Top surface
12b...背面12b. . . back
13...第二晶粒13. . . Second grain
13a...上端面13a. . . Upper end
13b...下端面13b. . . Lower end
14...第二基板14. . . Second substrate
15...散熱環15. . . Heat ring
15a...第一表面15a. . . First surface
15b...第二表面15b. . . Second surface
20...金屬導熱件20. . . Metal heat conductor
30...散熱件30. . . Heat sink
30a...內表面30a. . . The inner surface
31...第二接合層31. . . Second bonding layer
32...攔壩32. . . Barrier
32a...點狀體32a. . . Point body
40...散熱膠40. . . Heat sink
41...第一部分41. . . first part
42...第二部分42. . . the second part
50...膠體50. . . colloid
60...習知半導體封裝結構60. . . Conventional semiconductor package structure
61...晶粒61. . . Grain
62...散熱件62. . . Heat sink
63...導熱膠63. . . Thermal adhesive
64...散熱膠64. . . Heat sink
65...散熱環65. . . Heat ring
111...導通孔111. . . Via
121...第一接合層121. . . First bonding layer
122...第一凸塊122. . . First bump
123...第一底膠123. . . First primer
131...第二凸塊131. . . Second bump
132...第二底膠132. . . Second primer
141...中間區塊141. . . Intermediate block
142...周邊區塊142. . . Peripheral block
151...溝槽結構151. . . Groove structure
321...條狀體321. . . Strip
H...高度H. . . height
I...銦片I. . . Indium tablets
U...溝槽U. . . Trench
W...寬度W. . . width
X...包覆寬度X. . . Coat width
Y...間隙Y. . . gap
Z...包覆高度Z. . . Coating height
圖1A顯示習知半導體封裝結構之結構示意圖;1A is a schematic structural view showing a conventional semiconductor package structure;
圖1B顯示銦片使用於習知半導體封裝結構之狀態示意圖;1B is a schematic view showing a state in which an indium piece is used in a conventional semiconductor package structure;
圖2顯示本發明一實施例之半導體封裝的結構示意圖;2 is a schematic structural view of a semiconductor package according to an embodiment of the present invention;
圖2A顯示本發明一實施例之半導體封裝的局部放大圖;2A is a partial enlarged view of a semiconductor package in accordance with an embodiment of the present invention;
圖2B顯示本發明一實施例之半導體封裝的另一局部放大圖;2B is another partial enlarged view of a semiconductor package in accordance with an embodiment of the present invention;
圖3顯示本發明第一接合層之多種實施態樣圖;Figure 3 shows various embodiments of the first bonding layer of the present invention;
圖4顯示本發明一實施例之攔壩之結構示意圖;4 is a schematic structural view of a dam according to an embodiment of the present invention;
圖5顯示本發明另一實施例之攔壩之結構示意圖;Figure 5 is a schematic view showing the structure of a dam according to another embodiment of the present invention;
圖6顯示本發明又一實施例之攔壩之結構示意圖;6 is a schematic structural view of a dam according to still another embodiment of the present invention;
圖7A至7D顯示依據本發明一實施例之半導體封裝之製造流程圖;7A to 7D are diagrams showing the manufacture of a semiconductor package in accordance with an embodiment of the present invention;
圖8顯示依據本發明另一實施例之半導體封裝之狀態示意圖;8 is a schematic view showing a state of a semiconductor package in accordance with another embodiment of the present invention;
圖8A顯示依據本發明另一實施例之半導體封裝之局部放大圖;8A is a partial enlarged view of a semiconductor package in accordance with another embodiment of the present invention;
圖9顯示本發明第二接合層之粗糙表面的第一種形成步驟示意圖;Figure 9 is a view showing a first forming step of the rough surface of the second bonding layer of the present invention;
圖10顯示本發明第二接合層之粗糙表面的第二種形成步驟示意圖;及Figure 10 is a view showing a second forming step of the rough surface of the second bonding layer of the present invention;
圖11顯示本發明第二接合層之粗糙表面的第三種形成步驟示意圖。Figure 11 is a view showing a third forming step of the rough surface of the second bonding layer of the present invention.
10...半導體封裝10. . . Semiconductor package
11...第一基板11. . . First substrate
11a...上表面11a. . . Upper surface
12...第一晶粒12. . . First grain
12a...頂面12a. . . Top surface
12b...背面12b. . . back
13...第二晶粒13. . . Second grain
13a...上端面13a. . . Upper end
13b...下端面13b. . . Lower end
14...第二基板14. . . Second substrate
15...散熱環15. . . Heat ring
15a...第一表面15a. . . First surface
15b...第二表面15b. . . Second surface
20...金屬導熱件20. . . Metal heat conductor
30...散熱件30. . . Heat sink
30a...內表面30a. . . The inner surface
31...第二接合層31. . . Second bonding layer
32...攔壩32. . . Barrier
40...散熱膠40. . . Heat sink
41...第一部分41. . . first part
42...第二部分42. . . the second part
121...第一接合層121. . . First bonding layer
122...第一凸塊122. . . First bump
123...第一底膠123. . . First primer
131...第二凸塊131. . . Second bump
132...第二底膠132. . . Second primer
141...中間區塊141. . . Intermediate block
142...周邊區塊142. . . Peripheral block
151...溝槽結構151. . . Groove structure
U...溝槽U. . . Trench
Claims (10)
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TWI628760B (en) * | 2016-02-17 | 2018-07-01 | 美光科技公司 | Apparatuses and methods for internal heat spreading for packaged semiconductor die |
US10153222B2 (en) | 2016-11-14 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
TWI659509B (en) * | 2017-12-19 | 2019-05-11 | 英屬開曼群島商鳳凰先驅股份有限公司 | Electronic package and method of manufacture |
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TWI628760B (en) * | 2016-02-17 | 2018-07-01 | 美光科技公司 | Apparatuses and methods for internal heat spreading for packaged semiconductor die |
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