TW201301357A - Manufacturing method for metal gate - Google Patents

Abstract

A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Description

Metal gate manufacturing method

The invention relates to a metal gate and a manufacturing method thereof, in particular to a metal gate using a gate last process and a manufacturing method thereof.

As the size of semiconductor components continues to shrink, the conventional method of reducing the thickness of the gate dielectric layer, such as reducing the thickness of the yttria layer, for optimization purposes, is due to the tunneling effect of electrons. A physical limitation that causes excessive leakage current. In order to effectively extend the evolution of logic components, high dielectric constant (hereinafter referred to as high-k) materials have an effective reduction in physical limit thickness and the same equivalent oxide thickness (EOT). In order to effectively reduce the leakage current and achieve the equivalent capacitance to control the channel switch, it is used to replace the conventional ruthenium dioxide layer or the ruthenium oxynitride layer as the gate dielectric layer.

However, the conventional gate material polysilicon is faced with boron penetration effect, which leads to problems such as lower component efficiency; and the polysilicon gate encounters an inevitable depletion effect, making the equivalent gate dielectric layer The increase in thickness and the decrease in the gate capacitance value lead to difficulties such as the deterioration of the component driving capability. In response to this problem, the semiconductor industry has proposed to replace the traditional polysilicon gate with a new gate material, such as a metal gate with a work function metal layer, as a matching high-k gate dielectric layer. Control electrode.

However, even if a high-k gate dielectric layer is used in place of a conventional germanium dioxide or tantalum oxynitride dielectric layer, and a metal gate with a matching work function is substituted for a conventional polysilicon gate, how to continuously increase the performance of the semiconductor device, for example, It can ensure that the metal gate of an n-type metal-oxide-semiconductor (nMOS) transistor has a work function of about 4.1 electron volts (eV) and a p-type metal-oxide (p-type metal- Oxide-semiconductor, pMOS) The metal gate of the transistor has a work function of around 5.1 eV, which has been a problem for semiconductor manufacturers.

Accordingly, it is an object of the present invention to provide a method of fabricating a metal gate that ensures that the metal gate of an nMOS transistor or pMOS transistor has a desired work function.

According to the scope of the invention provided by the present invention, a method for fabricating a metal gate is provided. The fabrication method first provides a substrate on which at least one semiconductor component is formed, and the semiconductor component has a conductive pattern. Forming a gate trench in the semiconductor device, and forming a work function metal layer in the gate trench after forming the gate trench, the work function metal layer having the conductive pattern and a pair of conductive patterns Preset work function. Finally, an ion implantation process is performed to adjust the preset work function to a target work function, and the target work function corresponds to the conductive type.

According to the scope of the patent application of the present invention, a method for fabricating a metal gate is provided. The fabrication method first provides a substrate on which at least a first semiconductor component and a second semiconductor component are formed. The first semiconductor The component has a first conductivity pattern, the second semiconductor component has a second conductivity pattern, and the first conductivity pattern is complementary to the second conductivity pattern. Forming a first gate trench and a second gate trench respectively in the first semiconductor component and the second semiconductor component, and then forming a first work function metal layer in the first gate trench. The first work function metal layer has the first conductivity pattern and a first predetermined work function that should be the first conductivity pattern. After forming the first work function metal layer, performing a first ion implantation process to adjust the first predetermined work function to a first target work function. Thereafter, a portion of the first work function metal layer is removed to expose the bottom of the second gate trench. Next, a second work function metal layer is formed in the second gate trench, and the second work function metal layer has the second conductivity type and a second predetermined work function of the second conductivity type. Finally, a second ion implantation process is performed to adjust the second predetermined work function to a second target work function.

According to the method for fabricating a metal gate provided by the present invention, a work function metal layer is formed in a gate trench of a p-type semiconductor element or an n-type semiconductor element, and the work function metal layer itself has a corresponding conductive pattern. Preset work function. A specific ion is then implanted into the work function metal layer by an ion implantation process to adjust a predetermined work function of the work function metal layer to a target work function. The work function metal layer after the ion implantation process has a target work function corresponding to the conductivity type and conforming to the conductivity type requirement. In other words, the metal gate provided by the present invention can ensure that the metal gates of the p-type semiconductor element or the n-type semiconductor element have the required work function, and further ensure the p-type semiconductor having the metal gate. Electrical representation of an element or n-type semiconductor element.

Please refer to FIG. 1 to FIG. 10 . FIG. 1 to FIG. 10 are schematic diagrams showing a preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. As shown in FIG. 1, the preferred embodiment first provides a substrate 100, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. A first semiconductor component 110 and a second semiconductor component 112 are formed on the substrate 100, and a shallow trench isolation (shallow trench) for providing electrical isolation is formed in the substrate 100 between the first semiconductor component 110 and the second semiconductor component 112. Isolation, STI) 102. The first semiconductor component 110 has a first conductivity type, and the second semiconductor component 112 has a second conductivity pattern, and the first conductivity pattern is complementary to the second conductivity pattern. In the preferred embodiment, the first conductivity type is a P type; and the second conductivity type is an N type, but those skilled in the art should know the reverse.

Please refer to Figure 1. The first semiconductor device 110 and the second semiconductor device 112 each include a gate dielectric layer 104, a bottom barrier layer 106 and a dummy gate (not shown) such as a polysilicon layer. The gate dielectric layer 104 can be a conventional germanium dioxide layer or a high dielectric constant gate dielectric layer or a combination thereof; and the bottom barrier layer 106 comprises titanium nitride (TiN), but is not limited thereto. this. In addition, the first semiconductor component 110 and the second semiconductor component 112 respectively include a first light doped drain (LDD) 120 and a second LDD 122, a sidewall 124, and a first source/汲The pole 130 and a second source/drain 132. In addition, the surface of the first source/drain 130 and the second source/drain 132 respectively comprise a metal halide 134. On the first semiconductor device 110 and the second semiconductor device 112, a contact etch stop layer (CESL) 140 and an inter-layer dielectric (ILD) layer 142 are sequentially formed. . The fabrication steps and material selection of the above components, and even the selective epitaxial growth (SEG) method for forming the source/drain electrodes 130/132 in the semiconductor industry to provide stress and improve electrical performance are Those skilled in the art are well known and will not be described here.

Please continue to see Figure 1. After forming the CESL 140 and the ILD layer 142, a portion of the CESL 140 and the ILD layer 142 are removed by a planarization process until the dummy gates of the first semiconductor component 110 and the second semiconductor component 112 are exposed, and then utilized. A suitable etching process removes the dummy gates of the first semiconductor component 110 and the second semiconductor component 112, and a first gate trench 150 and a first gate are formed in the first semiconductor component 110 and the second semiconductor component 112, respectively. Two gate ditches 152. It should be noted that the preferred embodiment can be integrated with a high-k first process, in which case the gate dielectric layer 104 contains a high dielectric constant (high-k constant). A gate dielectric layer, which may be a metal oxide layer, such as a rare earth metal oxide layer. The high-k gate dielectric layer 104 can be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and hafnium silicon oxynitride (HfSiON). , aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), oxidation Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), yttrium Oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr) _a group consisting of _1-x TiO ₃ , BST). In addition, between the high-k gate dielectric layer 104 and the substrate 100, an interfacial layer (not shown) may be disposed. After forming the first gate trench 150 and the second gate trench 152, an etch stop layer may be formed on the bottom barrier layer 106 in the first gate trench 150 and the second gate trench 152 (etch stop) The etch stop layer 108 is exposed to the bottom of the first gate trench 150 and the second gate trench 152. The etch stop layer 108 may include tantalum nitride (TaN), but is not limited thereto.

In addition, please refer to FIG. 2, which is a schematic diagram of a variation of the preferred embodiment. As shown in FIG. 2, the variation uses a high-k last process integration, so the gate dielectric layer 104 can be a conventional ruthenium dioxide layer. After the first gate trench 150 and the second gate trench 152 are formed by removing the polysilicon layer, the gate dielectric layer 140 exposed to the bottom of the first gate trench 150 and the second gate trench 152 can serve as an interface layer. . A high-k gate dielectric layer 104a is then formed over the substrate 100, which may comprise the materials described above. As shown in FIG. 2, the high-k gate dielectric layer 104a in the first gate trench 150 and the second gate trench 152 has a U-shape, covering the first gate trench 150 and the second The sidewall and bottom of the gate trench 152. After the high-k gate dielectric layer 104a is formed, the aforementioned etch stop layer 108 may be formed thereon.

Please refer to Figure 3. After the etch stop layer 108 of the embodiment of FIG. 1 or FIG. 2 is formed, a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process is performed. A first work function metal layer 160 is formed in the first gate trench 150 and the second gate trench 152. The first work function metal layer 160 has a predetermined work function, and the predetermined work function corresponds to the conductive pattern of the first semiconductor device 110, that is, the first work function metal layer 160 may be a p-type having a p-type conductivity type. The work function metal layer includes, for example, titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (tungsten carbide). , WC), or aluminum titanium nitride (TiAlN), but is not limited thereto. In addition, the first work function metal layer 160 may be a single layer structure or a composite layer structure.

Please continue to see Figure 3. After forming the first work function metal layer 160, an ion implantation process 162 is performed for implanting aluminum (aluminum), nitrogen (nitrogen, N), chlorine (chlorine, Cl), oxygen (oxygen, O). , fluorine (F), or bromine (Br) to the first work function metal layer 160 for adjusting the predetermined work function of the first work function metal layer 160 to a target work function. The target work function is between 4.9 electron volts (eV) and 5.2 eV, and preferably 5.1 eV.

Additionally, the ion implantation process 162 can also be performed prior to forming the first work function metal layer 160. Please refer to Figure 4. Figure 4 is a schematic view of another variation of the preferred embodiment. As shown in FIG. 4, the present variation is performed prior to forming the etch stop layer 108 and before forming the first work function metal layer 160, and then performing an ion implantation process 162 for Al, N, Cl, O, F or Br implants an etch stop layer 108. After the ion implantation process 162, a first work function metal layer 160 is formed in the first gate trench 150 and the second gate trench 152.

After performing the ion implantation process 162 and forming the first work function metal layer 160, a heat treatment 164 is performed to cause the dopant in the etch stop layer 108 to enter the first work function metal layer 160 to adjust the first work. The predetermined work function of the function metal layer 160 is adjusted to the target work function. In addition, the heat treatment 164 may also include the passage of oxygen to participate in the work function adjustment of the first work function metal layer 160. It should be noted that the heat treatment 164 can be performed as shown in FIG. 5 after performing the ion implantation process 162 on the first work function metal layer 160 to ensure the work function adjustment result of the first work function 160. However, when the ion implantation process 162 has adjusted the preset work function of the first work function metal layer 160 to the target work function, the heat treatment 164 may also be omitted. In other words, when the ion implantation process 162 provided in the preferred embodiment has adjusted the preset work function of the first work function metal layer 160 to the target work function, the ion implantation provided by the preferred embodiment Process 162 can replace heat treatment 164 containing oxygen.

Please refer to Figure 6. Next, a patterned mask, such as a patterned photoresist layer (not shown), is formed on the substrate 100, but is not limited thereto. The patterned mask is used to cover the first semiconductor component 110 and expose the first work function metal layer 160 at the second semiconductor component 112. The first work function metal layer 160, which is not protected by the patterned mask, is then removed using a suitable etchant such that the etch stop layer 108 is re-exposed within the second gate trench 152. Upon removal of the first work function metal layer 160, the etch stop layer 108 protects the underlying barrier layer 106 and the high-k gate dielectric layer 104. It is also worth noting that, in order to improve the filling result of the subsequent metal film layer, when the first work function metal layer 160 in the second gate trench 152 is completely removed, the patterned mask can be formed in the first gate. The surface of the pole trench 150 is lower than the opening of the first gate trench 150. Therefore, when the first work function metal layer 160 is subsequently removed, the first work function metal layer 160 remains only in the first gate trench 160. The bottom of the first gate trench 160 and the sidewall of the first gate trench 160 are such that the height of the first work function metal layer 160 on the sidewall of the first gate trench 160 is smaller than the depth of the first gate trench 150, thereby increasing the thickness of the subsequent metal film layer. Fill in the ability.

Please continue to see Figure 6. After the first work function metal layer 160 in the second gate trench 152 is removed, a CVD process or a PVD process is performed to form a second work function metal layer 170 on the substrate 100. The second work function metal layer 170 also has a predetermined work function, and the predetermined work function corresponds to the conductive pattern of the second semiconductor device 120, that is, the second work function metal layer 170 can be an n-type conductive type. Type work function metal layer. In addition, the second work function metal layer 170 may be a single layer structure or a composite layer structure. In the preferred embodiment, when the second work function metal layer 170 can be a metal layer, preferably a titanium layer formed by a CVD process or a PVD process, and then an aluminum ion implant is performed immediately after the titanium layer is formed. Process 172 is used to implant aluminum ions into the metal layer to form a second work function metal layer 170, such as a titanium aluminide layer, while presetting the predetermined work function of the second work function metal layer 170.

In addition, in the preferred embodiment, the second work function metal layer 170 is also a titanium aluminide (TiAl) layer formed by a CVD process or a PVD process, and a zirconium aluminide (ZrAl) layer. A tungsten aluminide (WAl) layer, a tantalum aluminide (TaAl) layer or a hafnium aluminide (HfAl) layer, but is not limited thereto. And, after forming the TiAl layer, the ZrAl layer, the WAl layer or the HfAl layer, the aluminum ion implantation process 172 is performed to implant the aluminum ions into the second work function metal layer 170 for adjusting the second work function metal layer. The aluminum content of 170 is pre-adjusted to a predetermined work function of the second work function metal layer 170.

Please refer to Figure 7. After forming the second work function metal layer 170, an ion implantation process 174 is performed for implanting lanthanum (La), zirconium (Zr), hafnium (Hf), titanium (titanium, Ti). And aluminum (aluminum, Al), niobium (Nb) or tungsten (tungsten, W) to the second work function metal layer 170, adjusting the predetermined work function of the second work function metal layer 170 to a target work function. The target work function is between 3.9 eV and 4.2 eV, and preferably 4.1 eV.

Additionally, the ion implantation process 174 can also be performed prior to forming the second work function metal layer 170. Please refer to Figure 8. Figure 8 is a schematic view of another variation of the preferred embodiment. As shown in FIG. 8, the present variation is performed after the first work function metal layer 160 is removed, after the etch stop layer 108 is exposed, and before the second work function metal layer 170 is formed, the ion implantation process 174 is performed. La, Zr, Hf, Ti, Al, Nb or W is implanted into the etch stop layer 108. After the ion implantation process 174, a second work function metal layer 170 is formed on the substrate 100.

After performing the ion implantation process 174 and forming the second work function metal layer 170, a heat treatment 176 is performed to cause the dopant in the etch stop layer 108 to enter the second work function metal layer 170 to adjust the second work. The predetermined work function of the function metal layer 170 is adjusted to the target work function. Additionally, heat treatment 176 preferably includes the passage of nitrogen to densify the second work function metal layer 170. It should be noted that the heat treatment 176 can be performed as shown in FIG. 9 after the second work function metal layer 170 is subjected to the ion implantation process 174 to adjust the work function, and the work function adjustment of the second work function 170 is further ensured. As a result, the surface of the second work function metal layer 170 is simultaneously densified.

Please refer to Figure 10. Finally, a fill metal layer 180 is formed on the second work function metal layer 170 in the first gate trench 150 and the second gate trench 152. In addition, a top barrier layer (not shown) may be disposed between the second work function metal layer 170 and the filling metal layer 180, and the top barrier layer may include TiN, but is not limited thereto. The filling metal layer 180 is used to fill the first gate trench 150 and the second gate trench 152, and may select a metal or metal oxide having excellent filling ability and a lower resistance, such as aluminum (Al). Titanium aluminide (TiAl) or titanium aluminum oxide (TiAlO), but is not limited thereto.

Finally, a planarization process, such as a CMP process, is performed to remove the excess fill metal layer 180, the second work function metal layer 170, the first work function metal layer 160, and the etch stop layer 108, and complete a A metal gate (not shown) and a second metal gate (not shown) are fabricated. In addition, the present embodiment can also selectively remove the ILD layer 142 and the CESL 140 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those of ordinary skill in the art, they are not described herein.

According to the method for fabricating a metal gate provided by the present invention, a work function metal layer is formed in a gate trench of a p-type semiconductor element or an n-type semiconductor element, and the work function metal layer itself has a corresponding conductive pattern. Preset work function. A specific ion is then implanted into the work function metal layer by an ion implantation process to adjust a predetermined work function of the work function metal layer to a target work function. The work function metal layer after the ion implantation process has a target work function corresponding to the conductivity type and conforming to the conductivity type requirement. In other words, the metal gate provided by the present invention can ensure that the metal gates of the p-type semiconductor element or the n-type semiconductor element have the required work function, and further ensure the p-type semiconductor having the metal gate. Electrical representation of an element or n-type semiconductor element.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Base

102. . . Shallow trench isolation

104. . . Gate dielectric layer

104a. . . High dielectric constant gate dielectric layer

106. . . Bottom barrier layer

108. . . Etch stop layer

110. . . First semiconductor component

112. . . Second semiconductor component

120. . . First lightly doped bungee

122. . . Second lightly doped bungee

124. . . Side wall

130. . . First source/dip

132. . . Second source/dip

134. . . Metal telluride

140. . . Contact hole etch stop layer

142. . . Inner dielectric layer

150. . . First gate ditches

152. . . Second gate ditches

160. . . First work function metal layer

162. . . Ion implantation process

164. . . Heat treatment

170. . . Second work function metal layer

172. . . Aluminum ion implantation process

174. . . Ion implantation process

176. . . Heat treatment

180. . . Filled metal layer

1 to 10 are schematic views of a preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention, wherein FIG. 2 is a schematic diagram of a variation of the preferred embodiment. 4 is a schematic view showing another variation of the preferred embodiment, and FIG. 8 is a schematic view showing another variation of the preferred embodiment.

100. . . Base

102. . . Shallow trench isolation

104. . . Gate dielectric layer

106. . . Bottom barrier layer

108. . . Etch stop layer

110. . . First semiconductor component

112. . . Second semiconductor component

120. . . First lightly doped bungee

122. . . Second lightly doped bungee

124. . . Side wall

130. . . First source/dip

132. . . Second source/dip

134. . . Metal telluride

140. . . Contact hole etch stop layer

142. . . Inner dielectric layer

150. . . First gate ditches

152. . . Second gate ditches

160. . . First work function metal layer

162. . . Ion implantation process

Claims (36)

A method for fabricating a metal gate includes: providing a substrate on which at least one semiconductor component is formed, and the semiconductor component has a conductive pattern; forming a gate trench in the semiconductor component; and forming the gate trench Forming a work function metal layer having the conductive pattern and a predetermined work function of a pair of conductive patterns; and performing an ion implantation process to adjust the predetermined work function to a target work function, and The target work function corresponds to the conductive pattern. The manufacturing method of claim 1, wherein the semiconductor device further comprises at least one high dielectric constant gate dielectric layer, a bottom barrier layer and an etch stop layer, and the etch stop layer is exposed to the The bottom of one of the gate ditches. The manufacturing method according to claim 1, wherein the conductive type of the semiconductor element is a P-type conductivity type. The manufacturing method according to claim 3, wherein the work function metal layer comprises titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), carbonization. Tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN). The manufacturing method of claim 3, wherein the ion implantation process comprises implanting aluminum (aluminum, nitrogen), chlorine (chlorine, Cl), oxygen (oxygen, O). , fluorine (F), or bromine (Br). The manufacturing method of claim 3, wherein the target work function is between 4.9 eV and 5.2 eV. The manufacturing method described in claim 3, further comprising a heat treatment process, after the ion implantation process. The manufacturing method of claim 7, wherein the heat treatment process further comprises the step of introducing oxygen. The manufacturing method according to claim 7, wherein the ion implantation process is performed before the work function metal layer is formed, and the heat treatment process is performed after the work function metal layer is formed. The manufacturing method of claim 7, wherein the ion implantation process is performed after forming the work function metal layer. The manufacturing method according to claim 1, wherein the conductive type of the semiconductor element is an N-type conductivity type. The manufacturing method according to claim 11, wherein the work function metal layer comprises titanium aluminide (TiAl), zirconium aluminide (ZrAl), and tungsten aluminide (WAl). , tantalum aluminide (TaAl) or hafnium aluminide (HfAl). The manufacturing method of claim 12, further comprising: forming the work function metal layer on the substrate and the gate trench; and performing an aluminum ion implantation process for adjusting the work function metal layer The aluminum content. The manufacturing method of claim 12, further comprising: forming a metal layer on the substrate and the gate trench; and performing an aluminum ion implantation process to form the work function metal layer. The manufacturing method according to claim 11, wherein the ion implantation process comprises implanting lanthanum (La), zirconium (Zr), hafnium (Hf), titanium (titanium, Ti). , aluminum (aluminum, Al), niobium (Nb) or tungsten (tungsten, W). The manufacturing method of claim 11, wherein the target work function is between 3.9 eV and 4.2 eV. The manufacturing method as described in claim 11 further comprises a nitrogen heat treatment process after the ion implantation process. The manufacturing method according to claim 17, wherein the ion implantation process is performed before the work function metal layer is formed, and the nitrogen heat treatment process is performed after the work function metal layer is formed. The manufacturing method of claim 17, wherein the ion implantation process is performed after forming the work function metal layer. The manufacturing method of claim 1, further comprising the step of forming a filling metal layer in the gate trench, and filling the gate trench to fill the gate trench. A method of fabricating a metal gate includes: providing a substrate on which at least a first semiconductor component and a second semiconductor component are formed, the first semiconductor component having a first conductivity type, the second semiconductor component Having a second conductivity pattern, and the first conductivity pattern is complementary to the second conductivity pattern; forming a first gate trench and a second gate trench in the first semiconductor component and the second semiconductor component; Forming a first work function metal layer in the first gate trench, the first work function metal layer having the first conductivity type and a first predetermined work function of the first conductivity type; performing a first ion Deploying a process, adjusting the first predetermined work function to a first target work function; removing a portion of the first work function metal layer to expose a bottom of the second gate trench; and the second gate trench Forming a second work function metal layer, the second work function metal layer having the second conductivity pattern and a second predetermined work function of the second conductivity type; and performing a second ion cloth Process, adjusting the second predetermined work function to a second target work function. The manufacturing method of claim 21, wherein the first conductivity type of the first semiconductor component is a P-type conductivity type. The manufacturing method according to claim 22, wherein the first work function metal layer comprises titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide. (WC), or titanium aluminum nitride (TiAlN). The manufacturing method of claim 22, wherein the first ion implantation process comprises implanting aluminum (Al), nitrogen (N), chlorine (Cl), oxygen (O), fluorine (F), Or bromine (Br). The manufacturing method of claim 22, wherein the first target work function is between 4.9 eV and 5.2 eV. The manufacturing method according to claim 22, further comprising a heat treatment process, after the first ion implantation process. The manufacturing method of claim 26, wherein the first heat treatment process further comprises the step of introducing oxygen. The manufacturing method of claim 26, wherein the first ion implantation process is performed before or after forming the first work function metal layer. The manufacturing method of claim 21, wherein the second conductivity type of the second semiconductor component is an N-type conductivity type. The manufacturing method according to claim 29, wherein the second work function metal layer comprises titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl). Or aluminized bismuth (HfAl). The manufacturing method of claim 30, further comprising: forming the second work function metal layer on the substrate and the second gate trench; and performing an aluminum ion implantation process for adjusting the The aluminum content of the second work function metal layer. The manufacturing method of claim 30, further comprising: forming a metal layer on the substrate and the second gate trench; and performing an aluminum ion implantation process to form the second work function metal layer . The manufacturing method according to claim 29, wherein the second ion implantation process comprises implanting lanthanum (La), zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), Niobium (Nb) or tungsten (W). The manufacturing method of claim 29, wherein the second target work function is between 3.9 eV and 4.2 eV. The manufacturing method according to claim 21, further comprising a nitrogen heat treatment process, after the second ion implantation process. The manufacturing method of claim 21, wherein the second ion implantation process is performed before or after forming the second work function metal layer.