TW201308438A - Semiconductor device and method of making the same - Google Patents

Abstract

A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first gate/the second gate partially overlaps the first fin structure/the second fin structure having a first stress/a second stress within, and the first stress and the second stress are different. The first source/drain region/the second source/drain region is respectively disposed in the first fin structure/the second fin structure at two sides of the first/second gate.

Description

Semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a strained channel region and a method of fabricating the same.

As the size of metal-oxide-semiconductor (MOS) transistor elements continues to shrink, conventional techniques have proposed stereo or non-planar transistor elements such as multiple gate field effect transistors (multiple). The gate field effect transistor (multiple gate FET) element replaces the solution of the planar transistor element. Since the three-dimensional structure of the multi-gate field effect transistor element can increase the contact area between the gate and the fin-shaped germanium substrate, the gate control of the gate region can be further increased, thereby reducing the source of the small-sized component. The induced induced barrier lowering (DIBL) effect and the short channel effect. In addition, since the gate of the same length in the multi-gate field effect transistor element has a larger channel width, a doubled drain drive current can be obtained.

Therefore, in order to meet the trend of high-integration, high-efficiency and low-power semiconductor component design and product requirements, how to make a novel multi-gate field-effect transistor component to enhance electrical performance is still studied by the relevant technology. The subject.

It is an object of the present invention to provide a semiconductor device having a strained channel region and a method of fabricating the same.

A preferred embodiment of the present invention provides a method of fabricating a semiconductor device comprising the following steps. First, a semiconductor substrate having a first active region and a second active region is provided. Forming at least one first fin structure on the first active region, and the entire first fin structure has a first stress. Forming at least one second fin structure on the second active region, and the entire second fin structure has a second stress different from the first stress.

Another preferred embodiment of the present invention provides a semiconductor device including: a semiconductor substrate having at least one first active region and at least one second active active region. The at least one first fin structure is disposed on the first active region, and the at least one second fin structure is disposed on the second active region. The first fin structure has a first stress and the second fin structure has a second stress different from the first stress.

The invention adopts an ion implantation process and a selective epitaxial growth process to form a fin structure having a strained bismuth epitaxial layer, which can avoid damage caused to the formed structure by etching, cleaning and the like in the conventional strain 矽 epitaxial layer process. And reducing the adverse effects of the residual of the cleaning solution, the etching solution, and the chemical solvent on the electrical performance of the semiconductor device. In addition, the present invention also proposes to further integrate the fin structure with the strained germanium epitaxial layer and the metal gate process to form a novel multi-gate field effect transistor component to enhance the speed performance and electrical performance of the transistor.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to FIG. 1 to FIG. 3 . FIG. 1 to FIG. 3 are schematic diagrams showing the formation of a fin structure according to a preferred embodiment of the present invention. As shown in FIG. 1, this embodiment first provides a semiconductor substrate 10. The semiconductor substrate 10 may include a bulk silicon substrate having at least two active regions defined by a first active region and a second active region, for example, an N-type MOS transistor region 11 And a P-type MOS transistor region (PMOS) region 13. In addition, the semiconductor substrate 10 of the present invention may also be other kinds of substrates, such as a silicon-on-insulator (SOI) substrate, to provide better heat dissipation and grounding effects, and to reduce cost and Suppresses noise.

Then, a selective epitaxial growth (SEG) process is performed to form a semiconductor layer 16 on the surface of the semiconductor substrate 10, and the material of the semiconductor layer 16 has at least two kinds of 4A elements, and the composition thereof can be Neodymium carbon (Si _(1-xy) Ge _x C _y ) represents a positive number in which x and y are greater than or equal to 0 and less than 1, in order to utilize the lattice constant of germanium carbon and single crystal Si (single crystal Si) Different characteristics cause the semiconductor layer 16 to be structurally strained to form a strain 具 having a specific stress, and the band structure of the ytterbium is changed, thereby causing an increase in carrier mobility to enhance a semiconductor device such as a transistor. speed. Wherein, prior to the selective epitaxial growth (SEG) process, the present invention may also selectively perform an ion implantation process on the semiconductor substrate 10, and the dopant species used herein may include a Group 4A element such as carbon (carbon). , C), germanium (Gemanium, Ge) or a combination of two or more elements of Group 4A, and the like.

Subsequently, the strain state of the semiconductor layer 16 of the NMOS region 11 and/or the PMOS region 13 is adjusted for different device characteristics. For example, at least the following implementations are included:

The first embodiment:

When the fully formed semiconductor layer 16 is germanium carbon (Si _(1-xy) Ge _x C _y ) and y>0.1x, the semiconductor layer 16 has a native tensile stress. Therefore, in this embodiment, a patterned photoresist layer (not shown) can be used to cover the NMOS region 11 and expose the PMOS region 13 to perform a 4A group including germanium (Ge) for the semiconductor layer 16 of the PMOS region 13. The ion implantation process of the element is such that y < 0.1 x of the semiconductor layer 16 of the PMOS region 13 is converted into a depressive layer having a compressive stress. Finally, the patterned photoresist layer is removed.

Second implementation aspect:

When the fully formed semiconductor layer 16 is germanium carbon (Si _(1-xy) Ge _x C _y ), and y < 0.1 _x , the semiconductor layer 16 has a native compressive stress. Therefore, in this embodiment, a patterned photoresist layer (not shown) can be used to cover the PMOS region 13 and expose the NMOS region 11 to perform a 4A group including carbon (C) for the semiconductor layer 16 of the NMOS region 11. The ion implantation process of the element is such that y>0.1x of the semiconductor layer 16 of the NMOS region 11 is converted into an epitaxial layer with tensile stress. Finally, the patterned photoresist layer is removed.

The third embodiment:

When the fully formed semiconductor layer 16 is bismuth (Si _(1-x) Ge _x ), the semiconductor layer 16 has a native compressive stress. Therefore, in this embodiment, a patterned photoresist layer (not shown) can be used to cover the PMOS region 13 and expose the NMOS region 11 to perform a 4A group including carbon (C) for the semiconductor layer 16 of the NMOS region 11. The ion implantation process of the element is such that the semiconductor layer 16 of the NMOS region 11 is modified into germanium carbon (Si _(1-xy) Ge _x C _y ), and y>0.1x, which is transformed into an epitaxial strain of tensile stress. Floor. Finally, the patterned photoresist layer is removed.

Fourth implementation aspect:

When the fully formed semiconductor layer 16 is germanium carbon (Si _(1-y) C _y ), the semiconductor layer 16 has a native tensile stress. Therefore, in this embodiment, a patterned photoresist layer (not shown) can be used to cover the NMOS region 11 and expose the PMOS region 13 to perform a 4A group including germanium (Ge) for the semiconductor layer 16 of the PMOS region 13. The ion implantation process of the element is such that the semiconductor layer 16 of the PMOS region 13 is modified into germanium carbon (Si _(1-xy) Ge _x C _y ), and y<0.1x, which is transformed into a compressive stress epitaxy Floor. Finally, the patterned photoresist layer is removed.

Fifth embodiment:

When the fully formed semiconductor layer 16 is germanium, the present embodiment may first utilize a patterned photoresist layer (not shown) to cover the NMOS region 11 and expose the PMOS region 13 to the semiconductor layer of the PMOS region 13. An ion implantation process comprising a Group 4A element of germanium (Ge) is performed to modify the semiconductor layer 16 of the PMOS region 13 to germanium carbon (Si _(1-xy) Ge _x C _y ), and y < 0.1 x, which in turn is transformed into an epitaxial layer with compressive stress. After removing the patterned photoresist layer, another patterned photoresist layer (not shown) is used to cover the PMOS region 13 and expose the NMOS region 11 to perform a carbon (C) on the semiconductor layer 16 of the NMOS region 11. The ion implantation process of the 4A element is such that the semiconductor layer 16 of the NMOS region 11 is modified into germanium carbon (Si _(1-xy) Ge _x C _y ), and y>0.1x, which is converted into a tensile stress. Epitaxial layer. Finally, the patterned photoresist layer is removed.

Sixth implementation aspect:

Prior to the selective epitaxial growth (SEG) process, the present invention may also selectively perform an ion implantation process on the semiconductor substrate 10, and the dopant species used herein may include a Group 4A element such as carbon (C).锗 (Ge) or a combination of two or more Group 4A elements. For example, by using a patterned photoresist layer (not shown), covering the NMOS region 11 and exposing the PMOS region 13, an ion implantation process including a germanium (Ge) group 4A element is performed on the semiconductor substrate 10 of the PMOS region 13. So that the semiconductor layer 16 formed later in the PMOS region 13 becomes germanium (Si _(1-x) Ge _x ) or germanium carbon (Si _(1-xy) Ge _x C _y ) with y < 0.1x, and has A compressive stress. Similarly, another patterned photoresist layer (not shown) is used to cover the PMOS region 13 and expose the NMOS region 11 to perform an ion cloth including a carbon (C) 4A element for the semiconductor substrate 10 of the NMOS region 11. The implantation process is such that the semiconductor layer 16 formed later in the NMOS region 11 becomes germanium carbon (Si _{(1- y)} C _y ) or y > 0.1 _x germanium carbon (Si _(1-xy) Ge _x C _y ), It has a tensile stress.

In other words, the present invention utilizes a selective epitaxial growth (SEG) process and at least one ion implantation process including a group 4A element to form a semiconductor layer 16 on the surface of the semiconductor substrate 10 in a comprehensive manner. The material of the semiconductor layer 16 is made to have at least two Group 4A elements, the composition of which may be represented by bismuth carbon (Si _(1-xy) Ge _x C _y ), wherein x and y are positive numbers greater than or equal to 0 and less than 1, Moreover, the semiconductor layer 16 in the NMOS region 11 of the semiconductor substrate 10 and the semiconductor layer 16 in the PMOS region 13 have different x, y values, respectively. For example, when the carbon element molar ratio (y) in the material of the semiconductor layer 16 is substantially greater than one tenth of the 锗 element molar ratio (x), that is, y>0.1x, due to the semiconductor layer The lattice constant of 16 is smaller than that of 矽, which can form an epitaxial layer with tensile stress, and can be further used as a strained 矽 channel region of an N-type transistor (NMOS), which is advantageous for improving current drive. Theoretically, when the carbon element molar ratio (y) in the material of the semiconductor layer 16 is substantially less than one tenth of the 锗 element molar ratio (x), that is, y<0.1x, The lattice constant of the semiconductor layer 16 is larger than that of the germanium, and a depressive layer having a compressive stress can be formed, which can be further used as a strained channel region of a P-type transistor (PMOS), which is advantageous for improving current driving.

A portion of the semiconductor layer is then etched to form the desired fin structure on the semiconductor substrate. The steps may be as shown in FIG. 2, first forming a patterned hard mask 15 on the semiconductor layer 16 for defining at least one fin structure 18. An etching process is then performed to remove portions of the semiconductor layer 16 and portions of the semiconductor substrate 10, and a plurality of fin structures 18 and shallow trenches therebetween are simultaneously formed on the semiconductor substrate 10. Then, high-density plasma chemical vapor deposition (HDPCVD), sub-atmospheric chemical vapor deposition (SACVD), spin-on dielectric (SOD), etc. A dielectric layer 17 is formed on the semiconductor substrate 10 to cover the fin structures 18 and fill the shallow trenches. The dielectric layer 17 is then planarized by a chemical mechanical polishing process (CMP), and the patterned hard mask 15 and a portion of the dielectric layer 17 are removed by an etching process to form the semiconductor substrate 10 between the fin structures 18. A shallow trench isolation 19 is formed in the middle, as shown in FIG.

It should be noted that the order of the ion implantation process and the patterned semiconductor layer 16 to form the plurality of fin structures 18 is not limited thereto. For example, after the semiconductor layer 10 is formed by the selective epitaxial growth process on the semiconductor substrate 10 After the patterning process is defined to define at least one fin structure 18, the ion implantation process of each of the foregoing embodiments is performed to adjust the germanium carbon of each of the fin structures 18 in the NMOS region 11 and the PMOS region 13 ( Si _(1-xy) Ge _x C _y ) composition ratio. That is, the ion implantation process of the Group 4A element of the present invention can be performed comprehensively/regionally on the semiconductor substrate/fin structure.

Various semiconductor processes are then required, such as MOS processes with polysilicon gates or metal gates. The process of integrating the high-K last process and the fin structure process described above after the gate last process is taken as an example. Please refer to FIG. 4 to FIG. 9 . FIG. 4 to FIG. 9 are schematic diagrams showing a semiconductor device according to a preferred embodiment of the present invention. As shown in FIG. 4 , firstly, sequentially formed on the semiconductor substrate 10 . A dielectric layer 21, a gate material layer 22 covers the fin structures 18, and a planarization process is performed on the gate material layer 22. Next, as shown in FIG. 5, a patterned cap layer 28 is formed on the gate material layer 22 for defining the positions of the gates in the NMOS region 11 and the PMOS region 13. The gate material layer 22 and the dielectric layer 21 are then etched using the patterned cap layer 28 as an etch mask, and the dummy gates 20 of the respective fin structures 18 of the plurality of cap portions are formed on the semiconductor substrate 10. The extending direction of the dummy gate 20 is perpendicular to the extending direction of the fin structure 18 and the dummy gate 20 directly covers the two side walls and the top surface of each fin structure 18 . The dielectric layer 21 may include a dielectric material such as yttrium oxide (SiO), tantalum nitride (SiN), yttrium oxynitride (SiON). The gate material layer 22 may be composed of a polycrystalline germanium material having no undoped or a polycrystalline germanium material having an N+ dopant. The patterned cap layer 28 is disposed above the dummy gate 20, and may be composed of a material such as tantalum nitride, cerium oxide (SiO ₂ ) or cerium oxynitride (SiON).

Next, a lightly doped source/drain region (not shown) is selectively formed in the fin structure 18 not covered by the dummy gate 20. Then, a sidewall 32 is formed on the surrounding sidewall of the dummy gate 20, and the sidewall 32 may be a single layer or a multilayer structure, or may include a liner or the like. The material of the sidewall 32 may include a high temperature oxide (HTO), tantalum nitride, hafnium oxide or tantalum nitride (HCD-SiN) formed using hexachlorodisilane (Si ₂ Cl ₆ ). But not limited to this. The method of forming the side wall sub-32 is a conventional technique and will not be described herein. Thereafter, the sidewall spacer 32 and the cap layer 28 are used as masks to perform an ion implantation process, and a suitable dopant is doped, and the dopant may include an N-type or a P-type dopant in the NMOS region 11 and the PMOS region 13 The fin structure 18 exposed on both sides of the dummy gate 20 is respectively implanted with a corresponding source/drain dopant, and is combined with an annealing process to activate the source/drain region 34, such as the sixth The figure shows. Although the present embodiment preferably forms the lightly doped source/drain region, the sidewall spacer 32, and the source/drain region 34 in sequence, the present invention is not limited thereto, and the present invention can be arbitrarily adjusted according to the requirements of the process. The order in which the sidewalls and the doped regions are formed is within the scope of the present invention.

It is worth noting that, at this point, the process of a multi-gate field effect transistor with a polysilicon gate is generally completed. In this embodiment, the fin structure 18 and the dielectric layer 21 have three direct contact surfaces, for example, two contact sides and a contact top surface, and the multi-gate field effect crystal system is a stereo transistor (Tri-gate). ), but not limited thereto, the hard mask 15 may be present between the top surface of the fin structure 18 and the dielectric layer 21 . In this case, only the fin structure 18 and the dielectric layer 21 will be There are two direct contact surfaces, for example, two contact sides, and the formed multi-gate field effect crystal system is a Fin Field effect transistor (FinFET). The fin structure 18 located in the active region of the present invention contains at least two Group 4A elements such as ruthenium, osmium, and carbon, and the composition ratio thereof may be represented by (Si _(1-xy) Ge _x C _y ). The fin structure 18 partially covered by the dummy gate 20 can serve as a channel region in the middle of the source/drain region 34, which is advantageous for improving current drive. When the carbon element molar fraction ratio is substantially greater than one tenth of the 锗 element molar ratio, that is, the ratio of y to x is greater than 0.1, that is, y>0.1x, the entire fin structure 18 may include The epitaxial layer with tensile stress is favorable as a strained channel region of the subsequently formed NMOS, and when the carbon element molar ratio is substantially less than one tenth of the ratio of the elemental molar ratio, that is, y When the ratio to x is less than 0.1, that is, y < 0.1x, the entire fin structure 18 may include an epitaxial layer with compressive stress, which is advantageous as a strained channel region of the subsequently formed PMOS. The invention adopts an ion implantation method together with a selective epitaxial growth process to form a stress epitaxial layer, and then forms an fin structure through an etching process, which is different from the conventional strain 矽 transistor process for preparing a predetermined epitaxial layer. The notch needs to be additionally etched, cleaned and the like on the semiconductor substrate, and the invention can avoid the damage of the formed structure caused by such pre-process, and reduce the residual of the cleaning solution, the etching solution and the chemical solvent to the semiconductor device. The adverse effects of electrical performance.

The gate-high dielectric layer (high-K last) process is continued after the metal gate process. A single transistor component is taken as an example. As shown in FIG. 7, a contact etch stop layer (CESL) 36 and an inner dielectric layer are deposited on the semiconductor substrate 10 in sequence. Inter-layer dielectric (ILD) 38 comprehensively covers the semiconductor substrate 10. The material of the contact hole etch stop layer 36 may include, for example, tantalum nitride, and the material of the inner dielectric layer 38 may include one or more of nitride, oxide, carbide, low-k material.

As shown in FIG. 8, a planarization process, such as a chemical mechanical polish (CMP) process or an etch process, is performed to sequentially remove portions of the inner dielectric layer 38 and portions. The contact etch stop layer 36, a portion of the sidewall spacers 32, and the cap layer 28 are completely removed to expose the gate material layer 22. An etch process is then performed to remove the gate material layer 22. The etching process may include dry etching or wet etching. For example, in one embodiment, the dummy gate 20 is dry etched with chlorine gas as an etching gas, and then tetramethyl ammonium hydroxide (TMAH) is used. The solution removes the remaining gate material layer 22 as an etchant to form a gate opening (not shown), but is not limited thereto. A high dielectric constant gate dielectric layer 42 is then formed over the gate opening to cover the dielectric layer 21, the sidewall spacers 32, the contact hole etch stop layer 36, and the inner dielectric layer 38. The material of the high dielectric constant gate dielectric layer 42 may be selected from, for example, hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon (hafnium silicon). Oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ ) ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ) , strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT), barium strontium titanate , Ba _x Sr _1-x TiO ₃ , BST), and a group thereof, but are not limited thereto. In addition, an intermediate layer (not shown) may be newly formed to replace the dielectric layer 21 before the high-k gate dielectric layer 42 is formed.

Next, a work function metal layer 44 is selectively formed over the high dielectric constant gate dielectric layer 42 for adjusting the work function of the metal gate formed later to be suitable for an N-type transistor (NMOS) or P. Type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer may be selected from a metal material having a work function of 3.9 eV to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), or tungsten aluminide ( WAl), tantalum aluminide (TaAl) or hafnium aluminide (HfAl), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer may be selected from a metal having a work function of 4.8 eV to 5.2 eV Materials such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto.

Then, a metal conductive layer 46 is filled in the work function metal layer 44 and fills the gate opening. In this embodiment, the metal conductive layer 46 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like. Or a combination thereof. After forming the high dielectric constant gate dielectric layer 42, the work function metal layer 44, and the metal conductive layer 46, as shown in FIG. 9, a planarization process, such as a chemical mechanical polish, may be performed. , CMP) process, removing part of the metal conductive layer 46, part of the work function metal layer 44 and part of the high dielectric constant gate dielectric layer 42 to the top surface of the inner dielectric layer 38, thereby completing a metal gate A semiconductor device having a pole 48 and a fin structure 18. In addition, between the work function metal layer 44 and the high dielectric constant gate dielectric layer 42 and between the work function metal layer 44 and the metal conductive layer 46, a titanium (Ti) and a nitride may be selectively formed. A barrier layer of a material such as titanium (TiN), tantalum (Ta), tantalum nitride (TaN) or the like (not shown).

Please refer to FIG. 10, which is a schematic diagram of a semiconductor device according to a preferred embodiment of the present invention. As shown in FIG. 10, the semiconductor substrate 10 has at least one first active region 11 and at least one second active region 13. The semiconductor substrate 10 may comprise a silicon-on-insulator (SOI) substrate or a bulk silicon substrate. In the present embodiment, the semiconductor substrate 10 is described as a unitary substrate. The first active region 11 includes an N-type transistor disposed therein as an NMOS region. The second active region 13 includes a P-type transistor disposed therein as a PMOS region, but is not limited thereto. In addition, at least one first fin structure 58 is disposed on the first active region 11 , and at least one second fin structure 60 is disposed on the second active region 13 . The first fin structure 58 and the second fin structure 60 comprise a semiconductor material whose composition can be represented by carbon (Si _(1-xy) Ge _x C _y ), and x and y are greater than or equal to 0 and less than 1 Positive number. More specifically, when the ratio of y to x is greater than 0.1 (y > 0.1 x) in the material composition of the first fin structure 58, the entire first fin structure 58 has a tensile stress. When the ratio of y to x is less than 0.1 (y<0.1x) in the material composition of the second fin structure 60, the entire second fin structure 60 has a compressive stress. Also, a first gate 54 partially covers the first fin structure 58 and a second gate 56 partially covers the second fin structure 60. The first gate 54 includes a high dielectric constant gate dielectric layer 42 , a first work function metal layer 50 , and a metal conductive layer 46 , and the second gate 56 includes a high dielectric constant gate dielectric layer 42 . The second work function metal layer 52 and the metal conductive layer 46. The materials of the first work function metal layer 50 and the second work function metal layer 52 may be selected according to respective work function requirements of the NMOS and the PMOS, as described above; according to the work function requirements of the NMOS and the PMOS, the first work function metal The layer 50 and the second work function metal layer 52 may also optionally use a single layer or a multilayer structure. A first source/drain region (not shown) is further disposed in the first active region 11 (NMOS region) in the first fin structure 58 on both sides of the first gate 54. In the second active region 13 (PMOS region), a second source/drain region (not shown) is respectively disposed in the second fin structure 60 on both sides of the second gate 56. The relative arrangement of the first gate 54 , the second gate 56 , the first fin structure 58 , the second fin structure 60 and the source/drain regions is as shown in FIG. 6 , wherein the dummy gate 20 The direction of extension is perpendicular to the direction in which the fin structures 18 extend, that is, the source/drain regions described so far are located on the fin structure extending perpendicular to the plane of the paper.

In summary, the present invention forms a fin structure having a strained bismuth epitaxial layer by an ion implantation process and a selective epitaxial growth process, which can avoid the steps of etching, cleaning, etc. in the conventional strain 矽 epitaxial layer process. Structural damage and reduced adverse effects of cleaning solutions, etchants, and chemical solvents on the electrical performance of semiconductor devices. In addition, the present invention also proposes to further integrate the fin structure with the strained germanium epitaxial layer and the metal gate process to form a novel multi-gate field effect transistor component to enhance the speed performance and electrical performance of the transistor.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Semiconductor substrate

11. . . NMOS region

13. . . PMOS area

15. . . Hard mask

16. . . Semiconductor layer

17. . . Dielectric layer

18. . . Fin structure

19. . . Shallow trench isolation

20. . . Virtual gate

twenty one. . . Dielectric layer

twenty two. . . Gate material layer

28. . . Cover

32. . . Side wall

34. . . Source/bungee area

36. . . Contact hole etch stop layer

38. . . Inner dielectric layer

42. . . High dielectric constant gate dielectric layer

44. . . Work function metal layer

46. . . Metal conductive layer

48. . . Metal gate

50. . . First work function metal layer

52. . . Second work function metal layer

54. . . First gate

56. . . Second gate

58. . . First fin structure

60. . . Second fin structure

1 to 3 are schematic views showing the formation of a fin structure according to a preferred embodiment of the present invention.

4 to 9 are schematic views showing the formation of a semiconductor device in accordance with a preferred embodiment of the present invention.

Figure 10 is a schematic view of a semiconductor device in accordance with a preferred embodiment of the present invention.

10. . . Semiconductor substrate

18. . . Fin structure

19. . . Shallow trench isolation

20. . . Virtual gate

28. . . Cover

32. . . Side wall

34. . . Source/bungee area

Claims (20)

A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first active region and a second active region; forming at least one first fin structure on the first active region, and the entire first fin The structure has a first stress; and at least one second fin structure is formed on the second active region, and the entire second fin structure has a second stress different from the first stress. The method of fabricating a semiconductor device according to claim 1, further comprising: forming a first gate portion covering the first fin structure; forming a second gate portion covering the second fin structure; forming a first Source/drain regions are respectively located in the first fin structures on both sides of the first gate; and second second source/drain regions are formed on the two sides of the second gate In the structure. The method of fabricating a semiconductor device according to claim 1, wherein a material composition of each of the fin structures is represented by bismuth carbon (Si _(1-xy) Ge _x C _y ), and x and y are greater than or equal to 0. And a positive number less than one. The method of fabricating a semiconductor device according to claim 3, wherein the first active region comprises an N-type transistor (NMOS) region, and a ratio of y to x is greater than 0.1 in a material composition of the first fin structure. . The method of fabricating a semiconductor device according to claim 3, wherein the second active region comprises a P-type transistor (PMOS) region, and wherein the ratio of y to x is less than 0.1 in the material of the second fin structure. The method of fabricating a semiconductor device according to claim 1, wherein the method of forming the fin structures comprises: forming a semiconductor layer on the semiconductor substrate; performing at least one ion implantation process; and patterning the semiconductor layer to form The fin structures. The method of fabricating a semiconductor device according to claim 6, wherein the semiconductor layer has the first stress, and the ion implantation process is performed on the second active region, so that the second fin structure has the second stress . The method of fabricating a semiconductor device according to claim 6, wherein the ion implantation process is performed on the first active region such that the first fin structure has the first stress, and the method further comprises another ion The implanting process is performed on the second active region such that the second fin structure has the second stress. A method of fabricating a semiconductor device according to claim 6, wherein the ion implantation process is performed after patterning the semiconductor layer. The method of fabricating a semiconductor device according to claim 6, wherein the semiconductor layer comprises germanium, germanium carbon (Si _(1-xy) Ge _x C _y ), germanium carbon (Si _(1-y) C _y ) or germanium.锗(Si _(1-x) Ge _x ), and x and y are positive numbers greater than or equal to 0 and less than one. The method of fabricating a semiconductor device according to claim 1, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate or a bulk silicon substrate. The method of fabricating a semiconductor device according to claim 2, wherein at least one of the first gate and the second gate is a metal gate. A semiconductor device comprising: a semiconductor substrate comprising at least one first active region and at least one second active region; at least one first fin structure is disposed on the first active region, and the entire first fin structure has a a first stress; and at least one second fin structure is disposed on the second active region, and the entire second fin structure has a second stress different from the first stress. The semiconductor device of claim 13, further comprising: a first gate portion covering the first fin structure; a second gate portion covering the second fin structure; a first source/drain region And respectively disposed in the first fin structure on both sides of the first gate; and a second source/drain region respectively disposed in the second fin structure on both sides of the second gate. The semiconductor device of claim 13, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate or a bulk silicon substrate. The semiconductor device of claim 13, wherein the first fin structure and the second fin structure comprise a semiconductor material, represented by germanium carbon (Si _(1-xy) Ge _x C _y ), and x y is a positive number greater than or equal to 0 and less than one. The semiconductor device of claim 16, wherein the first active region comprises an N-type transistor (NMOS) region, and wherein a ratio of y to x is greater than 0.1 in a material composition of the first fin structure. The semiconductor device of claim 16, wherein the second active region comprises a P-type transistor (PMOS) region, and wherein the ratio of y to x is less than 0.1 in the material composition of the second fin structure. The semiconductor device of claim 14, wherein one of the first gate and the second gate comprises a high dielectric constant gate dielectric layer, a work function metal layer, and a metal conductive layer. The semiconductor device of claim 14, wherein at least one of the first gate and the second gate is a metal gate.