TW201242072A - Light emitting semiconductor device having multi-level substrate - Google Patents

Abstract

Provided is a light emitting semiconductor device that includes a substrate having a first area having a first height and a second area having a second height different from the first height, wherein the first area supports at least a first light emitting semiconductor (LES) and the second area supports at least a second light emitting semiconductor (LES).

Description

201242072 VI. INSTRUCTIONS: This application claims U.S. Provisional Patent Application No. 61/444,348, filed on Feb. 18, 2011, and U.S. Provisional Patent Application No. 61/577,733, filed on December 20, 2011. Priority is hereby incorporated by reference in its entirety. [Prior Art] The use of a light-emitting semiconductor (LES) (including a light-emitting diode (LED), a laser diode) and a LES device (LESD) and a package containing a LESD has several drawbacks. The power LESD generates a lot of heat that must be managed. The heat management of lEsd includes problems due to heat dissipation and thermal stress, which are currently the key factors limiting the performance of light-emitting diodes. In general, LESDs are generally susceptible to damage resulting from the heat generated within the device and the accumulation of heat from sunlight when used in external lighting applications. Excessive heat buildup can cause degradation of the materials used in the LES device, such as the LESD encapsulant. When the LESD is attached to a heat resistant substrate (e.g., FR4 flexible-circuit laminate) that often includes other electrical components, the heat dissipation problem is greatly increased. In addition, conventional LESDs and packages tend to be thicker, which limits their use in low form factor applications. Therefore, there is still a need in the industry to improve the flexibility of the design and packaging design to improve its heat dissipation properties and allow it to be used with low form factor. SUMMARY OF THE INVENTION At least one aspect of the present invention provides a cost effective thermal management solution via the robust flexible LESd for the current month' and future power LESD constructions 162438.doc 201242072. The operation of high power LESD arrays requires the ability to dissipate a large amount of heat. In accordance with at least one embodiment of the present invention, heat dissipation can be managed by integrating the LESD into a system having a flexible dielectric layer, wherein the LESD is disposed on one of the major surfaces of the dielectric layer and the thermally conductive material is disposed on On the second major surface of the dielectric layer, or she is adjacent to it. For good thermal management, [£8〇) can be placed at different distances from the thermal layer, based on, for example, its heat dissipation requirements. This is accomplished by controlling the thickness of the insulating (dielectric) layer between each type of LESD and the thermally conductive layer. In at least one embodiment of the invention, controlled regions of one or more desired thicknesses are applied to regions of the dielectric layer in order to achieve a desired arrangement of one or more lesd relative to the conductive material. The recessed areas comprising large areas or small cavities may be etched or may be formed by other suitable methods including microreplication. For the purposes of the present invention, the recessed area may be in the form of a small cavity in which only one or a few LESDs may be placed, or a large recess in which a plurality of LESDs may be placed. In some embodiments, when at least one LESD is located in the recess and one is not located in the recess, or when the LESD is placed in a recess of a different depth, the generation of a recessed area in which some of the LEDS are placed may be adjacent The amount of insulating (dielectric) material between LESDs increases. This increases in insulating material' so the LESD can be placed closer in the X and gamma directions than if it were on the same planar surface. In some embodiments, the etching of the dielectric layer provides the additional advantage of creating recessed regions having sloped sidewalls that may be coated with a reflective material to provide enhanced light efficiency. Additionally, in some embodiments, due to 162438.doc 201242072 the following 'so the present invention makes it extremely suitable for low', the solder can be held in at least a portion of the LESD at the surface of the dielectric layer. The flexible LESD has a lower than standard leSD. Profile, open > shape factor application. Moreover, in some embodiments recessed regions, and such embodiments avoid solder spreading as it undergoes a solder reflow process for die attach. The illumination system is a special light emitting semiconductor device having at least one aspect different from the present invention to include the following: an optical acquisition system; having a first height (LESD) 'the first-LESD facing optical acquisition system a second light-emitting semiconductor device (lesd) having a second height of south, the second LESD facing the optical system; and a substrate. The substrate has a first region and a second region, wherein the first region supports at least the first USD and the second region supports at least the second LESD, and the first region has a second region different from the second region The height of the first area of height. At least one aspect of the present invention is characterized by including illumination of a first light emitting semiconductor device (LESD) having a first height, and a second light emitting semiconductor device having a second degree different from the first degree (LESD) And a dielectric layer having a first region and a second region. The first region supports at least the first LESD and the second region supports at least the second LESD. The first region has a first regional extent different from the height of the second region of the second region such that the first LESD and the second LESD have a substantially planar emitting surface. At least one aspect of the invention features a method comprising: providing an optical acquisition system; providing a substrate having first and second major surfaces and a first region having a first height; on the first major surface Generating 162438.doc 201242072 at least a recessed person's H such that the second region has a second height less than the first height; and placing at least one light emitting semiconductor on: the first and to the optical acquisition system On each of the second areas. At least one aspect of the present invention features an article comprising: a flexible dielectric layer having first and second major surfaces, the first major surface having at least one first region having a first height and At least one second region having a second height different from the first temperature, wherein the first region supports at least one first light emitting semiconductor device (LESD) and the second region supports at least one second light emitting semiconductor device ( LESD); and a first conductive layer on the first major surface of the dielectric layer. At least one aspect of the present invention features a method of fabricating a flexible light emitting device, the method comprising the steps of: providing a flexible dielectric material having first and second major surfaces and a first region having a first height; Forming at least one recessed second region on the first major surface, the second region having a second height less than 5 Hz; generating a conductive layer on the first major surface of the dielectric material And placing at least one LESD on each of the first and second regions. As used in this application: "LES" means a light-emitting semiconductor 'including a light-emitting diode and a laser diode; LESD" means a light-emitting semiconductor device including a light-emitting diode device and a laser diode device. The LESD may be a bare LES die construction, a fully encapsulated LES construction, or an intermediate LES configuration containing more than bare die, but less than all components of a full LES package, such that the terms LES and LESD are available at 162438.doc 201242072 * Used interchangeably in some cases and refers to different LES configurations - either or all; the term "flexible LES device" or "flexible LESD" generally refers to a bare-die light-emitting semiconductor, encapsulated LES structure, or intermediate Les construction • Flexible objects; • The “height” and “thickness” of the dielectric layer often refer to the vertical dimension of the dielectric layer in a certain region; the depth of the concave region in the dielectric layer Generally refers to the vertical dimension of the recessed area in the dielectric layer (ie, 'no material present'); "cavity" means that only one or a few recessed areas of the LESD can be placed; and "recessed" means can be placed A large recessed area of a plurality of LESDs. The above summary of the present disclosure is not intended to describe each of the disclosed embodiments or embodiments. The following figures and detailed description more particularly exemplify illustrative embodiments. [Embodiment] The drawings are incorporated in and constitute a part of the specification, and the advantages and principles of the invention are explained in conjunction with the description. In the following description, reference is made to the accompanying drawings in the claims Other embodiments are contemplated and may be practiced without departing from the scope or spirit of the invention. Therefore, the following detailed description should not be considered limiting. Unless otherwise indicated, all numerical values, such as size, quantity, and physical properties, used in the specification and claims are in all cases 162 438.doc 201242072 is understood to be modified by the term "about." Accordingly, unless indicated to the contrary gamma, the numerical values set forth in the above specification and the accompanying claims are intended to be modified by those skilled in the art using the teachings disclosed herein. The range of values used by the endpoints includes all values within the range (eg, 1 to 5 including 1, 1.5, 2·75 3, 3'80, 4, and 5) and any range within the range . Unless otherwise stated, the term ""c〇at," "c〇ating," coated'") and the like are not limited to a particular type of application, such as spraying, dip coating, full-coating, etc. And may refer to a material deposited by any method suitable for the material, including a deposition method such as a vapor deposition method, a plating method, a coating method, and the like. Lighting assemblies often include LESDs having different colors, wherein different color LESDs can have different heights. For example, RGB (i.e., red, blue, and green) LESDs are typically combined to produce white light. Blue and green LESDs are sometimes made from the same material system and thus have similar dimensions, while red LeSD is often made from different material systems and has dimensions different from those of blue or green lESE). It is often desirable for a plurality of LESDs to have a substantially planar emitting surface, as illustrated in Figures 1A and 1B. Figures 及8 and 1B provide illustrative ray tracing diagrams for lighting assemblies with different configurations. FIG. 1A illustrates a lighting assembly 100A that includes two LESDs 110A and 120A and an optical acquisition system 150. The two LESDs 110A and 120A have different emitting surfaces. As illustrated in region 140A, a portion of the light emitted from LESD 110A (which is further from optical acquisition system 150 than from LESD 120A) is not acquired by optical acquisition system 162438.doc 201242072. Figure 1B illustrates a lighting assembly ι00Β, which includes two

LESD 110B and 120B and optical acquisition system 150. The two LESDs 110B and 120B have an essentially planar emitting surface. As illustrated in the area mob, 'a small portion of the light emitted from the LESD 110B is not used by the optical acquisition system.

System 150 collection. The proportion of light from lesd 11〇B that is not collected by optical acquisition system 150 is less than the ratio of uncollected light from LESD 11 〇A in Figure 1A. The method and system of the present invention pertains to an illumination assembly having a multi-layer substrate to support a plurality of LESDs having different heights, wherein the illumination assembly provides an essentially planar emission surface of the plurality of LESDs. Lighting assemblies often include an optical acquisition system that receives light generated by the LESD. For such embodiments, an illumination assembly having an essentially planar emitting surface can provide higher optical power because the optical acquisition system collects more light than has an emitting surface located at a different distance from the acquisition system. Lighting assembly. In some embodiments of the illumination assembly having acquisition optics, if the substrate supports a plurality of LESDs having different heights, the substrate can be multi-level so that at least two of the plurality of LESDs have their own emission The surface is substantially the same optical path length as the emission surface of the acquisition optics. For example, for acquisition optics having a higher index of refraction for shorter wavelength light, the I-wavelength LESD can be placed farther away than the shorter wavelength chirped acquisition optics. With these embodiments, the chromatic aberration of the illumination system can be largely corrected. In addition, the heat generation of the LESD can be used to adjust the substrate thickness and/or cavity surface area for better heat dissipation. Advantages of embodiments of the invention associated with LESD include: flexible LESD provides excellent heat dissipation (quality of J62438.doc 201242072 required for high power lesd); flexible LESD can be wired in a single flexible and insulating layer The resulting flexible LESD can be bent in a simple or composite curve; and an exemplary embodiment of a flexible LAY with a LESD for reducing the cost associated with a conventional submount is illustrated in Figure 2a. It shows a dielectric layer 12 having a first major surface 13, a second major surface 14 opposite the first major surface 13, and at least one recessed region 10. The LESD % is positioned within the recessed area 10. The bottom plate and the apparent wall of the recessed region 10 may be coated with a conductive material 18 which may be made of the same material as the conductive layer 19 or a material different from the conductive layer 19 and which may be deposited simultaneously with the conductive layer 19. The recessed regions 10 can have any suitable shape, such as circular, elliptical, rectangular, serpentine, channel, grid (i.e., large or small dielectric islands formed by successive patterns of overlapping channels), and the like. In other embodiments, the conductive material 18 can support additional layers, such as reflective coatings. The reflective coating can be a gold, silver, aluminum, intrinsically reflective dielectric material, or a colored material with enhanced reflectivity. The conductive layer 19 is positioned on the first major surface 13 of the dielectric layer 12 and the conductive layer 20 is positioned on the second major surface μ of the dielectric layer 12, as shown in Figure 2A. The conductive layer 19 may partially or completely cover the first major surface 13. The conductive material can be any suitable material, but is usually copper. In some embodiments, one or both of conductive layers 19 and 20 comprise conductive circuitry. The lesd 24 is positioned on a conductive feature 16 which may be part of the conductive layer 19 or an additional material such as a reflective coating included on the first major surface of the dielectric layer 12. [£3〇24 is insulated from LESD 26 and conductive layer 20 by a portion of dielectric layer 12 positioned beneath conductive feature 16, and in some cases conductive feature 16 may be electrically isolated conductive features 162438.doc 201242072. A portion of the dielectric layer under each coffee defines the distance between the test (and any intervening layers or materials) and the conductive layer on the second surface of the dielectric layer. This distance affects the heat transfer layer that is dissipated through the dielectric layer through the dielectric layer to the first surface of the dielectric. The dielectric layer can be a flexible dielectric layer or a rigid dielectric layer. The rigid dielectric layer can include - or a variety of materials, such as ceramics, FR4 PCB boards, or the like. The flexible dielectric layer may comprise - or a plurality of tractable non-conductive materials 'eg, polymeric materials, polyaminin, polyester, polycyclic vinegar, liquid crystal polymers, ferroelectric materials (ie, barium, titanic acid)钡), SrTi〇2 titanate or the like. The conductive layer may include - or a plurality of conductive materials 'eg 'copper, semiconductor (ie 'Shi Xi, 锗, gallium nitride, gallium gallium), Tao Jing (ie, tantalum carbide), carbon (ie, graphite 'class diamond carbon ), a transparent conductive material (ie, 'indium tin oxide, zinc oxide, etc.) or the like. In at least some embodiments of the invention, the suitable maximum thickness of the flexible dielectric layer is from about 1 micron to about 100 micro. Mining. The preferred thickness of the flexible dielectric layer beneath the recessed regions is from about 1 micron to about 1 micron. Typically, the cavity can be deeper than the recess, which is due to the thinner dielectric layer at the bottom of the cavity resulting in less structural and mechanical problems than the thin dielectric layer of the large area. If there are recessed areas having more than one depth, the depths may be any difference and may be 'but will typically differ by about 1% to about 5%. In at least some embodiments of the invention, the LESD 26 generates more heat than the lESD 24 generates heat. For example, LESD 26 can be blue or green led and LESD 24 can be a red LED. By placing the hotter LESD in the recessed region 1 ,, the heat generated by the LESD 26 travels through the dielectric layer to the conductive layer 2〇 is shorter than 162438.doc 201242072, and thus the heat generated therefrom can be further Pass to the radiator quickly. At the same time, by placing the generated heat 1ESd 24 less than the heat generated by the LESD 26 at a large distance from the conductive layer 20, the heat generated by the LESD 26 and traveling along the conductive layer 20 in the x-direction and the gamma direction is unlikely. Arrive at LESD 24 and negatively affect its operation and functionality. The amount of conductive material in the recessed area can also be controlled to further affect thermal management. The recessed area (especially the cavity) can be filled to 1% by using a conductive material. In some embodiments, this is preferred, but the recessed areas are more typically filled from about 10% to about 95% full. For example, if the cavity is 5 microns deep, in some embodiments, the conductive material is preferably 5 microns deep, but the depth of the conductive material is typically about 45 microns or less. Generally, the more conductive material is contained in the recessed area, the better the heat transfer from the LESD. 2B illustrates the comparative LESD apparatus of FIG. 2A in which the LESDs 24 and 26 are located in recessed areas 1〇 having the same depth. The bottom plate and the conditional wall of the recessed area may be coated with a conductive material 丨8. In FIG. 2B, the heat generated by the LESD 26 can be reached by LESd 24 by first traveling down the Z direction through the bottom of the recessed region 1〇 where the LESr 26 is positioned to the conductive layer 20. a thin layer of insulating material; subsequently traveling along the conductive layer 20 in the x-direction; and finally again traveling upward in the z-direction through the bottom of the conductive layer 20 and the recessed region 1 where the LESD 24 is positioned. A thin layer of insulating material between. In Figure 2B, this heat transfer is mitigated by the "electrical layer thickness region between the two recessed regions. However, having this thick region between the recessed regions occupies the surface area on the flexible LESD and will reduce the number of LESDs that can be placed in a given area. 162438.doc 12 201242072 As can be seen by comparing Figures 2A and 2B, by placing the LESDs 24 and 26 at different heights on the dielectric layer 12, the LESDs can be positioned to map each other in the X and Y directions. The 2B is closer, and a significant amount of insulating material (dielectric layer) is maintained between the LESDs. In at least some embodiments of the invention, (1) the difference between the first height and the second height and (2) the ratio of the distance between the LEDSs in the first and second regions may be any suitable ratio, but usually in From about 1:1 to about 1:10. Moreover, in some embodiments, the depth of one or more recessed regions can be adjusted such that LESD 24 and LESD 26 have a generally upper planar emitting surface. FIG. 3 illustrates an exemplary embodiment of a lighting system 300. The illumination system 300 can include a substrate 310, a first light emitting semiconductor device (LESD) 320, a second light emitting semiconductor device (LESD) 330, and an optional optical acquisition system 39A. The first LESD 320 has a first height and the second LESD 330 has a second height that is different from the first degree of §. The first LESD 320 and the second LESD 330 can face the optical acquisition system 390. Optical acquisition system 390 has LESD-directed light entering major surface 391 and light emitting major surface 392. The substrate 31 has a first major surface 312 and a second major surface 314 opposite the first major surface 312. The first major surface 312 faces the optical acquisition system 390. The substrate 31A can include at least a first region 370 supporting the first LESD 320 and a second region 380 of at least the second LESD 330 of the branch. The first region 370 has a first region height A' which can be indicated by the distance between the surface of the first region 370 and the second major surface 314 of the substrate 31〇. Similarly, the second region 38A has a second region that is highly private' which can be indicated by the distance between the surface of the second region 38〇 and the first major surface 314 of the substrate 310. In some embodiments 162438.doc • 13· 201242072, the first region height 仏 is different from the second region height such that the first LESD 320 and the second LESD 330 have substantially planar emission surfaces. In some embodiments, the difference in height between the first and second regions can be substantially the same as the difference in height between the first LESD 320 and the second LESD 330. In some embodiments of the illumination system 3 including the optical acquisition system, the emission surface of the first LESD 320 and the emission surface of the second LESD 33 are at substantially the same distance from the optical acquisition system 390. The optical acquisition system can include any acquisition optics such as lenses, integrating rods, parabolic mirrors, encapsulants, or the like. In some other embodiments, the first region height 沁 is different from the second region height horse such that the first LEsd 32 〇 and the second LESD 330 have substantially the same light from the light emitting major surface 392 of the optical acquisition system 39 〇 Length of the process. In some embodiments, substrate 310 can include a dielectric layer 34(). In some other embodiments, substrate 310 can include conductive layer 350 at first major surface 312. The substrate 310 can be included in another conductive layer 360 at the second major surface 314 of the substrate 31, as appropriate. In a particular embodiment, the dielectric layer 34 is designed to have a first dielectric layer height at the first region 370 and a second dielectric layer height at the second region 380. The electrical layer height ο% is different from the second dielectric layer twist, as illustrated in FIG. In some embodiments, the difference between the first and first dielectric layer heights can be substantially the same as the height difference between the first LESD 320 and the second LESD 330 to achieve substantially the first and second LESDs. Plane emitting surface. 4A through 4F illustrate several example configurations of the lighting assembly 400. Photo

The Ming assembly 400 can include a substrate 410, a first LESD 420, and a second LESD 162438.doc 14 201242072 430. The height of the first LESD 420 may be different from the height of the second LESD 43. Substrate 410 includes a first major surface 412 and a second major surface 414 opposite first major surface 412. The substrate 410 may include a first region 470 supporting at least the first 1⁄4〇42〇 and a second region 48〇 supporting at least the second LESD 43〇. The first region height may be different from the second region height such that the first lesd 420 and the second LESD 430 have a substantially planar emitting surface. The substrate 41A may include a dielectric layer 440 and a conductive layer 450. The substrate 41A may include a second conductive layer 460, as appropriate. In the exemplary embodiment illustrated in FIG. 4A, the difference in height between the first region and the height of the second region is obtained by different thicknesses of the dielectric layer 440 at the first region 47A and the second region 480. As illustrated in FIG. 4B, in an exemplary embodiment of the illumination assembly 4, the conductive layer 450 is designed to have a first conductive layer height at the first region 47〇 and a second region 480 at the second region 480 The second conductive layer height <: / ^, the first conductive layer height is different from the second conductive layer height. The height of the conductive layer can be understood as the height of the conductor below each LESD or between the LESD and the dielectric layer. The difference between the height of the first conductive layer CA and the height of the second conductive layer may be substantially the same as the difference between the heights of the first LESD 420 and the second LESD 430. 4C illustrates an exemplary embodiment of a lighting assembly*(10) having a recessed support region. The first region 47 of the substrate 41 is at the same level as the first major surface 412 of the substrate 410. The second region 480 of the substrate 41 is recessed. The dielectric layer 44 has a first dielectric layer height at the first region 47〇 and a second dielectric layer height at the second region 48〇. The first dielectric layer height is different from the second dielectric layer height of the stallion such that 162438.doc -15-201242072 LESD 420 and LESD 430 have an essentially planar emitting surface. 4D illustrates another exemplary embodiment of an illumination assembly 400 in which the dielectric layer 440 is completely etched at the second region 480. The conductive layer 450 has a first conductive layer height C7// different from the second conductive layer height CT/2 to offset the difference in height between the first LESD 420 and the second LESD 430 and the difference in dielectric layer thickness. 4E illustrates yet another exemplary embodiment of illumination assembly 400 in which dielectric layer 440 is completely etched at both first region 470 and second region 480. The conductive layer 450 can have a first conductive layer height CT/7 that is different from the second conductive layer height CT/2 to offset the difference in height between the first LESD 420 and the second LESD 430. In some embodiments, a first photolithography process can be applied to create two regions of substantially the same thickness. Subsequently, the first region 470 can be masked and a second photolithography process can be applied to create an additional layer of conductive material at the second region 480. 4F illustrates yet another exemplary embodiment of a lighting assembly 400 in which conductive material 455 having different thicknesses is disposed in first region 470 and second region 480. Conductive material 455 can be, for example, a conductive paste, solder, or the like. In some embodiments, the conductive material 455 can have different thicknesses to support the first LESD 420 and the second LESD 430 of the appropriate height. Figure 5A illustrates an exemplary embodiment of a LES device 500A in which LESDs 524 and 526 are disposed in adjacent recessed regions 510 that are small cavities of different depths. The LESD device 500A includes a conductive layer 519, a dielectric layer 512, and a second conductive layer 520. In this embodiment, the recessed area holds the cavity of the individual LESD. As with the embodiment illustrated in FIG. 2A, this allows the LESD 526 that generates the higher heat to be placed on a portion of the first major surface 513 having the second level 162438.doc -16 - 201242072 electrical layer 512, LESD 526 is disposed in close proximity to the second conductive layer 520, and is disposed by placing 1^3〇 524 on a portion of the first major surface 513 of the dielectric layer 512 having a first degree of homogeneity greater than the second height. The LESD 524 remains insulated from the heat generated by the LESD 526. In at least some embodiments of the invention, the second height is between about 1% and about 9% less than the first height D/^. 5B illustrates an exemplary embodiment of a LES device 5B in which the LESD 524 is disposed on a conductive feature of the conductive layer 519, and the conductive layer 519 is at the dielectric layer 512 at the maximum thickness of the dielectric layer 512. The Deng surface of a major surface 513 is positioned, and the LESD 526 is positioned on the conductive features in the recessed area 5i, and the recessed area 51 can position the recesses of the plurality of LESDs. The recess can be as wide as the full width of the dielectric layer 512 and can also extend along the length of the dielectric layer 512 such that the recessed regions effectively stepwise change at the level of the dielectric layer. In other embodiments, there may be a plurality of recesses 510 interspersed with large non-recessed regions. Figure 6A illustrates another exemplary embodiment of a LES device 600A in which recessed regions of different heights and sizes are present. The LESD 600A can include a dielectric layer 612, a conductive layer 619 that partially or completely covers the first major surface 613, and a conductive layer 62 that partially or completely covers the second major surface 614. In this embodiment, the LESD 624 is placed over the conductive features of the conductive layer 619 at a first height, the first height being at the maximum thickness of the dielectric layer 612. The LESD 626 is positioned on the conductive feature on a portion of the first major surface 613 of the dielectric layer 612 at a third height in the recessed region 6i 〇c, the recessed region 610C is a small cavity, and the LESD is 628 is positioned in the recessed area 162438.doc • 17· 201242072 The second height in the field 610L is a conductive feature on a portion of the first major surface 6i3 of the dielectric layer 612 where the recessed region 610L can be positioned The depression of LESD. The height of the portion of the dielectric layer 612 below the recessed region 61A is less than the maximum height of the dielectric layer 612 but greater than the height of the portion of the dielectric layer 612 below the recessed region 610C. This intermediate height can be adapted, for example, to an LED having a level of heat generated between LESD 624 and 626. In some embodiments of the invention, the second height is between about 10% and about 90% less than the first height and the third height is between about 10% and about 90% less than the second height . Figure 6B illustrates a perspective view of an exemplary embodiment of a LES device 600B similar to the LES device 600A illustrated in Figure 6A. The wleSD 624 is disposed on the conductive characteristics of the conductive layer 619 on the first major surface 613 of the dielectric layer 612. The LESD 62 8 is placed over the conductive features within the recessed area 61 0L. The LESD 626 is disposed on a conductive feature within the recessed region 610C that is a cavity formed in the surface of the recessed region 610L. Conductive layer 619 includes circuitry that spans a first major surface of dielectric layer 612, the first major surface including a surface of recessed region 610L. In this way, many LESDs can be connected to the circuitry of the flexible LESD. In some embodiments, the height of the recessed regions can be adjusted such that at least some of the LESDs included in the LESD device have a substantially planar emitting surface relative to each other. As shown in FIG. 6B, in some embodiments, one or more of LESDs 624, 626, and 628 can be wire bonded to a conductive circuit comprising conductive layer 19. Conductive layer 620 is preferably thermally conductive and electrically conductive as appropriate. In some embodiments, the conductive layer 620 includes conductive circuitry. In some embodiments, passivation or bonding 162438.doc -18-201242072 layers are positioned below LESD 624, 626, and 628 to facilitate bonding one or more of LESD 624, 626, and 628 to the underlying layer. Figures 7A and 7B illustrate an embodiment of an illumination assembly 700 having an integrating rod and four LESDs having emitting surfaces at different levels. Figure 7A is a side view of illumination assembly 700 and Figure 7B is a perspective view of illumination assembly 700. The illumination assembly 700 includes a LESD 710 (not shown in Figure 7A), a LESD 715, a LESD 720 (not shown in Figure 7A), a LESD 725, and an integrating rod 730 that acts as a collection optics. The integrating rod 730 has an entry surface 73 5 for collecting light from the LESD and an exit surface 73 7 (not shown in Fig. 7B) for outputting light. The LESD 715 has the emission surface closest to the integrating rod of the four LESDs and the LESD 720 has the emission surface furthest from the integrating rod in the four LESDs. In an exemplary embodiment, LESD 715 is a red LED with a height of 225 um; LESD 710 and 725 are green LEDs with a height of 170 um; LESD 720 is a blue LED with a height of 100 um; all four LESDs have 0.25 W output power; the integrating rod 730 is 5 mm long with a 2 mm X 2 mm entry surface 735 and a 2 mm X 3 mm exit surface 737; and the integrating rod 730 is placed at the top surface LESD 715 (ie, facing the integrating rod 730) Surface) 0.1 mm. The optical power entering the integrating rod is 0.83353 W and the optical power output from the integrating rod is 0.82955 W. In contrast, Figures 8A and 8B illustrate an embodiment illumination assembly having optical components identical to those of the illumination assemblies illustrated in Figures 7A and 7B, but with four LESDs having emission surfaces on a common plane. Figure 8A is a side view of illumination assembly 800 and Figure 8B is a perspective view of illumination assembly 800. In an exemplary embodiment having the same components as the above examples, wherein the integrating rod 162438.doc -19-201242072 730 is placed 0.1 mm from the emitting surface of the four LESDs, the optical power of the integrating rod is 0.903 W. And the optical power output from the integrator rod is 0.89856 W. As demonstrated in such examples, the illumination assembly of the LESD having substantially planar emitting surfaces (relative to each other) can provide higher illumination power than the LESD has an emission surface at different heights (relative to the acquisition optics or optics) Assembly. At least one embodiment of the present invention provides a flexible LESD array configuration using a partially etched dielectric layer. The recessed regions are etched to a desired depth in the dielectric layer. The recessed regions may have a conductive material deposited therein in any suitable manner (e.g., coating, vapor deposition, plating, etc.), but the conductive material is typically plated using electroplating or electroless plating. The LESD is typically attached directly or indirectly to the conductive material using known die bonding methods such as eutectic, solder (including solder bumps for flip chip mounting), adhesives, fusion bonding, or other bonding methods. Suitable dielectric layers of the present invention include polyesters, polycarbonates, liquid crystal polymers, and polyimines. Polyimine is preferred. Suitable polyimines include those available under the trade names KAPTON, available from DuPont, Wilmington, Delaware; APICAL, available from Kaneka Texas, Pasadena, Texas; SKC Kolon PI, available from SKC Kolon PI, purchased from Anyang, South Korea; and UPILEX and UPISEL, available from Ube-Nitto Industries, Tokyo, Japan. The most preferred are the polyimines available under the trade names UPILEX S, UPILEX SN and UPISEL VT, all available from Ube-Nitto Industries, Tokyo, Japan. These polyimines are prepared from monomers such as biphenyl tetraruthenic dianhydride 162438.doc -20- 201242072 (BPDA) and phenylenediamine (PDA). The indentation region can be formed in the dielectric layer using any suitable method (e.g., chemical etching, plasma etching, spotlighting, laser stripping, microreplication, embossing, and injection molding). In some embodiments, Chemistry (4) may be preferred. Any-money engraving agent can be used and its visible dielectric layer material can be varied. Suitable etchants may include alkali metal salts such as potassium hydroxide; one or both of an alkali metal salt with a solubilizing agent (e.g., an amine) and an alcohol (e.g., ethylene glycol). Chemical etchants suitable for use in some embodiments of the invention include potassium hydroxide (k〇h), ethanolamine, and ethylene glycol (tetra) 胄', such as those described in more detail in U.S. Patent Publication No. 2007-0120089-Α1, This case is incorporated herein by reference. Other chemical etchants suitable for use in some embodiments of the present invention include bismuth and glycine etchants, such as those described in more detail in co-pending U.S. Patent Application Serial No. 61/409,791, the The citations are incorporated herein by reference. The dielectric layer can be treated with an alkaline KOH/potassium permanganate (PPM) solution (e.g., a solution of about 7 wt% to about OH OH and about 3 wt 〇 / o KMn 〇 4) after etching. In at least one embodiment of the invention, the 'UPISEL VT dielectric layer forms a suitable starting material for the dielectric layer of the present invention, especially if the recessed region is formed by chemical etching." UPISEL. VT is comprised of UPILEX S. The core layer and a thin outer layer structure comprising a thermoplastic polyimine (TPPI). UPISEL ντ can be etched using any suitable chemical such as K〇H/ethanolamine/ethylene glycol, as described in more detail in U.S. Patent Publication No. 2007_0120089_A1. With this etchant, the hydrophobic nature of the UPILEX S and the higher modulus can be etched by the dissolution mechanism, which produces the side of the extremely smooth recessed region 162438.doc -21 - 201242072 wall. Since the etchant formulation etches quickly, the etch can be stopped before the recessed regions reach the second TPPI layer. Subsequently, a subsequent etch can be performed using a KOH/potassium permanganate (PPM) solution comprising about 0.7 wt% to about 1.0 wt% KOH and about 3 wt% ΚΜη04, which is not an effective etchant for the TPPI layer, to remove The residual thin layer of the UPILEX S core leaves a thin TPPI layer at the bottom of the buttoned recessed area. Another suitable etchant chemistry for use in the singular UPISEL VT is the KOH/glycine chemical KOH and glycine acid as described in more detail in co-pending U.S. Provisional Patent Application Serial No. 61/409,791. The etchant is extremely suitable for etching UPISEL VT's because it provides a slow and controlled etch which makes it possible to control the thickness of the dielectric material at the bottom of the recessed region of the button. As previously mentioned, 'as a chemical surname' Alternatively, recessed regions may be formed in the dielectric layer by plasma etching, focused ion beam etching, laser ablation, embossing, microreplication, injection molding, and other suitable methods. With these methods of forming the recessed regions, the sidewalls typically have, for example, at most 9 turns. At steeper angles, if embossing, microreplication, or injection molding is used, the sidewalls of any desired angle can be formed. The recessed regions having different depths can be formed in the dielectric layer of the present invention by any suitable method, such as multi-pass etching or grayscale etching. For example, to use a multi-pass process, the dielectric layer is coated with a first photoresist material. The first photoresist is patterned and developed to expose the desired shape to the shape of the red cage.

And developing the surface of the second depth after the path is formed by the storm. After removing the first light, the first photoresist pattern is recessed to the depth of the second photoresist pattern and 162438.doc -22- 201242072 = having the first The depth of the recessed area of the dielectric layer area, so it is not concave to the degree [Τ recessed into the area into the money engraved. The process can be repeated if it is desired to have a third deep recessed area. Figures 9 through 9A illustrate the steps that can also be used to form the recessive etch process of the present invention. The °° domain is applied to the layer of the first layer of the dielectric layer 920 on one side from the layer of the first layer of the dielectric layer 920. In the photoresist layer of the dielectric layer, the portions of the region that are not to be etched are 9H), the cross-linked regions are 94 〇, and the regions covered by the dielectric layer (and the second) are etched during the etching step. The material 910 is an uncrosslinked region 950, and the second-resistance resist material is inquired about the p... 15盍" the electric layer is to be in the portion of the second etching step 9:: the side of the photoresist portion of the portion In the cross-linking region 950, after the first developing step, the photoresist material 910' in the uncrosslinked region (4) is removed and the photoresist material in the partially cross-linked region is partially removed or not removed. 91G. Figure YANG shows the result of the first chemical engraving step of the region of the dielectric layer _ which is not covered by the photoresist material. Figure 9E shows that the photoresist material in the remaining portion of the partially crosslinked region 960 is removed after the second development step. Figure 9F shows the results of a second chemical etching step of (iv) the region of dielectric layer 920 covered by the photoresist. This causes the dielectric layer 920' surnamed in the first chemical cooking step to be further engraved in the region 95 and such that the dielectric layer 920 exposed by the photoresist material in the partially crosslinked region is removed. (four) engraved. The figure shows that the dielectric layer 920 is coated on the "side" with a conductive layer (4) after removing the photoresist material in the cross-linked region. The conductive layer may be coated on one side or both sides of the dielectric layer _ ^ /p i -V' / . If the conductive layer is to be patterned, it can be pre-patterned, or it can be patterned during the manufacturing process of the lemd. A multilayer flexible substrate (having multiple layers of dielectric and conductive materials) can also be used as the substrate. The conductive layer can be a suitable material, but is usually copper. If the conductive layer is to be added to one or both sides after the dielectric layer is formed to a desired thickness, this can be achieved by laminating the metal foil to the dielectric layer, but more usually by a certain type. The metal deposition process is implemented. Conductive features and circuitry can be formed as part of a metal deposition process. For example, a standard semi-additive deposition method for forming a circuit can include providing a vapor-deposited bonding layer of (usually) CrOx, NiCr, or NiCrOx, a metal that typically (but not necessarily) contains the same metal as the subsequently plated metal layer. The seed layer is vapor deposited thereon, the reticle is patterned on the seed layer using a conventional photolithography process, and the conductive material (any suitable material, but usually copper) is plated using electroplating or electroless plating. At the exposed portion of the seed layer, the reticle is stripped, and the exposed portions of the residual of the seed layer and the bonding layer are removed. The conductive features of the bonded LESD may be post-passivated using gold, tin, silver, etc. to facilitate the bonding. The individual LESDs can be bonded to the conductive features using any suitable bonding mechanism. Different types of joints such as eutectic, flip chip, melt and adhesive bonding can be used. The LESD preferably has a passivation layer applied to its bottom surface (usually gold/tin, but may be any suitable purification material such as a metal such as Au and an intermetallic alloy such as AuSn, AuGe, AuSi, etc.) to facilitate The LESD is bonded to the conductive features of the gold passivation. The temperature at which the LESD is attached to the conductive features is typically between about 250 C and 325 C, and for eutectic bonding (for Au/Sn* 162438.doc -24·201242072 Lv) the most common is about 2 8 5 died. The LESD can be adhered by other methods such as organic die attach, e.g., using silver epoxy or soldering. The eutectic bonding is regarded as a direct bonding method, and the soldering is regarded as an indirect bonding method. In at least one embodiment, the dielectric substrate and the copper layer thereon provide a thin compliant support for the lesd. The flexible layer can be directly applied, for example, by applying an encapsulating material to the individual LESD and to the recessed area on or in which the lesd is positioned, or by applying an encapsulant to the LESD array and surrounding area. Encapsulate the LESD. The encapsulant is preferably a transparent (i.e., having a transparency of more than 94%, preferably more than 99%) of the molding compound. The encapsulating agent can be adapted to function as a lens when cured. Polyoxymethylene and epoxy resins are suitable for encapsulating compounds. The encapsulant may further comprise optically diffusing particles distributed therein. Suitable molding compounds are available, for example, from Shin Etsu Chemical Co., Ltd., Tokyo, Japan and NuSil Silic〇ne Techn〇l〇gy, Santa

Barbara, California purchased. If desired, a wavelength converting material such as a phosphor coating can be deposited on top of the LESD prior to encapsulation. The underfill material can be applied as appropriate prior to encapsulation of the LESD. The flexible lesd can also be enclosed in a waterproof/weatherproof transparent outer cover that can be made from any suitable transparent polymeric material. In at least one embodiment of the invention, one or more cavity structures similar to those of Figure 5 are formed in the dielectric substrate layer, the LESD is disposed in the cavity and the cavity is filled with an encapsulant covering the LESD. In at least one embodiment of the invention, the encapsulant is a transparent color shift (4) that absorbs light emitted from the LES of lesd and re-emits light of a different (usually higher) wavelength. For example, a color conversion material containing a yellow illuminant can be used to encapsulate blue 162438.doc •25· 201242072 LED, which allows white light to be produced. In some embodiments of the invention, the slope of the sidewall of the chamber can be adjusted to produce a uniform thickness of color conversion layer around the LESD to provide uniform light conversion and preferably provide superior thermal management. In at least one embodiment of the invention, the slope of the sidewall of the chamber is about five. It is about 9 miles. An advantage of at least one embodiment of the present invention is that the placement of the LESd in the cavity makes it possible to provide an accurate female encapsulant because it can be snugly contained within the cavity. An advantage of at least one embodiment of the present invention is that placing the lesd in the center of the cavity and filling the cavity with an encapsulant results in uniform light conversion due to the uniform layer of encapsulant that can be created around the LESD. In an alternative embodiment of the invention, a layer of color conversion material is applied to the bottom plate of the cavity prior to placement of the LESD in the cavity instead of encapsulating the LSD with a color conversion material. In this manner, the color conversion material can absorb at least some of the light emitted from the LESD2LES and re-emit light of a different (usually higher) wavelength. An example of a suitable color conversion material is a phosphor filled encapsulant. This encapsulant can be prepared by mixing a yellow phosphor (e.g., commercially available under the trade designation ISIPH(R) ssA6i2 from Merck) with a suitable polyoxyl encapsulant having suitable adhesion properties. In some embodiments, a weight ratio of phosphor to polyoxygen adhesive of 75% may be suitable. After dispensing the encapsulant into the cavity, in some embodiments, it can be cured by exposure to UV light for 1 hour at 8{rc. In at least one embodiment of the invention, a cavity structure similar to that illustrated in Figure 5 is formed in the dielectric substrate layer. The LESD constructed for the fully encapsulated LES is placed in the cavity. The body of lesd resides in the cavity and the wire extends to the junction on the first major surface of the dielectric layer. In another embodiment of the invention, the fully encapsulated LES structure resides in a cavity in the dielectric layer of 162438.doc -26 - 201242072. In this embodiment, the LESD is directly surface mounted to the conductive material in the cavity. In this embodiment, the joint locations of the two LESD contacts need to be electrically isolated from each other. This can be accomplished, for example, by creating a gap in the conductive material deposited in the cavity. Examples of types of fully encapsulated LES configurations that may be suitable for use in embodiments of the present invention include Golden DRAGON LEDs available from OSRAM Opto Semiconductors GmbH, Munich, Germany; LUXION LEDs from Philips Lumileds Lighting, San Available from Jose, California, USA; and XLAMP LEDs available from Cree, Durham, North Carolina. In at least some embodiments of the invention, the copper layer on one or both of the first and second surfaces of the dielectric layer and the dielectric layer supports and surrounds the LESD to provide a robust flexible LESD. The flexible LESD of the present invention can be fabricated in a batch process or in a continuous process, such as a roll-to-roll process often used to fabricate flexible circuits. The array of LESDs can be placed on a flexible substrate in any desired pattern. The LESD can then be split, for example, by stamping or by cutting the substrate, for example, into individual LESD, strips of LESD, or arrays of LESDs. Thus, the entire reel of the LESD on the flexible substrate can be transported without the need for a conventional tape-and-reel process that typically transports individual LESDs in individual pockets of the carrier strip. Prior to or after forming a strip or array of individual LESD, LESD, the flexible LESD can be attached by, for example, attaching a conductive layer on the second major surface of the dielectric layer to the additional substrate using a thermally conductive adhesive To additional substrates. The heat transfer adhesive can further facilitate heat transfer away from the LESD. Or can

S 162438.doc -27- 201242072 The conductive layer on the second major surface of the dielectric substrate is treated with a metal or other material that facilitates adhesion of the conductive layer to the additional substrate. The intended use of the flexible flexible LESD attaches it to any desired substrate. The additional substrate may be thermally and/or electrically conductive, or may be a semiconductor, ceramic or polymer substrate that is thermally or non-conductive. For example, an additional substrate may be a flexible metal substrate, a rigid metal substrate, a heat sink, a dielectric substrate, a circuit board. Wait. If the LESD is used on a circuit board, then the flexible LESD can be attached directly to the end user's circuit board, either in single, strip or array form, thereby eliminating the need for conventional lead frame materials. If the LESd is used as a lighting strip' then the flexible LESD can be enclosed in a waterproof/weatherproof transparent enclosure as described above. If the LESD is in the form of a strip or array, the LESD can be electrically connected to one or more of the strips or other LESDs in the array. Zener diodes and Schottky diodes, such as Zener diodes and Schottky diodes, can also be used, for example, by using direct wafer bonding or flip chip processes, before dividing lesd into flexible LESDs. Additional elements are added to the first or second surface of the flexible LESD. The components can also be electrically connected to the LESD. In at least one embodiment of the invention, the flexible LESD is thinner than conventional single or multiple LESD packages because the LESD is below the surface of the dielectric layer. This makes it possible to use the flexible LESD of the present invention in applications with tight volume limitations, such as cellular phones and camera flashes. For example, the flexible LESD of the present invention can provide a package profile of about 0.7 mm to 4 mm, and in some embodiments 0.7 mm to 2 mm, while conventional LESD package profiles are typically greater than 4 mm and are about 4-8 mm to 6.00 mm. . In addition, if desired, 162438.doc •28- 201242072 allows the revolving device of this month to flex or bend for easy assembly into a non-linear or non-planar assembly. In at least one embodiment, the dielectric layer and the copper layer thereon are lesd thinning compliance. In at least one embodiment, the total copper thickness is less than 2 Å, and preferably less than 100 microns, and most preferably less than 50 microns. In at least one embodiment, the thickness of the dielectric layer is preferably 5 nanometers or less. EXAMPLES The present invention is illustrated by the following examples, which are not to be construed as limiting the invention. Etching Method A general procedure for preparing an etchant involves first dissolving 37 wt% potassium hydroxide (KOH) in water by mixing, followed by subsequent addition of 3.5 wt% ethylene glycol and 22 wt% ethanolamine. A water-based photoresist (available from Chemicals, Japan under the trade name HM_4〇56) was used as an etch mask to sample a 50 μm polyacrylonitrile dielectric layer coated with 3 copper layers on one side (under the trade name upisel_n) Since Ube-Nitto Kasei Co., Ltd., Industry, Tokyo, Japan, it has undergone selective etching from the PI side. The etching is controlled by timing to produce a thin polyimide phase having a bulk thickness, which takes about 15 minutes. The circuit was formed by multiplying a 20-inch (50.8 cm) wide by 1 μm long side of a sample coated with 3 μπι copper of 50 μηι polyimine (under the trade name UPISEL-N from Ube-Nitto Kasei). Ltd., purchased by Industries, Tokyo, Japan) cut into 162438.doc -29- 201242072 13.4 inches (34.04 (^) wide. After removing 18 111 copper carrier layers from the copper ((:11) side') A dry film photoresist (commercially available from Hitachi Chemicals Co., Ltd. under the trade name HM4〇56) was laminated on both sides and a patterned etch mask was created on the polyimide side using a photolithography process in the sample. The polyamidomine domain I is thin to the bulk thickness. The sample is then subjected to a chemical etching process for about 15 minutes using the engraving method described above to produce a thinned domain having about 5 μπ1 in the polyimide substrate. The thickness of the block, the width of the thinned ρι position is about 5〇〇μηι and the width of the original PI level is about 7〇〇 (the transition wall angle is about 25 to 28.). After the photoresist is removed, the exposed PI surface of the sample is subjected to a thickness of 2 11 〇 1 to 2 by vacuum deposition. The seeding of the chrome bonding layer of 111 is then deposited on the bonding layer by vacuum deposition at a thickness of about 1 〇〇 nm to form a conductive coating. The conductive coating is then subjected to electroplating to make a conductive copper layer. Accumulated to a final thickness of about 3 μηι. This provides a conductive coating structure in the etched thinned domain of the ?1 dielectric substrate. The photoresist is then applied to the clad copper (on one side) and coated with steel. On both sides of the dielectric layer (on the other side) and patterned on both sides by re-registration photolithography. Electrodeposition of 45 μm copper onto the thin electrodeposited steel on the etched side Exposing the exposed portion of the knife and the copper-clad side. Then, after removing the photoresist from the etched side, removing the exposed portion of the 3 μηι copper layer and the chrome bonding layer to create a circuit on the dielectric substrate A conductive electrode having a thickness of 45 μm is formed on the thinned domain of the polyimide substrate and the thick polyimide phase. Example 1 The following is to encapsulate the LESD on a flexible substrate, specifically using organic grains. The attachment material is mounted blue on the thinned domain of the flexible dielectric substrate J62438.doc 201242072 Example of a coffee. A conductive circuit is formed on a thinned domain of a flexible dielectric substrate using the circuit-forming method described above. The thinned domain has a bulk thickness of about 5 μηη and a thickness of about 45 μηη Copper-plated conductive coating. Using a silver epoxy organic die attach material (available from Quantum Materials, San Diego, US), Cree EZ 290 Gen II LED (part number CA460EZ290-S2100-2)

Cree, Durham, NC, U.S.A. commercially available) bonded to a conductive coating and thermally cured at 150 ° C for 1 hour. A hand wire bonder (available from Kulicke and Soffa Industries, Inc., Fort Washington, PA USA under the trade designation 4524d) was used and each LED wire was bonded to the top of the dielectric substrate using a gold bond pad using a 1 mil diameter gold wire. Conductive circuit on the surface. Use model EX4210R (voltage rating 42 V, current rating 1〇 a) since

Thurlby Thandar Instruments, Inc. (TTi), Huntingdon,

A power test assembly purchased by Cambridgeshire, United Kingdom. The LED is free of blue when the point is free and the assembly shows agility. Example 2 The following is another example of mounting a LESD on a flexible substrate, in particular using a direct grain bond to mount a blue LED on a thinned domain of a flexible dielectric substrate. A conductive circuit is formed on the thinned domain of the flexible dielectric substrate using the circuit-forming method described above. The thinned domain has a bulk thickness of about 5 μπ1 and a copper-coated conductive coating of about 45 μm. Bonding Cree EZ 290 Gen II LED (part number CA460EZ290-S2100-2 from Cree, Durham, NC, USA, 162438.doc 31-201242072) to the conductive coating using [solder between the ED and the conductive coating) . Use a manual wire bonder (available under the trade name 4524D from Kulicke and Soffa Industries, Fort Washington, PA, U.S.A.) and utilize it! The mil diameter gold wire bonds each LED wire to a conductive circuit on the top surface of the dielectric substrate via a gold bond pad. A power test assembly commercially available from Thurlby Thandar Instruments, Inc. (TTi), Huntingdon, Cambridgeshire, United Kingdom, using model EX4210R (voltage rating 42 V, current rating 10 A). The LED is bright blue when illuminated and the assembly shows flexibility. Example Embodiment 1 An illumination system comprising: an optical acquisition system, a first light emitting semiconductor device (LESD) having a first height, the first LESD facing the optical acquisition system, and a second light emitting semiconductor device (LESD) 'Having a second height different from the first height', the second LESD facing the optical acquisition system, the substrate having a first region and a second region, the first region having at least the first LESD and the first The second region supports at least the second lESd, and the first region has a first region degree ' different from the height of the second region of the second region such that the emission surface of the first LESD and the emission surface of the second LESD are at a distance The optical optical collection system is at substantially the same distance. 2. The illumination system of embodiment 1 wherein the optical acquisition system comprises a lens. 3. The illumination system of embodiment 1, wherein the optical acquisition system comprises an integrating rod. 4. The illumination system of embodiment 1, wherein the substrate comprises a conductor layer having a first conductor layer height at the first region and a second conductor at the second region The height of the layer, the height of the first conductor layer is different from the height of the second conductor layer. 5. The system of claim 1, wherein the substrate comprises a dielectric layer, the dielectric layer being designed to have a first dielectric layer height at the first region and at a second region of β There is a second dielectric layer height, the first dielectric layer height being different from the second dielectric layer height. 6. The illumination system of embodiment 5 wherein the dielectric layer comprises a polyimide core and a thermoplastic polyimide layer on one side of the core. The illumination system of embodiment 1, wherein the light emitting semiconductor device is an intermediate light emitting semiconductor structure. 8. The illumination system of embodiment 1, wherein the light emitting semiconductor device is an encapsulated light emitting semiconductor construction. 9. The illumination system of embodiment 1, wherein at least one of the first region and the second region is a recessed region. 1 . The illumination system of embodiment 9, wherein the recessed region is a cavity. 11. The illumination system of embodiment 10 wherein the cavity is filled with a phosphor filled encapsulant. 12. A lighting assembly comprising: a first light emitting semiconductor device (LESD) having a first height, a second light emitting semiconductor device (LESD) having a second height different from the first height, The electrical layer 'has a first region and a second region, the first region supporting at least the first LESD and the second region supporting the first:LESD, and the first region has a different The first region height of the second region of the second region is such that the first LESD and the second LESD have a substantially planar emitting surface. 13. The illumination assembly of embodiment 12, further comprising: an optical acquisition system facing the first LESD and the second LESD. M. The illumination assembly of embodiment 13, wherein the optical acquisition system comprises a lens. The illumination assembly of embodiment 13, wherein the optical acquisition system comprises an integrating rod 3 16. The illumination assembly of embodiment 12, further comprising: a conductor layer on top of the dielectric layer, the conductor layer The first region has a first conductor layer height and a second conductor layer height at the second region, and the first conductor layer height is different from the second conductor layer height. 17. The illumination assembly of embodiment 12 wherein the light emitting semiconductor device is an intermediate light emitting semiconductor construction. 18. The illumination assembly of embodiment 12 wherein the light emitting semiconductor device is an encapsulated light emitting semiconductor construction. 19. The illumination assembly of embodiment 12, wherein the dielectric layer comprises a polyimide core and a thermoplastic polyimide layer on one side of the core. 20. The illumination assembly of embodiment 12 wherein at least one of the first region and the second region is a recessed region. 21. The illumination assembly of embodiment 20, wherein the recessed region is a lumen. 22. The illumination assembly of embodiment 21 wherein the cavity is filled with a phosphor filling 162438.doc • 34-201242072 encapsulant. 23. A method, comprising: providing an optical acquisition system; a first region of height providing a substrate having first and second major surfaces and having a first domain; generating at least one recessed surface on the first major surface The second region is such that the second region has a second high yield less than the first height and a is disposed at least one of the light emitting semiconductors (4) to each of the first and second regions of the optical system. 24. The method of embodiment 23, wherein the substrate comprises a dielectric layer. 25. The method of embodiment 24, wherein the substrate is a conductive layer on top of the layer. A step is included in the dielectric. 26. The method of embodiment 25, wherein the conductive layer comprises circuitry. 27. The method of embodiment 23, wherein the first major surface of the dielectric layer is produced by a method selected from the group consisting of chemical (4), electro-optic, focused ion beam, and laser stripping Second area. 28. The method of embodiment 23, wherein the at least one recessed second region is chemically etched using an etchant solution comprising a gas oxidizing off, ethanolamine, and ethylene glycol. The method of embodiment 28, wherein the at least one recessed second region is further etched by a neutralizing agent solution comprising an indicating potassium permanganate. 30. The method of embodiment 23, wherein the at least one recessed second region is chemically etched using an etchant solution comprising a hydroxide desorbing and glycine. 3. The method of embodiment 23, wherein the at least one recessed second region is further etched by including an inspective high 162438.doc -35 - 201242072 engraved linger solution. 32. An object comprising: a flexible dielectric layer, and a right flute a ^ ± ± a head eight having a first and first major surface, the first major surface having a first to a height of > a region and at least one second region having a second height that is not 5 degrees, wherein the first region supports at least one of the first light emitting semiconductor devices (LESD) and the second region supports at least one second light emitting a semiconductor device (LESD); and a first conductive layer on the first major surface of the dielectric layer. 33. The article of embodiment 32, wherein the first height is greater than the second height. 34. The article of embodiment 33, wherein the first height is a maximum height of the dielectric layer. 35. The article of embodiment 33, wherein the second height is formed by removing material from the first major surface. The object of any one of embodiments 32 to 34, wherein the second LESD generates more heat than the first LESD generates heat. 37. The article of embodiment 32, wherein the first height and the second height are both less than a maximum height of the flexible dielectric layer and the second height is less than the first height. 38. The article of embodiment 32, wherein the second region is a recessed region. 3. The article of embodiment 38, wherein the recessed region is a lumen. 40. The article of embodiment 32, wherein the first and second regions are recessed regions of the cavity. 41. The article of embodiment 32, wherein the ratio of the difference between the first height and the second height is 162 438.doc • 36 · 201242072 and the distance between the LEDs in the first and second regions is about 1:1. To about 1:1 〇. 42. The article of embodiment 32, wherein the first region is a recessed recessed region and the second region is a recessed region of the cavity. 43. The article of embodiment 32, further comprising at least a third region' having a third higher than the first and second heights, the third region of the third light emitting semiconductor device. 44. The article of embodiment 32, wherein the second illuminating semiconductor device generates more heat during operation than the heat generated by the first illuminating semiconductor device. 45. The article of embodiment 32, wherein the third luminescent semiconductor device generates more heat during operation than the first and second illuminating semiconductor devices. 46. The article of embodiment 32, wherein the second height is between about 10% and about 90% less than the first height. 47. The article of embodiment 32, wherein the second height is between about 90% less than the first height and the third height is between about 1% and about 90% less than the second height. 48. The article surface of embodiment 32 having a conductive layer. 49. The conductive layer of the article of embodiment 48 comprising the circuit 50. The article of embodiment 32, wherein the flexible dielectric layer comprises a polyimide core and a thermoplastic polymer on the side of the core A layer of quinone imine. 51. The article of embodiment 32, wherein the light emitting semiconductor device is m wherein the second major surface of the dielectric layer is configured on the second major surface of the dielectric layer 162438.doc • 37· 201242072 LES. 52. The article of embodiment 32 wherein the light emitting semiconductor device is an intermediate LES configuration. 5. The article of embodiment 32 wherein the light emitting semiconductor device is in a fully encapsulated LES configuration. 5. The article of embodiment 32 wherein the cavity is filled with a disc filled encapsulant. 55. A method, comprising: providing a flexible dielectric layer having first and second major surfaces and a first region having a first height; generating at least one recessed second region on the first major surface The second region has a second height less than the first height; a conductive layer is formed on the first major surface of the dielectric layer; and at least one LES is disposed in each of the first and second regions One. One step is included on the first major surface, and the second region has a smaller than the fifth method. The method of the fifth embodiment is to generate at least one recessed third region first and second third. height. 57. The method of embodiment 55 wherein the conductive layer on the first major surface of the dielectric layer comprises circuitry. 5 8 - The method of Embodiment 5 5, and the step of introducing a conductive layer on the two major surfaces of the dielectric layer. 59. The method of embodiment 58, wherein the conductive layer on the second major surface of the dielectric layer comprises circuitry. The method of embodiment 55, wherein the method is selected from the group consisting of chemical etching, plasma button etching, focused ion beam etching, and laser stripping in the present dielectric layer. The second region is created in the first major surface. 61. The method of embodiment 55, wherein the at least one recessed second region is chemically etched using an etchant solution comprising potassium hydroxide (k〇h), ethanolamine (ΜΕΑ), and ethylene glycol (MEG). 62. The method of embodiment 61, wherein the at least one recessed second region is further engraved by an etchant solution comprising an alkaline potassium permanganate. 63. The method of embodiment 5, wherein the at least one recessed second region is chemically etched using an etchant solution comprising K〇H and glycine. 64. The method of embodiment 63, wherein the at least one recessed second region is further surnamed by a buttoning agent solution comprising an alkaline potassium permanganate. 65. An illumination system comprising: an optical acquisition system having a light entering a major surface and a light emitting surface opposite the light entering the major surface, a first light emitting semiconductor device (LESD) having a first height, the first A light of the LESD facing the optical acquisition system enters a major surface, a second light emitting semiconductor device (LESD) having a first intensity different from the first height 'the second LESD facing the light entry of the optical acquisition system a main surface, and a substrate having a first region and a second region, the first region having at least the first LESD and the second region supporting at least the second lESd, and the first region having a different second The first region of the second region of the region is south. 162438.doc -39- 201242072 66. The illumination system of embodiment 65 wherein the first region height is different from the second region height such that an emission surface of the first LESD and an emission surface of the second LESD are at a distance The light from the optical acquisition system enters the main surface at substantially the same distance. 67. The illumination system of embodiment 65 wherein the first region height is different from the second region height such that the emission surface of the first LESD and the emission surface of the second LESD are located from the optical acquisition system The light emitting main surface is substantially the same length of the optical path. While the invention has been illustrated and described with respect to the preferred embodiments of the preferred embodiments of the preferred embodiments, The examples do not depart from the scope of the invention. This application is intended to cover any adaptations or variations of the preferred embodiments discussed herein. Therefore, the invention is intended to be limited only by the scope of the claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B provide illustrative ray trace diagrams of illumination assemblies having different configurations; FIG. 2A illustrates an exemplary embodiment of a flexible LES device; FIG. 2B illustrates a comparison LESD of FIG. 2A. Figure 3 illustrates a schematic cross-sectional view of an exemplary embodiment of a lighting system; Figures 4A-4F illustrate schematic cross-sectional views of several example configurations of a lighting assembly; Figures 5A and 5B illustrate an example of a LES device Schematic cross-section of an embodiment 162438.doc • 40 201242072 FIG. 6A illustrates a schematic cross-sectional view of another exemplary embodiment of a LES device; FIG. 6B illustrates a LES similar to the LES device illustrated in FIG. 6A A schematic perspective view of an exemplary embodiment of a device; Figures 7A and 7B illustrate an embodiment of an illumination assembly having an integrating rod and four LESDs having emitting surfaces at different levels. Figure 7A is a side view and Figure 7B is a perspective view of the illumination assembly; Figures 8A and 8B illustrate an embodiment illumination assembly having optical components identical to those of the illumination assemblies illustrated in Figures 7A and 7B, but four Each lesd has an essentially + face emitting surface. Figure 8A is a side view of the illumination assembly and Figure 8B is a perspective view thereof; and Figures 9A through 9G illustrate the steps that may be used to form an exemplary etching process for the recessed regions of the present invention. [Main component symbol description] 10 recessed region 12 dielectric layer 13 first main surface 14 second main surface 16 conductive feature 18 conductive material 19 conductive layer 20 conductive layer 24 light emitting semiconductor device 162438.doc £ -41 . 201242072 26 Semiconductor device 100A illumination assembly 100B illumination assembly 110A illumination semiconductor device 1 10B illumination semiconductor device 120A illumination semiconductor device 120B illumination semiconductor device 140A region 140B region 150 optical acquisition system 300 illumination system 310 substrate 3 12 first major surface 314 second main Surface 320 First Light Emitting Semiconductor Device 330 Second Light Emitting Semiconductor Device 340 Dielectric Layer 350 Conducting Layer 360 Conducting Layer 370 First Area 380 Second Area 390 Optical Acquisition System 391 Light Entering Main Surface 392 Light Emitting Main Surface 162438.doc • 42 - 201242072 400 illumination assembly 410 substrate 412 first major surface 414 second major surface 420 first light emitting semiconductor device 430 second light emitting semiconductor device 440 dielectric layer 450 conductive layer 455 conductive material 460 second conductive layer 470 first region 480 second Region 500A Light Emitting Semiconductor Device 500B Light Emitting Semiconductor Device 510 Recessed Region 512 Dielectric Layer 513 First Main Surface 519 Conducting Layer 520 Second Conducting Layer 524 Light Emitting Semiconductor Device 526 Light Emitting Semiconductor Device 600A Light Emitting Semiconductor Device 600B Light Emitting Semiconductor Device 610C Concave Region 162438 .doc • 43- 201242072 610L recessed area 612 dielectric layer 613 first major surface 614 second major surface 619 conductive layer 620 conductive layer 624 light emitting semiconductor device 626 light emitting semiconductor device 628 light emitting semiconductor device 700 lighting assembly 710 light emitting semiconductor device 715 illuminating semiconductor device 720 illuminating semiconductor device 725 illuminating semiconductor device 730 integrating rod 735 entering surface 737 leaving surface 800 illuminating assembly 910 photoresist material 920 dielectric layer 930 conductive film / conductive layer 940 parent unit area 950 non-parent area 960 Partially cross-linked area 162438.doc • 44·

Claims (1)

201242072 VII. Patent application scope: 1. An illumination system comprising: an optical acquisition system having light entering a main surface and a light emitting surface opposite to the light entering the main surface, a first light emitting semiconductor device (LESD) having a first height, the light of the first LESD facing the optical acquisition system entering the main surface, a second light emitting semiconductor device (LESD) having a first twist different from the first height, the first LESD facing the optical The light of the acquisition system enters the main surface, and the substrate has a first area and a second area, the first area supporting at least a D first first LESD and the second area at least a second floor of the branch, and the second area The first region has a first region height that is different from the height of the second region of the second region. 2. The illumination system of claim 1, wherein the first region height is different from the second region height such that the emission surface of the first LESD and the emission surface of the second LESD are located from the optical acquisition system The light enters the main surface at substantially the same distance. 3. The illumination system of claim 1, wherein the first region height is different from the second region height such that the emission surface of the first LESD and the emission surface of the second LESD are located from the optical collection system The light emitting main surface is substantially the same length of the optical path. 4. The illumination system of claim i, wherein the optical acquisition system comprises a lens. 5. The illumination system of claim 1, wherein the optical acquisition system comprises an integral 162438.doc 201242072 pole. 6. The illumination system of the requester, wherein the substrate comprises a conductive layer having a first conductive layer height at the first region and a second conductive layer height at the second region. The height of the conductive layer is different from the height of the second conductive layer. 7. The solar system of claim i, wherein the substrate comprises a dielectric layer, the dielectric layer being designed to have a first dielectric layer height at the first region and at the second region Having a second dielectric layer high 纟 'the first dielectric layer height is different from the second dielectric layer height. 8. The illumination system of claim i, wherein the light emitting semiconductor device is an inter-semiconductor semiconductor structure. 9. An illumination system as in the item i, wherein the light-emitting semiconductor device is encapsulated by a light-emitting semiconductor. 10. A lighting system as claimed, wherein at least one of the first region and the second region is a recessed region. U. The illumination system of claim 10, wherein the recessed region is a cavity. 12. The illumination system of the item ii, wherein the cavity is filled with a lining-filled encapsulant. 13. A lighting assembly comprising: a first illuminating semiconductor device (LESD) having a first a second light emitting semiconductor device (LESD) having a second height different from the first height, and an electrical layer having a first region and a second region, the first region supporting at least the first LESD And the second area at least the second I62438.doc 201242072 LESD, and the first area has a first area height different from the second area of the second area, so that the first LESD and the first The two LESDs have a substantially planar emitting surface. 14. The illumination assembly of claim 13, further comprising: an optical acquisition system facing the first LESD and the second [ESD. 15. The illumination assembly of claim 14, wherein the optical acquisition system comprises a lens. 16. The illumination assembly of claim 14, wherein the optical acquisition system comprises an integrating rod. 17. The illumination assembly of claim 13, further comprising: a conductive layer on top of the dielectric layer, the conductive layer having a first conductive layer height at the first region and having a second region at the second region The second conductive layer is of a height, and the first conductive layer height is different from the second conductive layer height. 18. The illumination assembly of claim 3, wherein the light emitting semiconductor device is an intermediate light emitting semiconductor structure. 19. The illumination assembly of claim 13, wherein the light emitting semiconductor device is an encapsulated light emitting semiconductor construction. 20. The illumination assembly of claim 13, wherein the dielectric layer comprises a polyimide core and a thermoplastic polyimide layer on one side of the core. 21. The illumination assembly of claim 13, wherein at least one of the first region and the second region is a recessed region. 22. The illumination assembly of claim 21, wherein the recessed region is a lumen. 23. The illumination assembly of claim 22, wherein the cavity is filled with a phosphor filled 162438.doc 201242072 encapsulant. 24. A method comprising: providing an optical acquisition system; providing first and second mains a surface and a substrate having a first region of a first height; generating at least one recessed second region on the first major surface such that the second region has a second height less than the first height; and at least one A light emitting semiconductor is disposed on each of the first and second regions facing the optical system. The method of claim 24, wherein the substrate comprises a dielectric layer. 2 6 The method of claim 2, wherein the substrate is further provided with a conductive layer on top of the dielectric layer. 27. The method of claim 26, wherein the conductive layer comprises circuitry 28. The article comprises: a drawable dielectric layer having first and second major surfaces, the first major surface having at least one a first region of the first height and a second region having at least one second height different from the first height, wherein the first region is at least a branch-first light-emitting semiconductor device (LESD) and the f-region Supporting at least one second light emitting semiconductor device (LESD); and a first conductive layer on the first surface of the upper surface of the electrical layer. 29. The object of claim 28, 30. The object, the surface removal material is shaped to be $31. The object of claim 28, wherein the first height is greater than the second height, wherein the second height is generated by the first LED from the second LESD More than the heat generated by the LESD of the first I62438.doc 201242072. 32. The object of claim 28, wherein the difference between the first height and the second height is the same as the LESD in the first and second regions The ratio of the spacing is from about 1:1 to about 1:10. 33. An object, wherein the first region is a recessed recessed region and the third region is a recessed region of the cavity. 34. The object of claim 28, wherein the second major surface of the dielectric layer has a conductive layer. The method of: providing a flexible dielectric layer having first and second major surfaces and a first region having a first height; generating at least one recess on the first major surface a second region having a second height less than the first height; a conductive layer being formed on the first major surface of the dielectric layer; and at least one LES disposed in the first and second regions 36. 37. The method of claim 35, wherein the conductive layer on the first major surface of the dielectric layer comprises circuitry. The method of claim 35, further comprising A conductive layer is formed on the second major surface of the dielectric layer. 162438.doc