TW201240318A

TW201240318A - Multilevel inverter

Info

Publication number: TW201240318A
Application number: TW100110909A
Authority: TW
Inventors: Paul Bleus; Thierry Joannes; Francois Milstein
Original assignee: Ce & T S A
Priority date: 2011-03-30
Filing date: 2011-03-30
Publication date: 2012-10-01
Also published as: TWI441440B

Abstract

Multilevel DC to AC power converter comprising three DC inputs (IN1, IN2, IN3) for receiving respectively three DC voltages (V1, V2, V3) wherein V1 > V2 > V3, one AC output (OUT1) for delivering an AC voltage (Va), a set of at least six switching means (T1, T2, T3, T4, T5, T6) arranged in a symmetric pyramidal fashion as shown in Fig.1, and switch control means for controlling an ON/OFF state of each of the six switching means. The switch control means is configured in such a way that the top two switching means (T5, T6) are switched ON and OFF in a complementary fashion and exclusively at a fundamental frequency (Fa) of the AC voltage to be delivered at the AC output (OUT1), whereas at least some of the other four switching means (T1, T2, T3, T4) are switched ON and OFF at higher frequencies. The top two switching means (T5, T6) are hence subject to lower switching losses, thereby increasing the overall efficiency of the converter.

Description

201240318 六、發明說明：【發明所屬之技術領域】 _本發明係相關於將多階層之直流電源轉換交流電源之反〇〇 100110909 流器（converters)，有時也稱為變頻器。更具體地來說，本發明係相關於一種反流器模組其包含以下之構件： -三個直流輸入（IN1、IN2、IN3)，用於分別接收第— 直流電壓（VI)、第二直流電壓（V2)和第三直流電壓 (V3)，其中 vi> V2> V3， -一個第一開關裝置（T1)、一個第二開關裝置（Τ2) 、一個第三開關裝置（Τ3)和一個第四開關裝置（Τ4) ，依序串聯在第一直流輸入（ΙΝ1)和第三直流輸入（ ΙΝ3)之間，而第二直流輸入（ΙΝ2)則係設置在第二開關裝置（Τ2)和第三開關裝置（Τ3)之串聯之間 -一個第五開關裝置（Τ5 )和一個第六開關裝置（Τ6 ) ，依序串聯起來，它們一面連接到第一開關裝置（T1 ) 和第二開關裝置（T2)的串聯之間，而另一面它們連接到第三開關裝置（T3)和第四開關裝置（T4)的串聯之間， -一個交流輸出（0UT1)連接到第五開關裝置（T5)和第六開關裝置（Τ6 )之間的串聯，提供一個與第二直流輸入（ΙΝ2)相關的交流電壓（va)， -:¾干開關控制裝置（switch control means)用來控制六個開關裝置（ΤΙ、T2、T3、T4、T5、T6)之中各別開關裝置之接通與斷開的狀態。 [先前技術3 表單編衆Α0101 第5頁/共28頁 10〇3361457-0 201240318 【發明内容】 [0002] 本發明之目的即在於提供一個反流器模組，其相較於已知的反流器模組，為具有更高的整體效率（higher overall eificiency)者。為此，根據本發明之反流器模組，其特徵為，其開關控制裝置是設計成： [0003] *當要在交流輸出（0UT1 )上，輸出一個正極交替時，T3 和T4和T6都是斷開的、T5是接通的，而T1和T2以互補的方式接通與斷開數次，以及 [0004] 其設計要能： *當要在交流輸出（0UT1)上，輸出一個負極交替時，T1 和T2和T5都將被斷開、T6則係被接通，而T3和T4以互補的方式令其接通與斷開數次。 [0005] 重點是，當這種反流器模組投入運作時，用於轉換直流輸入電壓成為交流輸出電壓，在交流輸出電壓的一個完整週期過程中，T5將只被接通與斷開一次，但是，在習知技術的反流器模組中，在同樣的週期過程中，T5將被接通與斷開多數次，（該次數通常為一個非常大數目）。對T 6來說，其情形也是一樣。 [0006] 換言之，本發明的反流器模組，係將T5和T6僅以一個基頻（一階頻率）來作接通與斷開之動作，而該基頻即係交流輸出之頻率，但是，基於習知技術的反流器模組中，T5和T6皆以較高（很高）的頻率來作接通與斷開之動作。 100110909 表單編號A0101 第6頁/共28頁 1003361457-0 201240318 [画]因此之故，在T5和在T6中的開關損耗（switching losses)，相較於習知的反流器而言，能得以降低。因此，相較於已知的反流器模組而言，本解決方案有助於提高反流器模組的整體效率。 [0008] 有利的是，根據本發明的反流器模組，其特徵為，該第一、第二、第三和第四開關裝置（T1、T2、T3、T4)係具有第一規格之半導體元件（semic〇nduct〇r devices having first specifications)，而第五開關裝置 ς} (Τ5)和第六開關裝置（Τ6)為具有第二規格的半導體元件（semiconductor devices having second specifications)，而該第二規格係不同於第一規格者〇 [0009] 一方面藉由對於T5和T6使用具有第一規格之半導體元件，而另一方面相對於ΤΙ、T2、T3和T4選用具有第二規格之半導體元件（意即，依該元件原廠資料表中之所示而選用具有不同規格之元件），吾人即可選擇合適之半導〇體元件，以最佳化該特定開關頻率（specific switching frequency)。 [0010] 更有利的是，根據本發明的反流器模組，其特徵為，第五開關裝置（T5)和第六開關裝置（T6)所表現的一個半導體本質傳導損耗（intrinsic conduction loss )，其為低於第一開關裝置（T1)、第二開關裝置（T2 )、第二開關裝置置（Τ3 )和第四開關裝置（Τ4 )各自之本質傳導損耗者。 100110909 表單編號Α0101 第7頁/共28頁 1003361457-0 201240318 [⑻⑴所謂『半導體本質傳導損耗』（intr insic conduc- tion loss) ’我們必須理解該本質傳導損耗，本質上係源自於半導體本身（意即其可自其原薇資料表中之規格數據中得出）。 [0012] 因此，T5和T6的本質傳導損耗可予以降低，從而，進一步，相較於已知的反流器模組，可提高該反流器模組的整體效率。【實施方式】 [0013] 圖1為一個整體流程圖，以示意圖方式顯示本發明的一個反流器模組。其包含至少六個開關裝置（T1至冗），其相互聯接為如圖中之所示者，三個直流輸入（IN1、IN2 、IN3)，用於分別接收三個直流電壓（V1、V2、V3) ，其關係為Π> V2〉V3，一個交流輸出（ουτί )用來提供一個交流電壓（Va),以及一個開關控制裝置 switch control means)，其經由開關控制線路（CT1 至CT6)傳送開關控制信號（ci至C6)用來控制六個開關裝置（T1至T6)中各別開關裝置之接通與斷開的狀態。 [0014] 該電路拓撲（circuit topology)在現有技術之中是眾所習知的，故在此不再進一步作詳細描述。 [0015] 在此關注之重點為開關控制裝置其控制開關裝置之接通與斷開狀態之方法。為此，圖2顯不出一個圖1中本發明的之反流器模組開關表（swi tching table )。此表顯示該六個開關裝置之中，各別開關裝置之接通與斷開的狀態係如何藉由開關控制裝置來設定，以決定¥1 1003361457-0 100110909 表單編號A0101 第8頁/共28頁 201240318 、V2或V3之中的那一個來輸出至交流輸出（0UT1)處。此外，該表的兩個中間列，進一步說明，該交流輸出是如何在VI改變成V2之間，或在V2改變成V3之間，來達成者。一個邏輯符號1對應一個開關裝置之接通的狀態，而一個邏輯符號0對應一個開關裝置之斷開的狀態。 [0016] 吾人可以容易地讀取該表，例如，為了將交流輸出提昇到VI階層，T5和T1都要是接通的，而T2、T3、T4和T6都要是斷開的。為了要將交流輸出從VI階層轉變至V2階層，T5要是保持接通的，T1要是斷開的，T2要是接通的，而T3、T4和T6都是要是保持斷開的。 [0017] 在交流輸出之中，正極和負極之交替變化，得以基於此表的開關規則（based on the switching rules of this table)而產生。 [0018] 進一步來說： [0019] *為了在交流輸出（0UT1 )之中，提供一個相對於第二直流輸入（IN2)而言之正極交替（a positive altern-ation) ，T5要是接通的，而T1和T2要以互補的方式接通與斷開數次（即，若Τ1是接通的，則Τ2是斷開的，反之亦然），而Τ3、Τ4和Τ6要是保持斷開的， [0020] 以及 *為了在交流輸出（0UT1 )之中，提供一個相對於第二直流輸入（ΙΝ2)而言之負極交替（a negative altern-ation)，則T6要是接通的，而T3和T4要以互補的方式接通與斷開數次（即，若Τ3是接通的，則Τ4是斷開的， 100110909 表單編號 Α0101 第 9 頁/共 28 頁 1003361457-0 201240318 反之亦然），而ΤΙ、T2和T5要是保持斷開的。 [0021] [0022] [0023] [0024] 因此，在交流電壓（Va)的一個完整週期（Ta = 1/Fa )期間，T5僅被接通與斷開一次，T6僅被接通與斷開一次’而ΤΙ、Τ2、Τ3和Τ4則各自需被接通與斷開數次。有利的是，V2 = (VI-V3)/2，以利交流電壓（Va)的正負交替得以平衡。圖3顯示在本發明之控制條件下，由開關控制裝置所產生的開關控制信號（CT1至CT6)之波形之示例，以及在圖j 反流器模組的交流輸出（OUT1)中，所產生之交流電壓 (Va)波形之實施例。在此圖中，Va係為相對於V2之電壓（標記為Va2)，因為交流輸出此時係為OUT1和IN2之間的電壓。此處之波形僅顯示了Va的第一個完整循環之週期（Ta = Ι/Fa)。隨後的循環週期可能相同或不同於此已示出的第一個完整循環週期，這取決於吾人是否要令Va為週期型式的（periodical)。有利的是，全部的循環週期都大致相同。正極交替（當Va高於V2)並不一定必須與負極交替（當 Va低於V2)持續相同的時間（Ta/ 2):吾人可根據所需的Va波形，而令其涵蓋一個較長（> Ta/2)或一個較短（< Ta/2 )的時間。吾人必須同時了解，在實際實施的條件下，可能藉由開關控制裝置，在開關控制信號之間，穿插一些簡短的等待時間（some brief dead time) ’以利一對互補組 100110909 表單編號A0101 第10頁/共28頁 1003361457-0 201240318 合（T1/T2、T3/T4、T5/T6)的兩個開關裝置，在這個轉換期間的少量時間之中，可以都是接通的或都是斷開的，而這樣做也是沒有脫離本發明的範圍的。 [0025] 在此例中，在正極交替的期間内，T1被接通與斷開三次，而在負極交替的期間，T3被接通與斷開三次。 [0026] 有利的是，該開關控制裝置，開關T1和/或T3的接通與斷開之頻率，可令其遠高於在交流輸出之Va的基本頻率（ Fa二Ι/Ta)，因為這樣可以允許在交流輸出之中使用較小的過濾裝置（例如圖5中使用較小的自感應線圈L1 ) 〇 [0027] 在交流輸出之中，基頻（Fa)可能通常是一個在1 Hz和1 KHz之間的數值，而T1和/或T3則正常要被以1 KHz和 500 KHz之間的頻率來接通與斷開。例如，以提供一個基本的交流輸出頻率（Fa ) 50Hz的情況下，T1和/或T3可以以15 KHz的頻率來被接通與斷開。 [0028] 此外，T1和/或T3可依據習知的脈波寬度調變（PWM， Pulse Width Modulation)方案或任何其它適當的方案，來被接通與斷開。 [0029] 有利的是，該開關裝置為可主動控制之半導體元件（ actively controllable semiconductor devices )，如晶體管型元件（transistor-type devices)或晶閘管開關型元件（thyristor-type devices)。 [0030] 有利的是，選擇用於ΤΙ、T2、T3和T4的那些半導體元件，不同於選擇用於T5和T6的那些半導體元件。例如，吾 100110909 表單編號A0101 第11頁/共28頁 1003361457-0 201240318 人可以選擇使用下列半導體元件之組合： ΤΙ、T2、T3、T4 : 一個第一類型之絕緣閘雙極晶體管（ Insulated Gate Bipolar Transistors,IGBT, of- first type)，以及 T5、T6 : —個不同於第一類型（根據其數據表，data sheet)之第二類型絕緣閘雙極晶體管（IG_ BT,Insulated Gate Bipolar Transistors of a second type); 或 ΤΙ、T2、T3、T4 : 一個第一類型之絕緣閘雙極晶體管（ IGBT)，以及 T5、T6 :集成門極換流晶閘管（Integrated Gate201240318 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a converter for converting a multi-level DC power source to an AC power source, 100110909, sometimes referred to as a frequency converter. More specifically, the present invention relates to a inverter module comprising the following components: - three DC inputs (IN1, IN2, IN3) for respectively receiving a first DC voltage (VI), a second a direct current voltage (V2) and a third direct current voltage (V3), wherein vi > V2 > V3, - a first switching device (T1), a second switching device (Τ2), a third switching device (Τ3), and a The fourth switching device (Τ4) is sequentially connected in series between the first DC input (ΙΝ1) and the third DC input (ΙΝ3), and the second DC input (ΙΝ2) is disposed in the second switching device (Τ2) Between the series connection of the third switching device (Τ3) - a fifth switching device (Τ5) and a sixth switching device (Τ6), which are connected in series, one side connected to the first switching device (T1) and the second The switching devices (T2) are connected in series, while the other side is connected between the series connection of the third switching device (T3) and the fourth switching device (T4), - an alternating current output (OUT1) is connected to the fifth switching device ( a series connection between T5) and the sixth switching device (Τ6), providing a The second DC input (ΙΝ2) related AC voltage (va), -: 3⁄4 dry switch control means are used to control each of the six switching devices (ΤΙ, T2, T3, T4, T5, T6) The state in which the switching device is turned on and off. [Prior Art 3 Form Editors 101 0101 Page 5 / Total 28 Pages 10 〇 3361457-0 201240318 SUMMARY OF THE INVENTION [0002] It is an object of the present invention to provide a inverter module that is comparable to known counters. The flow module is for higher overall eificiency. To this end, the inverter module according to the invention is characterized in that the switching control device is designed to: [0003] * When an alternating current output (0UT1) is output, T3 and T4 and T6 are alternated. Both are open, T5 is on, and T1 and T2 are turned on and off several times in a complementary manner, and [0004] are designed to: *When on the AC output (0UT1), output one When the negative poles alternate, T1 and T2 and T5 will both be turned off, T6 will be turned on, and T3 and T4 will be turned on and off several times in a complementary manner. [0005] The point is that when this inverter module is put into operation, it is used to convert the DC input voltage into an AC output voltage. During a complete cycle of the AC output voltage, T5 will only be turned on and off once. However, in the conventional art inverter module, T5 will be turned on and off most times during the same cycle (this number is usually a very large number). The same is true for T6. [0006] In other words, the inverter module of the present invention performs the operations of turning on and off with only one fundamental frequency (first-order frequency) of T5 and T6, and the fundamental frequency is the frequency of the AC output. However, in the conventional inverter module, both T5 and T6 are turned on and off at a relatively high (very high) frequency. 100110909 Form No. A0101 Page 6 of 28 1003361457-0 201240318 [Drawing] Therefore, the switching losses in T5 and T6 can be compared with the conventional inverters. reduce. Therefore, this solution helps to improve the overall efficiency of the inverter module compared to known inverter modules. [0008] Advantageously, the inverter module according to the present invention is characterized in that the first, second, third and fourth switching devices (T1, T2, T3, T4) have the first specification a semiconductor device (semiconductor device having first specifications), and a fifth switching device Τ} (Τ5) and a sixth switching device (Τ6) are semiconductor devices having second specifications, and the semiconductor device The second specification is different from the first specification. [0009] On the one hand, by using the semiconductor component having the first specification for T5 and T6, and on the other hand, the second specification is selected with respect to ΤΙ, T2, T3 and T4. For semiconductor components (ie, components with different specifications as shown in the original manufacturer's data sheet), we can select a suitable semiconductor component to optimize the specific switching frequency. ). [0010] More advantageously, the inverter module according to the present invention is characterized by a semiconductor intrinsic conduction loss exhibited by the fifth switching device (T5) and the sixth switching device (T6). It is lower than the intrinsic conduction loss of each of the first switching device (T1), the second switching device (T2), the second switching device (Τ3), and the fourth switching device (Τ4). 100110909 Form No. 1010101 Page 7 of 28 1003361457-0 201240318 [(8)(1) The so-called "intr insic conducing loss" 'We must understand the essential conduction loss, which is essentially derived from the semiconductor itself ( This means that it can be derived from the specification data in its original data sheet. [0012] Therefore, the intrinsic conduction loss of T5 and T6 can be reduced, and further, the overall efficiency of the inverter module can be improved compared to known inverter modules. [Embodiment] [0013] FIG. 1 is a general flow chart showing a reverberator module of the present invention in a schematic manner. It comprises at least six switching devices (T1 to redundant) interconnected as shown in the figure, three DC inputs (IN1, IN2, IN3) for receiving three DC voltages (V1, V2, respectively) V3), the relationship is Π> V2>V3, an AC output (ουτί) is used to provide an AC voltage (Va), and a switch control means is transmitted via the switch control lines (CT1 to CT6) The control signals (ci to C6) are used to control the on and off states of the respective switching devices of the six switching devices (T1 to T6). [0014] The circuit topology is well known in the prior art and will not be described in further detail herein. [0015] The focus here is on the method by which the switching control device controls the on and off states of the switching device. To this end, Figure 2 shows a swi tching table of the present invention of Figure 1 . This table shows how the state of the respective switching devices is turned on and off, and the state of the respective switching devices is set by the switch control device to determine ¥1 1003361457-0 100110909 Form No. A0101 Page 8 of 28 The one of pages 201240318, V2 or V3 is output to the AC output (0UT1). In addition, the two middle columns of the table further illustrate how the AC output is achieved between a VI change to V2 or a change between V2 and V3. A logical symbol 1 corresponds to the on state of a switching device, and a logical symbol 0 corresponds to the disconnected state of a switching device. [0016] The table can be easily read by us, for example, in order to raise the AC output to the VI level, both T5 and T1 are turned on, and T2, T3, T4, and T6 are all turned off. In order to change the AC output from the VI level to the V2 level, if T5 remains on, T1 should be turned off, T2 should be turned on, and T3, T4 and T6 should remain disconnected. [0017] Among the AC outputs, the alternating changes of the positive and negative electrodes are generated based on the switching rules of this table. [0018] Further: [0019] * In order to provide a positive altern-ation with respect to the second DC input (IN2) in the AC output (0UT1), T5 is to be turned on. And T1 and T2 are turned on and off several times in a complementary manner (ie, if Τ1 is on, then Τ2 is off, and vice versa), while Τ3, Τ4, and Τ6 remain disconnected. [0020] and * In order to provide a negative altern-ation with respect to the second DC input (ΙΝ2) among the AC output (0UT1), T6 is turned on, and T3 and T4 is turned on and off several times in a complementary manner (ie, if Τ3 is on, then Τ4 is off, 100110909 form number Α0101, page 9/28 pages 1003361457-0 201240318 and vice versa), And ΤΙ, T2 and T5 remain disconnected. [0024] Therefore, during a complete cycle (Ta = 1/Fa) of the alternating voltage (Va), T5 is only turned on and off once, and T6 is only turned on and off. Open once and 'ΤΙ, Τ2, Τ3, and Τ4 each need to be turned on and off several times. Advantageously, V2 = (VI-V3)/2 to balance the positive and negative alternating voltages (Va). Figure 3 shows an example of the waveforms of the switch control signals (CT1 to CT6) generated by the switch control device under the control conditions of the present invention, and generated in the AC output (OUT1) of the inverter module of Figure j. An embodiment of an alternating voltage (Va) waveform. In this figure, Va is the voltage relative to V2 (labeled Va2) because the AC output is now the voltage between OUT1 and IN2. The waveform here shows only the period of the first full cycle of Va (Ta = Ι/Fa). Subsequent cycles may be the same or different from the first full cycle shown here, depending on whether we want Va to be periodic. Advantageously, all of the cycle periods are approximately the same. Alternating positive poles (when Va is higher than V2) do not necessarily have to alternate with the negative pole (when Va is lower than V2) for the same time (Ta/2): we can cover a longer one depending on the desired Va waveform ( > Ta/2) or a shorter (< Ta/2) time. We must also understand that under the actual implementation conditions, some short dead time may be interspersed between the switch control signals by the switch control device to facilitate a pair of complementary groups 100110909 Form No. A0101 10 pages/total 28 pages 1003361457-0 201240318 Two switching devices (T1/T2, T3/T4, T5/T6) can be switched on or off during a small amount of time during this transition. It is also possible to do so without departing from the scope of the invention. [0025] In this example, T1 is turned on and off three times during the period in which the positive electrodes are alternated, and T3 is turned on and off three times during the period in which the negative electrodes are alternated. [0026] Advantageously, the switching control device, the switching diodes T1 and / or T3 can be turned on and off at a frequency which is much higher than the fundamental frequency of the Va at the AC output (F2 / Ta) because This allows a smaller filter to be used in the AC output (for example, using a smaller self-inducting coil L1 in Figure 5). [0027] In the AC output, the fundamental frequency (Fa) may usually be one at 1 Hz. And the value between 1 KHz, and T1 and / or T3 are normally turned on and off at a frequency between 1 KHz and 500 KHz. For example, in the case of providing a basic AC output frequency (Fa) of 50 Hz, T1 and/or T3 can be turned on and off at a frequency of 15 KHz. In addition, T1 and/or T3 may be turned "on" and "off" in accordance with a conventional Pulse Width Modulation (PWM) scheme or any other suitable scheme. [0029] Advantageously, the switching device is a actively controlledl semiconductor device, such as a transistor-type device or a thyristor-type device. [0030] Advantageously, those semiconductor components for ΤΙ, T2, T3 and T4 are selected, unlike those selected for T5 and T6. For example, my 100110909 Form No. A0101 Page 11 / Total 28 Page 1003361457-0 201240318 One can choose to use the following combination of semiconductor components: ΤΙ, T2, T3, T4: A first type of insulated gate bipolar transistor (Insulated Gate Bipolar) Transistors, IGBT, of-first type), and T5, T6: a second type of insulated gate bipolar transistor (IG_BT, Insulated Gate Bipolar Transistors of a different from the first type (according to its data sheet) Second type); or ΤΙ, T2, T3, T4: a first type of insulated gate bipolar transistor (IGBT), and T5, T6: integrated gate commutated thyristor (Integrated Gate)

Commutated Thyristors,IGCT) > 或 ΤΙ、T2 ' T3、T4 :金屬氧化層場效晶體管（Metal oxide Sem. Field Effect Transistor, MOSFET) ，以及 T5'T6.集成門極換流晶閘管（integrated Gate Commutated Thyristors, IGCT) > 或 ΤΙ、T2、T3、T4 .集成門極換流晶閘管（integrated Gate Commutated Thyristors, IGCT)，以及 T5、T6 :閘控可關斷晶閘管（Gate Turn ο"Commutated Thyristors, IGCT) > or ΤΙ, T2 'T3, T4: Metal Oxide Field Effect Transistor (MOSFET), and T5'T6. Integrated Gate Commutated Thyristors , IGCT) > or ΤΙ, T2, T3, T4. Integrated Gate Commutated Thyristors (IGCT), and T5, T6: Gate-controlled turn-off thyristors (Gate Turn ο"

Thyristor，GTO)。 [0031]圖4示反流器模組的一個實施例，其使用絕緣閘雙極晶體 100110909 表單編號A0101 第12頁/共28頁 1003361457-0 201240318 [0032] Ο [0033] [0034]Thyristor, GTO). [0031] FIG. 4 shows an embodiment of a inverter module using an insulated gate bipolar crystal 100110909 Form No. A0101 Page 12 of 28 1003361457-0 201240318 [0033] [0034]

管（IGBT) ’其分別提供給每個IGBT (Τ]^Τ6)依反向平行（anti-parallel)的方式安裝一個“耵之續流二極管（freewheel diode) (D1 至D6)。有利的是，用於T5和T6的半導體元件，具有相較於用於 ΤΙ、T2、T3和T4的半導體元件而言，更低的傳導損耗。正如技術人員眾所周知的，半導體元件的傳導損耗，主要取決於其正向壓降（forward voltage drop)及其通態電阻（on-state resistance)，兩者都會存在於伴隨該元件的數據表（data sheet)中。至於半導體元件之計算或測量傳導損耗的一些方法，也是眾所周知的〇更為有利的情況為，ΤΙ、T2、T3和T4是晶體管型元件(transistor-type devices)，例如是IGBT，而其中T5和T6是晶閘管開關型元件（thyr i stor-type devices )，如IGCT。圖5顯示圖4中所示意之反流器模組的一個應用實施例。在此例之中，兩個電池、B2)和兩個平行的緩衝電容器（C1、C2)，係被連接到反流器模組的直流輸入上 ’如圖中之所示者’以供給三個直流電壓（V1、V2、V3 )。一個低通遽頻器（A i〇w-pass filter: LI、C3) 係被連接至反流器模组的交流輸出（0UT1 )上，用於過濾Va的高階頻率，其根據眾所周知的過濾方法。為了清楚起見，開關控制裝置（the switch control means )並不顯示在這個圖中。 100110909 表單編號Α0101 第13頁/共28頁 1003361457-0 201240318 刚—個交流負載（Z)係被連接於低«、頻If (GUT2)輸出與第二個直流輸入（IN2)之間。因此，當該系統投入運作時，電池的直流電壓將被轉換成為一個，例如說，大致上’相對於V2 (=%)的正弦交流電壓（v )。The tube (IGBT) 'is supplied to each IGBT (Τ)^6) in an anti-parallel manner to install a "freewheel diode" (D1 to D6). Semiconductor components for T5 and T6 have lower conduction losses than semiconductor components for ΤΙ, T2, T3 and T4. As is well known to the skilled person, the conduction loss of semiconductor components depends mainly on Its forward voltage drop and its on-state resistance, both of which are present in the data sheet accompanying the component. As for the calculation or measurement of the conduction loss of the semiconductor component The method, which is also well known, is more advantageous in that ΤΙ, T2, T3 and T4 are transistor-type devices, such as IGBTs, and T5 and T6 are thyristor switching elements (thyr i stor- Type devices ), such as IGCT. Figure 5 shows an application embodiment of the inverter module shown in Figure 4. In this example, two batteries, B2) and two parallel snubber capacitors (C1, C2) ),system Connect to the DC input of the inverter module 'as shown in the figure' to supply three DC voltages (V1, V2, V3). A low-pass frequency converter (A i〇w-pass filter: LI , C3) is connected to the AC output (0UT1) of the inverter module for filtering the high-order frequency of Va according to the well-known filtering method. For the sake of clarity, the switch control means Not shown in this figure. 100110909 Form number Α0101 Page 13 of 28 1003361457-0 201240318 Just-AC load (Z) is connected to the low «, frequency If (GUT2) output and the second DC input ( Between IN2) Therefore, when the system is put into operation, the DC voltage of the battery will be converted into one, for example, roughly 'sinusoidal AC voltage (v) relative to V2 (=%).

A C 圖6以示意方式顯示依據本發明的一個五階層反流器。為了清楚起見，開關控制裝置和開關控制線路（the switch control means and the switch control 1 ines ) ’皆不顯示在此圖之中，但我們必須明白，其類似於圖1所顯示的部分，即開關控制線路Ci，控制Ti的接通與斷開之開關，而間關控制信號CTi是藉由開關控制裝置傳送至開關控制線路Ci之信號。我們也應注意，圖6顯示的虛線部分，不代表電氣連接，而是對稱的拓撲軸線 (topological axes of symmetry)。 [0036] 這種五階層反流器至少包含兩個三階層反流器模組（ M0D-A1、M0D-A2 )，兩個模組各自為一個基本的三階層反流器模組（M0D-A1)，其設計與控制皆如上文之描述。第一反流器模組之第三直流輸入（Μ〇!)_Α1)，連接至第二反流器模組（M0D-A2)之第一直流輸入，使反流器呈現五個直流輸入，用於分別接收五個直流電壓（V1至 V5)，其關係為VI >V2 >V3 >V4 >V5 [0037] » 最有利的是 ’ V3 = (Vl+V5)/2、V2 = (Vl+V3)/2，以及 V4=(V3+V5)/2 。 [0038] 此外，兩個附加的開關裝置（T13、T14)，串聯在第一反流器模組（M0D-A1)的第一交流輸出（out- A1)與 100110909 表單編號A0101 第14頁/共28頁 1003361457-0 201240318 第二反流器模組（M0D-A2)的第二交流輸出（OUT- A1 )之間，而中點在T13和T14之間，為該反流器的交流輸出（0UT1)。 [0039] 為了在交流輸出（0UT1)之中，輸出一個相對於第三直流輸入（即相對於V3)的正極交替，T1 3要是被接通的，而T14如同Til、T12、T5、T6、T7和T8是要被斷開的，而T9、T10、ΤΙ、T2、T3和T4則係根據圖2和圖3之設計而被接通與斷開，來傳送VI或V2或V3至交流輸出。 [0040] 為了在交流輸出（0UT1 )之中，輸出一個相對第三直流輸入（即相對V3)的負極交替，T14要是被接通的，而 T13如同T9，T10，T1，T2，T3和T4是要被斷開的，而 Tll，Τ12, Τ5, Τ6, Τ7和Τ8則係根據圖2和圖3之設計而被接通與斷開，來傳送V3或V4或V5至交流輸出。 [0041] 圖7顯示根據本發明之控制之開關控制信號（CT1至CT14 )的各種示例波形，以及在圖6五階層反流器的交流輸出 (0UT1)之中所產生出之交流電壓（Va)的結果波形。對於技術人員來說，現在即可以清楚得知，如何建立和控制2n+l階層（2的η次方加1，其中n = l，2, 3, 4. . ·)的多階層反流器。因此，本發明為相關於這些任何及全部之各類多階層反流器者。 [0042] 一個如同上文描述的實施例的九階層反流器（η = 3)，其至少包含兩個五階層反流器（M0D-B1、M0D-B2)，係示意圖於圖8之中者。 [0043] 圖9以示意方式顯示依據本發明的一個三階層之三相反流 100110909 表單編號A0101 第15頁/共28頁 1003361457-0 201240318 器。其至少包含三個反流器模組（MOD-A1、MOD-A2、 M0D-A3) ’ 而構成三個相腳（constituting the three phase legs)，每個模組皆為上文描述的模組 (M0D-A)之一。每個模組的第一直流輸入（V11、V12 、V13)和第三直流輸入（V31、V32、V33)，皆被連接至一個直流導線（a DC rail, V+、V-)，如該圖中所示者’而每個模組的第二直流輸入（V21、V22、V23 )，則係被連接至一個電容器組（C、C)的中點，亦如該圖中之所示者。其所提供的開關控制信號（未顯示），皆係互相有相移 120度（phase-shifted by 120 degrees) 者’以控制三個反流器模組之中之每一個（即每個相腳，i.e. for each phase leg)，因而三相交流電壓將得以傳送至輸出（Val、Va2、Va3)中，而以電容器組中點之電壓（Vo)為中性點（neutral p〇int) ο [0044] [0045] 本發明已藉數個具體實施例而得以描述，唯該些具體實施例其為本發明的說明例，而絕非將本發明限制於此具體實施例之範圍内。更一般而言，熟習該項技術者將會了解，本發明並不受限於上文所特別示出和/或描述出的各項内容。本發明實包括每項及所有各項俱有新穎性之特徵與特點，以及該每項及所有各項倶有新穎性的特徵與特點之各種組合。申請專利範圍各項中所使用之元件符號，並非限制各該元件之保護範圍者。動闲『包含』、『包括』、『構成』的使用，或任何其 100110909 表單編號Α0101 第16頁/共28頁 1003361457- 201240318 [0046] [0047]A C Figure 6 shows in a schematic manner a five-level inverter in accordance with the present invention. For the sake of clarity, the switch control means and the switch control 1 ines ' are not shown in this figure, but we must understand that it is similar to the part shown in Figure 1, ie The switch control circuit Ci controls the on and off switches of Ti, and the off control signal CTi is a signal transmitted to the switch control line Ci by the switch control means. It should also be noted that the dotted line shown in Figure 6 does not represent an electrical connection but a topological axes of symmetry. [0036] The five-level inverter includes at least two three-level inverter modules (M0D-A1, M0D-A2), and each of the two modules is a basic three-level inverter module (M0D- A1), its design and control are as described above. The third DC input of the first inverter module (Μ〇!)_Α1) is connected to the first DC input of the second inverter module (M0D-A2), so that the inverter presents five DC inputs. For receiving five DC voltages (V1 to V5) respectively, the relationship is VI >V2 >V3 >V4 >V5 [0037] » The most advantageous is 'V3 = (Vl+V5)/2, V2 = (Vl+V3)/2, and V4=(V3+V5)/2. [0038] In addition, two additional switching devices (T13, T14) are connected in series with the first AC output (out-A1) of the first inverter module (M0D-A1) and 100110909 Form No. A0101 page 14/ 28 pages 1003361457-0 201240318 The second inverter output (M0D-A2) is between the second AC output (OUT-A1), and the midpoint is between T13 and T14, which is the AC output of the inverter. (0UT1). [0039] In order to output an alternating current with respect to the third direct current input (ie, relative to V3) among the alternating current outputs (OUT1), T13 is turned on, and T14 is like Til, T12, T5, T6, T7 and T8 are to be disconnected, while T9, T10, ΤΙ, T2, T3 and T4 are switched on and off according to the design of Figures 2 and 3 to transfer VI or V2 or V3 to AC output. . [0040] In order to output an anode alternating with respect to the third DC input (ie, relative to V3) among the AC outputs (0UT1), T14 is turned on, and T13 is like T9, T10, T1, T2, T3, and T4. It is to be disconnected, and Tll, Τ12, Τ5, Τ6, Τ7 and Τ8 are switched on and off according to the design of Figures 2 and 3 to deliver V3 or V4 or V5 to the AC output. 7 shows various example waveforms of the control switching signals (CT1 to CT14) controlled according to the present invention, and the AC voltage generated in the AC output (OUT1) of the five-level inverter of FIG. 6 (Va). The resulting waveform. For the technician, it is now clear how to establish and control the multi-level inverter of the 2n+1 class (2 η power plus 1, where n = l, 2, 3, 4. . . ) . Accordingly, the present invention is directed to any and all of these various types of multi-level inverters. [0042] A nine-level inverter (n=3) as in the embodiment described above, comprising at least two five-level inverters (M0D-B1, M0D-B2), which are schematically illustrated in FIG. By. [0043] FIG. 9 shows in schematic form a three-level three-phase reverse flow according to the present invention. 100110909 Form No. A0101 Page 15 of 28 1003361457-0 201240318. It consists of at least three inverter modules (MOD-A1, MOD-A2, M0D-A3) and constitutes the three phase legs, each of which is the module described above. One of (M0D-A). The first DC input (V11, V12, V13) and the third DC input (V31, V32, V33) of each module are connected to a DC conductor (a DC rail, V+, V-), such as The second DC input (V21, V22, V23) of each module is connected to the midpoint of a capacitor bank (C, C), as shown in the figure. . The switch control signals (not shown) provided by them are phase-shifted by 120 degrees to control each of the three inverter modules (ie, each phase leg). , ie for each phase leg), so that the three-phase AC voltage will be transmitted to the output (Val, Va2, Va3), and the voltage (Vo) at the midpoint of the capacitor bank is neutral p〇int ο [ The present invention has been described with reference to a number of specific embodiments, which are not intended to limit the scope of the invention. More generally, those skilled in the art will appreciate that the invention is not limited to the particulars shown and/or described herein. The present invention includes various features and characteristics of each and every item, as well as various combinations of features and characteristics of each and every novel. The symbol of a component used in the scope of the patent application is not intended to limit the scope of protection of each component. Use of "including", "including", "composition", or any of its 100110909 Form No. 1010101 Page 16 of 28 1003361457- 201240318 [0047] [0047]

[0048] 100110909 它的詞語變體，如同其各自的連接詞受詞，皆不排除該說明以外的其它元件之存在。冠詞『一』、『一個』，或『該』的使用，加在一個元件之前，不排除有複數個該類元件存在之情況。總結而言，本發明同時也可說明如下：一種將多階層直流電源轉換為交流電源的反流器，至少包含三個直流輸入（INI、IN2、IN3)，用於分別接收三個直流電壓（VI、V2、V3)，其中V1>V2 >V3 ; —個交流輸出（OUT1)，用於提供一個交流電壓（Va)，將一組為至少六個的開關裝置（ΤΙ、T2、T3、T4、T5、T6 )，安排於一個對稱的金字塔樣式之安排之中，如圖1所示；以及開關的控制裝置，用於控制六個開關裝置之中每個接通與斷開的狀態。此開關控制裝置是配置成為，上端的兩個開關裝置（T5、T6)是於交流電壓的一個基頻（Fa)上，以互補的方式被接通與斷開，傳送一個該基頻之交流電壓至交流輸出處（OUT1 )，而其它四個開關裝置（ΤΙ、T2、T3、T4)之中至少有些是被控制在更高的頻率上作接通與斷開者。因此，前面兩個開關裝置 (T5 ' T6 )，受到較低的開關損耗（sub ject to lower switching losse)，從而提高反流器的整體效率ο 【圖式簡單說明】本發明在這些方面與其它進一步方面之細節，將藉由實施例以及參考所附之圖來更詳細加以解釋，其中：圖1為根據本發明的一個反流器模組之示意圖；表單編號Α0101 第17頁/共28頁 1003361457-0 [0049] 201240318 [0050] 圖2顯示圖1中反流器模組之開關表（Sw i t ch i ng t ab 1 e [0051] [0052] [0053] [0054] [0055] [0056] [0057] [0058] [0059] 圖3顯示圖1所示意反流器模組之典型之控制信號和輸出電壓之波形；圖4顯示圖1所示意的反流器模組之一個實施例；圖5顯示圖4所示意之反流器模組的一個應用之實施例；圖6以示意方式顯示依據本發明的一個五階層反流器；圖7顯示圖6五階層反流器之典型控制信號和輸出電壓波形；圖8以示意方式顯示根據本發明的一個九階層反流器；圖9以示意方式顯示依據本發明的一個三階層之三相反流益，這些圖表並非係按實際比例繪製而成者。一般來說，在各圖之中，相同構件皆由相同的元件符號所表示。【主要元件符號說明】 B1 電池1 B2 電池2 C1 開關控制信號1，缓衝電容器1 C2 開關控制信號2，緩衝電容器2 C3 開關控制信號3，電容器3 C4 開關控制信號4 C5 開關控制信號5 C6 開關控制信號6 表單編號A0101 第18頁/共28頁 1003361457-0 100110909 201240318[0048] 100110909 Its word variants, like their respective conjunctions, are not excluded from the existence of other elements than the description. The use of the articles "a", "an", or "the" is added before an element, and does not exclude the existence of a plurality of such elements. In summary, the present invention can also be explained as follows: A inverter for converting a multi-level DC power supply into an AC power supply, comprising at least three DC inputs (INI, IN2, IN3) for respectively receiving three DC voltages ( VI, V2, V3), where V1 > V2 >V3; an AC output (OUT1) for providing an AC voltage (Va), a group of at least six switching devices (ΤΙ, T2, T3, T4, T5, T6) are arranged in a symmetrical pyramid pattern arrangement as shown in Fig. 1; and a switch control device for controlling the state of each of the six switching devices being turned on and off. The switch control device is configured such that the upper two switching devices (T5, T6) are turned on and off in a complementary manner on a fundamental frequency (Fa) of the alternating voltage to transmit an alternating current of the fundamental frequency. The voltage is at the AC output (OUT1), while at least some of the other four switching devices (ΤΙ, T2, T3, T4) are controlled to turn on and off at higher frequencies. Therefore, the first two switching devices (T5 'T6) are subject to lower switching losses, thereby improving the overall efficiency of the inverter. [Simplified illustration] The present invention is in these respects and other aspects. The details of further aspects will be explained in more detail by way of embodiments and with reference to the accompanying drawings in which: FIG. 1 is a schematic diagram of a inverter module according to the present invention; Form No. 1010101 Page 17 of 28 1003361457-0 [0049] [0050] FIG. 2 shows a switch table of the inverter module of FIG. 1 (FIG. 2) [0054] [0054] [0055] [0059] FIG. 3 shows a typical control signal and output voltage waveform of the inverter module shown in FIG. 1. FIG. 4 shows an implementation of the inverter module illustrated in FIG. Figure 5 shows an embodiment of an application of the inverter module shown in Figure 4; Figure 6 shows a five-level inverter in accordance with the present invention in a schematic manner; Figure 7 shows a five-level inverter of Figure 6. Typical control signal and output voltage waveform; Figure 8 is shown in schematic form according to this A nine-level inverter of the present invention; Figure 9 shows in schematic form a three-level three-phase flow according to the present invention, and these charts are not drawn to actual scales. Generally, among the figures, The same components are denoted by the same component symbols. [Main component symbol description] B1 Battery 1 B2 Battery 2 C1 Switch control signal 1, snubber capacitor 1 C2 Switch control signal 2, snubber capacitor 2 C3 Switch control signal 3, capacitor 3 C4 Switch Control Signal 4 C5 Switch Control Signal 5 C6 Switch Control Signal 6 Form No. A0101 Page 18 of 28 1003361457-0 100110909 201240318

CT1 開關控制線路1 CT2 開關控制線路2 CT3 開關控制線路3 CT4 開關控制線路4 CT5 開關控制線路5 CT6 開關控制線路6 D1 續流二極管1 D2 續流二極管2 D3 續流二極管3 D4 續流二極管4 D5 續流二極管5 D6 續流二極管6 Fa 交流電頻率 INI 直流輸入1 IN2 直流輸入2 IN3 直流輸入3 LI 自感應線圈1 LI, C3 低通濾頻器 MOD-A 基本型三階層反流器模組 MOD-A1 三階層反流器模組1 M0D-A2 三階層反流器模組2 MOD-A3 三階層反流器模組3 MOD-B1 五階層反流器模組1 MOD-B2 五階層反流器模組2 OUT1 交流輸出1 OUTA1 相對於V1之交流輸出電壓表單編號A0101 第19頁/共28頁 1003361457-0 100110909 201240318 OUTA2 相對於V2之交流輸出電壓 t 時間 T1 開關裝置1 T10 開關裝置1 0 T11 開關裝置11 T12 開關裝置1 2 T13 開關裝置1 3 T14 開關裝置14 T15 開關裝置1 5 T16 開關裝置1 6 T2 開關裝置2 T3 開關裝置3 T4 開關裝置4 T5 開關裝置5 T6 開關裝置6 T7 開關裝置7 T8 開關裝置8 T9 開關裝置9 Ta 交流電週期 V- 直流輸入負極導線 V + 直流輸入正極導線 VI 直流電壓1 Vll 第一直流輸入1 V12 第一直流輸入2 V13 第一直流輸入3 V2 直流電壓2 表單編號AOlOi 第20頁/共28頁 1003361457-0 100110909 201240318 V21 第二直流輸入1 V22 第二直流輸入2 V23 第二直流輸入3 V3 直流電壓3 V31 第三直流輸入1 V32 第三直流輸入2 V33 第三直流輸入3 V4 直流電壓4 V5 直流電壓5 VA 輸出交流電壓 Val 輸出交流電壓第1相 Va2 輸出交流電壓第2相 Va3 輸出交流電壓第3相 VAC 交流輸出 VN 交流輸出中線 z 交流負載 100110909 表單編號A0101 第21頁/共28頁 1003361457-0CT1 Switch Control Line 1 CT2 Switch Control Line 2 CT3 Switch Control Line 3 CT4 Switch Control Line 4 CT5 Switch Control Line 5 CT6 Switch Control Line 6 D1 Freewheeling Diode 1 D2 Freewheeling Diode 2 D3 Freewheeling Diode 3 D4 Freewheeling Diode 4 D5 Freewheeling diode 5 D6 Freewheeling diode 6 Fa AC frequency INI DC input 1 IN2 DC input 2 IN3 DC input 3 LI Self-inductive coil 1 LI, C3 Low-pass filter MOD-A Basic three-level inverter module MOD-A1 three-level inverter module 1 M0D-A2 three-level inverter module 2 MOD-A3 three-level inverter module 3 MOD-B1 five-level inverter module 1 MOD-B2 five-level anti- Flow Module 2 OUT1 AC Output 1 OUTA1 AC Output Voltage Relative to V1 Form No. A0101 Page 19 / Total 28 Page 1003361457-0 100110909 201240318 OUTA2 AC Output Voltage vs. V2 Time T1 Switching Device 1 T10 Switching Device 1 0 T11 Switching device 11 T12 Switching device 1 2 T13 Switching device 1 3 T14 Switching device 14 T15 Switching device 1 5 T16 Switching device 1 6 T2 Switching device 2 T3 Switching device 3 T4 Switching 4 T5 Switchgear 5 T6 Switchgear 6 T7 Switching Device 7 T8 Switching Device 8 T9 Switching Device 9 Ta AC Cycle V- DC Input Negative Conductor V + DC Input Positive Conductor VI DC Voltage 1 Vll First DC Input 1 V12 First DC input 2 V13 First DC input 3 V2 DC voltage 2 Form number AOlOi Page 20 of 28 1003361457-0 100110909 201240318 V21 Second DC input 1 V22 Second DC input 2 V23 Second DC input 3 V3 DC Voltage 3 V31 Third DC input 1 V32 Third DC input 2 V33 Third DC input 3 V4 DC voltage 4 V5 DC voltage 5 VA Output AC voltage Val Output AC voltage Phase 1 Va2 Output AC voltage Phase 2 Va3 Output AC voltage Phase 3 VAC AC Output VN AC Output Neutral z AC Load 100110909 Form No. A0101 Page 21 of 28 1003361457-0

Claims

201240318 VII. Patent application scope: 1. A inverter module includes at least the following components for respectively receiving the first three DC inputs (INI, ΙΝ2, ΙΝ3), a DC voltage (VI), and a second DC voltage ( V2) and a third direct current - a first switching device (a third switching device (voltage (V3), where Vl >V2> V3, -T1), a second switching device (T2), T3) and a The fourth switching device (T4) is sequentially connected in series between the first DC input (IΝ1) and the third DC input (I ν 3 ), and the second DC input (ΙΝ2) is disposed in the second switching device ( Τ 2) and the series connection of the third switching device (Τ3), a fifth switching device (Τ5) and a // switching device (Τ6) are connected in series, one side of which is connected to the first switching device (Τ1) ) between the series connection of the second switching device (Τ2) and the other side connected between the series connection of the third switching device (Τ3) and the fourth switching device (Τ4), the AC output (0UT1) is connected to Between the fifth switching device (Τ5) and the sixth switching device (Τ6)联' provides an AC voltage (Va) associated with the second DC input (IΝ 2 ), and a number of switch control means are used to control the six switching devices (ΤΙ, T2, T3, T4, T5, a state in which the respective switching devices are turned on and off in T6), characterized in that the switching control device is configured to: - output a positive alternation in the alternating current output (0UT1), T3 and T4 and T6 are both controlled to be open, Τ5 is controlled to be turned "on" and Τ1 and Τ2 are controlled to be turned on and off several times in a complementary manner, and 100110909 Form No. A0101 Page 22 of 28 1003361457-0 201240318 - In order to output a negative alternation in the AC output (0UT1), T1 and T2 and T5 are both controlled to be off, T6 is controlled to be on" and T3 and T4 are Then it is controlled to be turned on and off several times in a complementary manner. 2. The inverter module of claim 2, wherein the first, second, third, and fourth switching devices (>n, T2, T3, T4) have a A semiconductor component of a specification, and the fifth switching device (Τ5) and the sixth switching device (Τ6) are semiconductor components having a second specification, and the second specification is different from the first specification. 3. The inverter module as described in claim 2, characterized in that the fifth switching device (Τ5) and the sixth switching device (Τ6) have an intrinsic conduction loss (intrinsic conduction 1〇ss) ), which is lower than the intrinsic conduction loss of each of the switching device (T1), the second switching device (η), the third switching device (T3), and the fourth switching device (T4). 4. The inverter module according to claim 3, wherein the fifth switching device (T5) and the sixth switching device are thyristor-type semiconductors, and A switching device (T1), a second switching device (T2), a third switching device (T3), and a fourth switching device (Τ4) are transistor type (transist〇r_type) semiconductors. A flow reactor comprising a flow reactor module according to any one of the preceding claims. A three-phase flow reactor, characterized in that it comprises at least three legs, each of which comprises at least one of the aforementioned flow reactors according to any one of the preceding claims. Module. 100110909 Form No. A0101 Page 23 of 28 1003361457-0