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TW201244034A - Package structure having embedded electronic component and fabrication method thereof - Google Patents

Package structure having embedded electronic component and fabrication method thereof Download PDF

Info

Publication number
TW201244034A
TW201244034A TW100114827A TW100114827A TW201244034A TW 201244034 A TW201244034 A TW 201244034A TW 100114827 A TW100114827 A TW 100114827A TW 100114827 A TW100114827 A TW 100114827A TW 201244034 A TW201244034 A TW 201244034A
Authority
TW
Taiwan
Prior art keywords
layer
opening
wafer
solder
dielectric layer
Prior art date
Application number
TW100114827A
Other languages
Chinese (zh)
Other versions
TWI418003B (en
Inventor
Zhao-Chong Zhng
Original Assignee
Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to TW100114827A priority Critical patent/TWI418003B/en
Priority to CN2011103038632A priority patent/CN102760715A/en
Priority to US13/352,664 priority patent/US8884429B2/en
Publication of TW201244034A publication Critical patent/TW201244034A/en
Application granted granted Critical
Publication of TWI418003B publication Critical patent/TWI418003B/en
Priority to US14/314,242 priority patent/US9129870B2/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Disclosed is a package structure having an embedded electronic component, including a carrier board formed with an opening, a chip received in the opening and having solder tin bumps formed thereon, a dielectric layer covering the carrier board and the chip and encapsulating the solder tin bumps, a circuit layer formed on the dielectric layer, an insulating protection layer formed over the dielectric layer and the circuit layer, and a solder tin material disposed in the dielectric layer and the insulating protection layer to electrically connect to the solder tin material in the circuit layer and the solder tin bumps, thereby shortening the signal transmission path between the chip and the carrier board to prevent signal loss. The invention further provides a method of fabricating the package structure as described above.

Description

201244034 六、發明說明: 【發明所屬之技術領域】 [0001] , ^ 本發明係有關一種封裝結構,尤指一種嵌埋電子元 件之封裝結構及其製法。 【先前技術】 [0002] ^ 隨者半導體封裝技術的演進,半導體農置 (Semiconductor device)已開發出不同的封裝型態, 而為滿足封裝結構高積集度(integration)以及微型化 (Miniaturization)的封裝需求,封裝形式遂發展出打 線式(Wire bonding)或覆晶式(Flip Chip)封裝形態 ,其主要係將晶片藉由金線電性連接導線架或將晶片 藉由焊錫凸塊電性連接封裝基板》 如第1圖所示,係為一習知覆晶式封裝結構之剖面圖 ,該封裝結構1係包括:一封裝基板1〇,係具有覆晶面 l〇a與植球面i〇b,該覆晶面l〇a上具有焊錫凸塊1〇();晶 片11,係藉由錫球11 〇對應覆晶結合於該焊錫凸塊丨〇 〇上 ’以及焊球16,係形成於該植球面1 〇 b上。 然,習知覆晶封裝結構1中,該封裝基板10之線路係 微小等級,使該晶片11之錫球110的間距無法縮小,而使 該封裝結構1難以滿足微型化之需求。 [0005] 再者,於覆晶製程中,該封裝基板10需形成焊錫凸 塊100,且該晶片11需形成錫球11(),使得當封裝結構1 作用時’該晶片11與封裝基板丨〇之間的訊號傳輸路徑過 長’且傳輸時需經過不同介質(焊錫凸塊1〇〇與錫球n〇 100114827 ),因而導致訊號容易損失。 表單編號A0101 第4頁/共20頁 1002024826-0 201244034 [0006] 因此,如何克服上述習知技術中之種種問題,實已 成目前亟欲解決的課題。 【發明内容】 [0007] 鑑於上述習知技術之缺失,本發明提供一種嵌埋電 子元件之封裝結構,係包括:承載板,係具有開口與金 屬層,且令該金屬層覆蓋於該開口之一端;晶片,係收 納於該開口中,且具有相對之作用面與非作用面,該作 用面上具有複數電極墊,且各該電極墊上具有焊錫凸塊 ,而該非作用面係接置於該金屬層上;介電層,係覆於 〇 該承載板及晶片上且包覆該焊錫凸塊,並填入該晶片與 該開口壁面之間,又該介電層具有複數通孔,以對應外 露該焊錫凸塊;線路層,係設於該介電層上,且具有複 數電性接觸墊;絕緣保護層,係敷設於該介電層與線路 層上,且具有複數第一開孔,令該第一開孔連通該通孔 而外露該焊錫凸塊;以及焊錫材,係填充於該第一開孔 與該通孔中,以電性連接該線路層與該焊錫凸塊。 q [〇〇〇8] 前述之封裝基板中,該絕緣保護層復具有複數第二 開孔,令該些電性接觸墊對應外露各該第二開孔,俾供 設置焊球。 [0009] 本發明復提供一種嵌埋電子元件之封裝結構,係包 括:承載板,係具有開口與金屬層,且令該金屬層覆蓋 於該開口之一端;晶片,係收納於該開口中,且具有相 對之作用面與非作用面,該作用面上具有複數電極墊, 且各該電極墊上具有焊錫凸塊,而該非作用面係接置於 該金屬層上;介電層,係覆於該承載板及晶片上且包覆 100114827 表單編號A0101 第5頁/共20頁 1002024826-0 201244034 該焊錫凸塊,並填入該晶片與該開口壁面之間;線路層 ,係設於該介電層上,且具有複數電性接觸墊及位於該 介電層中並電性連接該焊錫凸塊之導電盲孔;以及絕緣 保護層,係敷設於該介電層與線路層上,且具有複數開 孔,以令該電性接觸墊對應外露於各該開孔中。 [0010] [0011] [0012] [0013] [0014] [0015] 前述之兩種封裝基板中,該金屬層可為銅層。 由上可知,本發明嵌埋電子元件之封裝結構,係藉 由將晶片收納於該承載板之開口中,使該焊錫材或導電 盲孔可電性連接該線路層與該晶片上之焊錫凸塊,以縮 短該晶片與承載板之間的訊號傳輸路徑,且傳輸時經過 相同介質,故可避免訊號損失。 再者,因該晶片嵌埋於該承載板中,故該導電盲孔 或焊錫材之間距可配合該晶片上之焊錫凸塊之間距,使 該焊錫凸塊的間距可依需求而縮小,且該線路層之間的 間距亦可一併縮小,因而可滿足微型化之需求。 另外,本發明復提供一種嵌埋電子元件之封裝結構 之製法,如後所述。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方式 ,熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 須知,本說明書所附圖式所繪示之結構、比例、大 小等,均僅用以配合說明書所揭示之内容,以供熟悉此 技藝之人士之瞭解與閱讀,並非用以限定本發明可實施 100114827 表單編號A0101 第6頁/共20頁 1002024826-0 201244034 之限定條件,故不具技術上之實質意義,任何結構之修 飾、比例關係之改變或大小之調整,在不影響本發明所 能產生之功效及所能達成之目的下,均應仍落在本發明 所揭示之技術内容得能涵蓋之範圍内。同時,本說明書 中所引用之如“上”及“一”等之用語,亦僅為便於敘 述之明瞭,而非用以限定本發明可實施之範圍,其相對 關係之改變或調整,在無實質變更技術内容下,當亦視 為本發明可實施之範疇。 [0016] Ο [0017] 請參閱第2Α至2G圖,係為本發明嵌埋電子元件之封 裝結構之製法剖面示意圖。 如第2Α圖所示,首先,提供一具有開口 200之承載板 20,該承載板20復具有覆蓋於該開口 200之一側之金屬層 201。於本實施例中,該承載板20係為銅箔基板,該金屬 層201係為銅層。 [0018] Ο 如第2Β圖所示,提供一具有相對之作用面21a與非作 用面21b之晶片21,該作用面21 a上具有複數電極墊210 ,且於各該電極墊210上具有焊錫凸塊211,將該晶片21 收納於該開口 200中,且該非作用面21b藉由一黏著層 212結合於該金屬層201上。於本實施例中,該作用面 21a上敷設一保護層213,以覆蓋該電極墊210且與該焊 錫凸塊211齊平。 如第2C圖所示,於該承載板2 0及晶片21上形成一介 電層22,以包覆該焊錫凸塊211,且該介電層22復填入於 該晶片21與該開口 200壁面之間。 100114827 表單編號A0101 第7頁/共20頁 1002024826-0 [0019] 201244034 [0020] [0021] [0022] [0023] [0024] [0025] 如第2D圖所示,於該介電層22上沉積銅層,再藉由 圖案化製程,使該銅層形成具有複數電性接觸墊230之線 路層23。 如第2E圖所示,於該介電層22上藉由雷射方式形成 複數通孔220,以對應外露該些焊錫凸塊211,且該些通 孔2 2 0之孔緣係連接該線路層2 3。 如第2F圖所示,於該介電層22與線路層23上形成一 絕緣保護層24,該絕緣保護層24並形成有複數第一開孔 240,以令該第一開孔240連通該通孔220而外露該焊錫 凸塊211。於本實施例中,該絕緣保護層24復具有複數第 二開孔241,以令該些電性接觸墊230對應外露各該第二 開孔241。 如第2G圖所示,於該第一開孔240與該通孔220中填 充焊錫材25,以電性連接該線路層23與該焊錫凸塊211, 且將複數焊球26植接於各該電性接觸墊230上。 如第2F’及2G’圖所示,該第一開孔240’係可連通該 第二開孔241’,使該些焊球26’接觸該焊錫材25’。 本發明之製法,係先將該晶片21收納於該承載板20 之開口 200中,再形成線路層23,接著藉由焊錫材25電性 連接該線路層23與該焊錫凸塊211,以縮短該晶片21與承 載板20之間的訊號傳輸路徑,且傳輸時僅經過一種介質 (即焊錫材25),故可避免訊號損失。 再者,因該晶片21嵌埋於該承載板20中,故該通孔 220之間距係可配合該焊錫凸塊211之間距,使該焊錫凸 100114827 表單編號A0101 第8頁/共20頁 1002024826-0 [0026] 201244034 塊211的間距可依需求縮小,而該晶片21之體積將可更薄 小,以滿足微型化之需求。 [0027] 又,該線路層23之間的間距亦可一併縮小。 [0028] 請參閱第3A至3C圖,係為本發明之另一種製法之剖 面示意圖。本實施例係接續上述實施例之第2C圖的製程 ,且兩者相異處在於電性連接焊錫凸塊與線路層之方式 ,故有關本發明封裝結構之相同製程將不再贅述,以下 僅說明相異處之製程。 〇 [0029] 如第3A圖所示,於該介電層32中形成複數盲孔320, 以對應外露該晶片21之焊錫凸塊211。 [0030] 如第3B圖所示,於該介電層32上形成具有電性接觸 墊330之線路層33,且於該盲孔320中形成導電盲孔331 以電性連接該線路層33與焊錫凸塊211。 [0031] 如第3C圖所示,於該介電層32與線路層33上形成絕 緣保護層34,該絕緣保護層34並形成有複數開孔340,以 令該電性接觸墊330對應外露於該開孔340中,再將複數 焊球26植接於各該電性接觸墊330上。 [0032] 本發明之製法,係藉由導電盲孔331電性連接該線路 層33與該焊錫凸塊211,以縮短該晶片21與承載板20之 間的訊號傳輸路徑,且傳輸時僅經過一種介質(即導電 盲孔331),故可避免訊號損失。 [0033] 再者,該線路層33與該導電盲孔331係為相同材質, 例如銅,故可減少焊錫材料之使用量,因而節省製作成 1002024826-0 100114827 表單編號A0101 第9頁/共20頁 201244034 本0 [0034] 綜上所述,本發明嵌埋電子元件之封裝結構,主要 藉由該焊錫材或導電盲孔可電性連接該線路層與該晶片 ,以縮短該晶片與承載板之間的訊號傳輸路徑,故可避 免訊號損失。 [0035] 再者,因該晶片嵌埋於該承載板中,故該導電盲孔 或焊錫材之間距可配合該焊錫凸塊之間距,使該焊錫凸 塊的間距可依需求縮小,因而可滿足微型化之需求。 [0036] 上述實施例係用以例示性說明本發明之原理及其功 效,而非用於限制本發明。任何熟習此項技藝之人士均 可在不違背本發明之精神及範疇下,對上述實施例進行 修改。因此本發明之權利保護範圍,應如後述之申請專 利範圍所列。 【圖式簡單說明】 [0037] 第1圖係為習知覆晶式封裝結構之剖面圖; [0038] 第2A至2G圖係為本發明嵌埋電子元件之封裝結構之 製法的剖面示意圖;其中,第2F’及2G’圖係為第2F及2G 圖之另一實施態樣;以及 [0039] 第3A至3C圖係為本發明嵌埋電子元件之封裝結構之 製法之另一實施例的剖面示意圖。 【主要元件符號說明】 [0040] 1 封裝結構 [0041] 10 封裝基板 100114827 表單編號A0101 第10頁/共20頁 1002024826-0 201244034 [0042] 10a 覆晶面 [0043] 10b 植球面 [0044] 100 、 211 焊錫凸塊 [0045] 11 ' 21 晶片 [0046] 110 錫球 [0047] 16 ' 26 ' 26; 焊球 [0048] 20 承載板 f) [0049] 200 開口 [0050] 201 金屬層 [0051] 21a 作用面 [0052] 21b 非作用面 [0053] 210 電極墊 [0054] 212 黏著層 〇 [0055] 213 保護層 [0056] 22 ' 32 介電層 [0057] 220 通孔 [0058] 23 ' 33 線路層 [0059] 230 、 330 電性接觸墊 [0060] 24 ' 34 絕緣保護層 100114827 表單編號A0101 第11頁/共20頁 1002024826-0 201244034 [0061] 240 、 240’ 第一開孔 [0062] 241 、 241, 第二開孔 [0063] 25、25’ 焊錫材 [0064] 320 盲孑L [0065] 331 導電盲孔 [0066] 340 開孔 100114827 表單編號 A0101 第 12 頁/共 20 頁 1002024826-0201244034 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a package structure, and more particularly to a package structure for embedding an electronic component and a method of fabricating the same. [Prior Art] [0002] ^ With the evolution of semiconductor packaging technology, semiconductor device has developed different package types, in order to meet the high integration and miniaturization of package structure. Package requirements, package form, development of wire bonding (Wire bonding) or flip chip (Flip Chip) package form, which is mainly used to electrically connect the wafer to the lead frame by gold wire or to solder the wafer by solder bump Connecting the package substrate as shown in FIG. 1 is a cross-sectional view of a conventional flip chip package structure, the package structure 1 includes: a package substrate 1 〇 having a flip face l〇a and a ball surface i 〇b, the flip chip l〇a has solder bumps 1〇(); the wafer 11 is bonded to the solder bumps by solder balls 11 〇, and the solder balls 16 Formed on the spherical surface 1 〇b. However, in the conventional flip-chip package structure 1, the wiring of the package substrate 10 is minute, so that the pitch of the solder balls 110 of the wafer 11 cannot be reduced, and the package structure 1 is difficult to meet the demand for miniaturization. [0005] Furthermore, in the flip chip process, the package substrate 10 needs to form the solder bump 100, and the wafer 11 needs to form the solder ball 11 (), so that when the package structure 1 acts, the wafer 11 and the package substrate 丨The signal transmission path between the 〇 is too long' and it needs to pass through different media (solder bump 1〇〇 and solder ball n〇100114827), which leads to easy signal loss. Form No. A0101 Page 4 of 20 1002024826-0 201244034 [0006] Therefore, how to overcome various problems in the above-mentioned prior art has become a problem to be solved at present. SUMMARY OF THE INVENTION [0007] In view of the above-mentioned deficiencies of the prior art, the present invention provides a package structure for embedding electronic components, comprising: a carrier plate having an opening and a metal layer, and covering the opening with the metal layer One end of the wafer; the wafer is received in the opening, and has an opposite active surface and a non-active surface, the active surface has a plurality of electrode pads, and each of the electrode pads has a solder bump thereon, and the non-active surface is attached to the a dielectric layer overlying the carrier plate and the wafer and covering the solder bumps, and filling the wafer and the opening wall surface, the dielectric layer having a plurality of through holes to correspond to Exposed the solder bump; the circuit layer is disposed on the dielectric layer and has a plurality of electrical contact pads; the insulating protective layer is disposed on the dielectric layer and the circuit layer, and has a plurality of first openings, And the soldering material is filled in the first opening and the through hole to electrically connect the circuit layer and the solder bump. [8] In the above package substrate, the insulating protection layer has a plurality of second openings, so that the electrical contact pads respectively expose the second openings, and the solder balls are provided. [0009] The present invention further provides a package structure for embedding an electronic component, comprising: a carrier plate having an opening and a metal layer, and the metal layer covering one end of the opening; the wafer being received in the opening; And having a working surface and a non-active surface, the active surface has a plurality of electrode pads, and each of the electrode pads has a solder bump thereon, and the non-active surface is attached to the metal layer; the dielectric layer is covered by The carrier board and the wafer are covered with 100114827 Form No. A0101 Page 5 / Total 20 pages 1002024826-0 201244034 The solder bump is filled between the wafer and the opening wall surface; the circuit layer is disposed on the dielectric layer a plurality of electrical contact pads and a conductive blind vias in the dielectric layer and electrically connected to the solder bumps; and an insulating protective layer disposed on the dielectric layer and the circuit layer, and having a plurality of Opening the holes so that the electrical contact pads are correspondingly exposed in the openings. [0012] [0014] [0015] In the foregoing two package substrates, the metal layer may be a copper layer. As can be seen from the above, the package structure of the embedded electronic component of the present invention is such that the solder material or the conductive blind via can be electrically connected to the wiring layer and the solder bump on the wafer by accommodating the wafer in the opening of the carrier. The block is used to shorten the signal transmission path between the chip and the carrier board, and the same medium is transmitted during transmission, so that signal loss can be avoided. Furthermore, since the wafer is embedded in the carrier, the distance between the conductive blind holes or the solder material can be matched with the solder bumps on the wafer, so that the pitch of the solder bumps can be reduced according to requirements, and The spacing between the circuit layers can also be reduced, thereby meeting the needs of miniaturization. Further, the present invention provides a method of fabricating a package structure in which an electronic component is embedded, as will be described later. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand other advantages and functions of the present invention from the disclosure of the present disclosure. It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. 100114827 Form No. A0101 Page 6 / Total 20 pages 1002024826-0 201244034 The conditions are not technically meaningful, any structural modifications, proportional changes or adjustments in size, without affecting the invention. The efficacies and the achievable objectives should still fall within the scope of the technical content disclosed in the present invention. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention. [0016] Please refer to FIGS. 2A to 2G, which are schematic cross-sectional views showing the structure of the package structure of the embedded electronic component of the present invention. As shown in Fig. 2, first, a carrier 20 having an opening 200 is provided, the carrier 20 having a metal layer 201 covering one side of the opening 200. In this embodiment, the carrier 20 is a copper foil substrate, and the metal layer 201 is a copper layer. [0018] As shown in FIG. 2, a wafer 21 having an opposite active surface 21a and a non-active surface 21b is provided. The active surface 21a has a plurality of electrode pads 210, and has solder on each of the electrode pads 210. The bump 211 receives the wafer 21 in the opening 200, and the non-active surface 21b is bonded to the metal layer 201 by an adhesive layer 212. In the embodiment, a protective layer 213 is disposed on the active surface 21a to cover the electrode pad 210 and is flush with the solder bump 211. As shown in FIG. 2C, a dielectric layer 22 is formed on the carrier 20 and the wafer 21 to cover the solder bump 211, and the dielectric layer 22 is filled in the wafer 21 and the opening 200. Between the walls. 100114827 Form No. A0101 Page 7 / Total 20 Page 1002024826-0 [0019] [0022] [0024] [0024] [0025] As shown in FIG. 2D, on the dielectric layer 22 A copper layer is deposited, and the copper layer is formed into a wiring layer 23 having a plurality of electrical contact pads 230 by a patterning process. As shown in FIG. 2E, a plurality of via holes 220 are formed on the dielectric layer 22 by laser to correspondingly expose the solder bumps 211, and the via holes of the through holes 220 are connected to the lines. Layer 2 3. As shown in FIG. 2F, an insulating protective layer 24 is formed on the dielectric layer 22 and the circuit layer 23. The insulating protective layer 24 is formed with a plurality of first openings 240 to connect the first opening 240. The solder bumps 211 are exposed through the via holes 220. In the embodiment, the insulating protection layer 24 has a plurality of second openings 241, so that the electrical contact pads 230 correspondingly expose the second openings 241. As shown in FIG. 2G, the first opening 240 and the through hole 220 are filled with a solder material 25 to electrically connect the circuit layer 23 and the solder bump 211, and the plurality of solder balls 26 are implanted in each The electrical contact pad 230 is on. As shown in Figures 2F' and 2G', the first opening 240' is connectable to the second opening 241' such that the solder balls 26' contact the solder material 25'. In the method of the present invention, the wafer 21 is first received in the opening 200 of the carrier 20, and then the wiring layer 23 is formed. Then, the wiring layer 23 and the solder bump 211 are electrically connected by the solder material 25 to shorten the wafer. The signal transmission path between the wafer 21 and the carrier 20 is transmitted through only one medium (ie, the solder material 25), so that signal loss can be avoided. Furthermore, since the wafer 21 is embedded in the carrier 20, the distance between the through holes 220 can be matched with the distance between the solder bumps 211, so that the solder bumps 100114827 form number A0101 page 8 / total 20 pages 1002024826 -0 [0026] 201244034 The spacing of block 211 can be reduced as needed, and the volume of the wafer 21 will be thinner to meet the needs of miniaturization. [0027] Moreover, the spacing between the circuit layers 23 can also be reduced. [0028] Referring to Figures 3A through 3C, there are shown schematic views of another method of the present invention. The embodiment is the process of the second embodiment of the above embodiment, and the difference between the two is that the solder bumps and the circuit layer are electrically connected. Therefore, the same process of the package structure of the present invention will not be described again. Explain the process of the difference. [0029] As shown in FIG. 3A, a plurality of blind vias 320 are formed in the dielectric layer 32 to correspond to the solder bumps 211 exposing the wafer 21. [0030] As shown in FIG. 3B, a wiring layer 33 having an electrical contact pad 330 is formed on the dielectric layer 32, and a conductive via hole 331 is formed in the blind via 320 to electrically connect the wiring layer 33 with Solder bump 211. [0031] As shown in FIG. 3C, an insulating protective layer 34 is formed on the dielectric layer 32 and the circuit layer 33. The insulating protective layer 34 is formed with a plurality of openings 340 to expose the electrical contact pads 330. In the opening 340, a plurality of solder balls 26 are implanted on each of the electrical contact pads 330. The method of the present invention is to electrically connect the circuit layer 33 and the solder bumps 211 through the conductive vias 331 to shorten the signal transmission path between the wafer 21 and the carrier 20, and only pass through the transmission. A medium (ie, conductive blind hole 331) can avoid signal loss. [0033] Moreover, the circuit layer 33 and the conductive blind via 331 are made of the same material, such as copper, so that the amount of solder material used can be reduced, thereby saving 1002024826-0 100114827 Form No. A0101 Page 9 of 20 [0034] In summary, the package structure of the embedded electronic component of the present invention can be electrically connected to the circuit layer and the wafer by the solder material or the conductive blind via hole to shorten the wafer and the carrier board. The signal transmission path between the two can avoid signal loss. [0035] Furthermore, since the wafer is embedded in the carrier, the distance between the conductive blind holes or the solder material can be matched with the solder bumps, so that the pitch of the solder bumps can be reduced according to requirements. Meet the needs of miniaturization. The above-described embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the application patents which will be described later. BRIEF DESCRIPTION OF THE DRAWINGS [0037] FIG. 1 is a cross-sectional view of a conventional flip-chip package structure; [0038] FIGS. 2A to 2G are cross-sectional views showing a method of fabricating a package structure for embedding electronic components of the present invention; Wherein, the 2F' and 2G' diagrams are another embodiment of the 2F and 2G diagrams; and [0039] 3A to 3C are another embodiment of the method for fabricating the package structure of the embedded electronic component of the present invention. Schematic diagram of the section. [Description of Main Component Symbols] [0040] 1 Package Structure [0041] 10 Package Substrate 100114827 Form No. A0101 Page 10/Total 20 Page 1002024826-0 201244034 [0042] 10a Cladding Surface [0043] 10b Globular Surface [0044] 100 , 211 solder bumps [0045] 11 ' 21 wafers [0046] 110 solder balls [0047] 16 ' 26 ' 26; solder balls [0048] 20 carrier plates f) [0049] 200 openings [0050] 201 metal layers [0051 21a active surface [0052] 21b non-active surface [0053] 210 electrode pad [0054] 212 adhesive layer 〇 [0055] 213 protective layer [0056] 22 ' 32 dielectric layer [0057] 220 through hole [0058] 23 ' 33 circuit layer [0059] 230, 330 Electrical contact pad [0060] 24 ' 34 Insulation protection layer 100114827 Form number A0101 Page 11 / Total 20 pages 1002024826-0 201244034 [0061] 240, 240' First opening [0062 ] 241, 241, second opening [0063] 25, 25' solder material [0064] 320 blind 孑 L [0065] 331 conductive blind hole [0066] 340 opening 100114827 form number A0101 page 12 / 20 page 1002024826 -0

Claims (1)

.201244034 七、申請專利範圍: 1 . 一種嵌埋電子元件之封裝結構,係包括: 承載板,係具有開口與金屬層,且令該金屬層覆蓋於 該開口之一端; 晶片,係收納於該開口中,且具有相對之作用面與非 作用面,該作用面上具有複數電極墊,且各該電極墊上具 有焊錫凸塊,而該非作用面係接置於該金屬層上; 介電層,係覆於該承載板及晶片上且包覆該焊錫凸塊 ,並填入該晶片與該開口壁面之間,又該介電層具有複數 〇 通孔,以對應外露該焊錫凸塊; 線路層,係設於該介電層上,且具有複數電性接觸墊 y 絕緣保護層,係敷設於該介電層與線路層上,且具有 複數第一開孔,令該第一開孔連通該通孔而外露該焊錫凸 塊;以及 焊錫材,係填充於該第一開孔與該通孔中,以電性連 接該線路層與該焊錫凸塊。 0 2 .如申請專利範圍第1項所述之嵌埋電子元件之封裝結構, 其中,該金屬層係為銅層。 3 .如申請專利範圍第1項所述之嵌埋電子元件之封裝結構, 其中,該絕緣保護層復具有複數第二開孔,令該些電性接 觸墊對應外露各該第二開孔,俾供設置焊球。 4 .如申請專利範圍第3項所述之嵌埋電子元件之封裝結構, 其中,該第一開孔係連通該第二開孔,以使該些焊球接觸 該焊錫材。 100114827 表單編號A0101 第13頁/共20頁 1002024826-0 201244034 5 . 一種嵌埋電子元件之封裝結構,係包括: 承載板,係具有開口與金屬層,且令該金屬層覆蓋於 該開口之一端; 晶片,係收納於該開口中,且具有相對之作用面與非 作用面,該作用面上具有複數電極墊,且各該電極墊上具 有焊錫凸塊,而該非作用面係接置於該金屬層上; 介電層,係覆於該承載板及晶片上且包覆該焊錫凸塊 ,並填入該晶片與該開口壁面之間; 線路層,係設於該介電層上,且具有複數電性接觸墊 及位於該介電層中並電性連接該焊錫凸塊之導電盲孔;以 及 絕緣保護層,係敷設於該介電層與線路層上,且具有 複數開孔,以令該電性接觸墊對應外露於各該開孔中。 6 .如申請專利範圍第5項所述之嵌埋電子元件之封裝結構, 其中,該金屬層係為銅層。 7 . —種嵌埋電子元件之封裝結構之製法,係包括: 提供一具有開口之承載板,該承載板復具有覆蓋於該 開口之一側之金屬層; 將一具有相對之作用面與非作用面之晶片收納於該開 口中,使該非作用面接置於該金屬層上,該晶片之作用面 上並具有複數電極墊,且各該電極墊上具有焊錫凸塊; 於該承載板及晶片上形成介電層,以包覆該焊錫凸塊 ,且該介電層復填入於該晶片與該開口壁面之間; 於該介電層上形成具有複數電性接觸墊之線路層; 於該介電層上形成複數通孔,以對應外露各該焊錫凸 塊,且該通孔之孔緣連接該線路層; 100114827 表單編號A0101 第14頁/共20頁 1002024826-0 .201244034 於該介電層與線路層上形成絕緣保護層,該絕緣保護 層並形成有複數第一開孔,以令該第一開孔連通該通孔而 外露該焊錫凸塊;以及 於該第一開孔與該通孔中填充焊錫材,以電性連接該 線路層與該焊錫凸塊。 8 .如申請專利範圍第7項所述之嵌埋電子元件之封裝結構之 製法,其中,該承載板係為銅箔基板,且該金屬層係為銅 層。 9 .如申請專利範圍第7項所述之嵌埋電子元件之封裝結構之 〇 製法,其中,該絕緣保護層復具有複數第二開孔,以令該 些電性接觸墊對應外露於各該第二開孔中。 10 .如申請專利範圍第9項所述之嵌埋電子元件之封裝結構之 製法,復包括於該電性接觸墊上形成焊球。 11 .如申請專利範圍第10項所述之嵌埋電子元件之封裝結構之 製法,其中,該第一開孔係連通該第二開孔,以使該些焊 球接觸該焊錫材。 12 . —種嵌埋電子元件之封裝結構之製法,係包括: 〇 提供一具有開口之承載板,該承載板復具有覆蓋於該 開口之一侧之金屬層; 將一具有相對之作用面與非作用面之晶片收納於該開 口中,使該非作用面接置於該金屬層上,該晶片之作用面 上並具有複數電極墊,且各該電極墊上具有焊錫凸塊; 於該承載板及晶片上形成介電層,以包覆該焊錫凸塊 ,且該介電層復填入於該晶片與該開口壁面之間; 於該介電層中形成複數盲孔,以對應外露該焊錫凸塊 100114827 表單編號A0101 第15頁/共20頁 1002024826-0 201244034 於該介電層上形成具有複數電性接觸墊之線路層,且 於該盲孔中形成導電盲孔以電性連接該線路層與焊錫凸塊 » 於該介電層與線路層上形成絕緣保護層,該絕緣保護 層並形成有複數開孔,以令該電性接觸墊對應外露於該開 孔中;以及 將複數焊球植接於各該電性接觸墊上。 13 .如申請專利範圍第12項所述之嵌埋電子元件之封裝結構之 製法,其中,該承載板係為銅箔基板,該金屬層係為銅層 100114827 表單編號A0101 第16頁/共20頁 1002024826-0.201244034 VII. Patent application scope: 1. A package structure for embedding electronic components, comprising: a carrier plate having an opening and a metal layer, and the metal layer covering one end of the opening; the wafer is received in the In the opening, and having an opposite active surface and a non-active surface, the active surface has a plurality of electrode pads, and each of the electrode pads has a solder bump thereon, and the non-active surface is attached to the metal layer; the dielectric layer, Attaching to the carrier plate and the wafer and covering the solder bumps, and filling the wafer and the opening wall surface, the dielectric layer having a plurality of through holes for correspondingly exposing the solder bumps; The layer is disposed on the dielectric layer and has a plurality of electrical contact pads y insulating protective layer disposed on the dielectric layer and the circuit layer, and has a plurality of first openings for connecting the first openings The through hole exposes the solder bump; and the solder material is filled in the first opening and the through hole to electrically connect the circuit layer and the solder bump. The package structure of the embedded electronic component according to claim 1, wherein the metal layer is a copper layer. The package structure of the embedded electronic component of claim 1, wherein the insulating protection layer has a plurality of second openings, so that the electrical contact pads respectively expose the second openings.俾 For setting solder balls. 4. The package structure of the embedded electronic component of claim 3, wherein the first opening communicates with the second opening to contact the solder balls. 100114827 Form No. A0101 Page 13 of 20 1002024826-0 201244034 5 . A package structure for embedding electronic components, comprising: a carrier plate having an opening and a metal layer, and covering the metal layer at one end of the opening The wafer is received in the opening and has an opposite active surface and a non-active surface. The active surface has a plurality of electrode pads, and each of the electrode pads has a solder bump thereon, and the non-active surface is attached to the metal a dielectric layer covering the carrier and the wafer and covering the solder bump and filling the wafer and the opening wall; the circuit layer is disposed on the dielectric layer and has a plurality of electrical contact pads and conductive blind holes in the dielectric layer and electrically connected to the solder bumps; and an insulating protective layer disposed on the dielectric layer and the circuit layer, and having a plurality of openings The electrical contact pads are correspondingly exposed in each of the openings. 6. The package structure of an embedded electronic component according to claim 5, wherein the metal layer is a copper layer. 7. A method of fabricating a package structure for embedding an electronic component, comprising: providing a carrier plate having an opening, the carrier plate having a metal layer covering one side of the opening; and having a relative active surface The active surface of the wafer is received in the opening, the non-active surface is placed on the metal layer, and the active surface of the wafer has a plurality of electrode pads, and each of the electrode pads has solder bumps thereon; on the carrier plate and the wafer Forming a dielectric layer to cover the solder bump, and filling the dielectric layer between the wafer and the opening wall surface; forming a circuit layer having a plurality of electrical contact pads on the dielectric layer; Forming a plurality of through holes on the dielectric layer to correspondingly expose the solder bumps, and the hole edges of the through holes are connected to the circuit layer; 100114827 Form No. A0101 Page 14 of 20 1002024826-0 .201244034 Forming an insulating protective layer on the layer and the circuit layer, the insulating protective layer is formed with a plurality of first openings, so that the first opening communicates with the through hole to expose the solder bump; and the first opening and the Through hole Filling a solder material, electrically connecting the wiring layer and the solder bump. The method of manufacturing a package structure for embedding an electronic component according to claim 7, wherein the carrier plate is a copper foil substrate, and the metal layer is a copper layer. 9. The method of manufacturing a package structure for embedding an electronic component according to claim 7, wherein the insulating protection layer has a plurality of second openings, so that the electrical contact pads are correspondingly exposed to each of the plurality of openings. In the second opening. 10. The method of fabricating a package structure for embedding an electronic component according to claim 9, wherein the method comprises forming a solder ball on the electrical contact pad. 11. The method of claim 4, wherein the first opening is in communication with the second opening such that the solder balls contact the solder material. 12. A method of fabricating a package structure for embedding an electronic component, comprising: providing a carrier plate having an opening, the carrier plate having a metal layer covering one side of the opening; and having a relative active surface The non-active surface of the wafer is received in the opening, the non-active surface is placed on the metal layer, and the active surface of the wafer has a plurality of electrode pads, and each of the electrode pads has a solder bump; the carrier plate and the wafer Forming a dielectric layer on the solder bump to cover the solder bump, and filling the dielectric layer between the wafer and the opening wall surface; forming a plurality of blind holes in the dielectric layer to correspondingly expose the solder bump 100114827 Form No. A0101 Page 15 of 20 1002024826-0 201244034 A circuit layer having a plurality of electrical contact pads is formed on the dielectric layer, and a conductive via hole is formed in the blind via to electrically connect the circuit layer with Solder bumps are formed on the dielectric layer and the circuit layer, and the insulating protective layer is formed with a plurality of openings to expose the electrical contact pads to the openings; and The solder balls connected to each of the implanted electrical contact pads. The method of manufacturing a package structure for embedding an electronic component according to claim 12, wherein the carrier plate is a copper foil substrate, and the metal layer is a copper layer 100114827. Form No. A0101 Page 16 of 20 Page 1002024826-0
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI556395B (en) * 2015-03-25 2016-11-01 恆勁科技股份有限公司 Electronic package and method of fabricating the same

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134270A (en) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd Semiconductor device and manufacturing method of the same
US8633588B2 (en) 2011-12-21 2014-01-21 Mediatek Inc. Semiconductor package
US9659893B2 (en) 2011-12-21 2017-05-23 Mediatek Inc. Semiconductor package
KR102033788B1 (en) * 2013-06-13 2019-10-17 에스케이하이닉스 주식회사 Embedded package and method of fabricating the same
WO2015026344A1 (en) * 2013-08-21 2015-02-26 Intel Corporation Bumpless die-package interface for bumpless build-up layer (bbul)
CN107658284B (en) * 2013-10-25 2020-07-14 日月光半导体制造股份有限公司 Semiconductor package and method of manufacturing the same
TWI591768B (en) * 2015-11-30 2017-07-11 矽品精密工業股份有限公司 Package structure and method of fabrication
CN106971993B (en) 2016-01-14 2021-10-15 三星电子株式会社 Semiconductor package
KR102595276B1 (en) 2016-01-14 2023-10-31 삼성전자주식회사 Semiconductor packages
US9887167B1 (en) * 2016-09-19 2018-02-06 Advanced Semiconductor Engineering, Inc. Embedded component package structure and method of manufacturing the same
CN107170731A (en) * 2017-05-05 2017-09-15 华为技术有限公司 Embedded substrate and its manufacture method
KR101901712B1 (en) * 2017-10-27 2018-09-27 삼성전기 주식회사 Fan-out semiconductor package
EP3522685B1 (en) 2018-02-05 2021-12-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Metallic layer as carrier for component embedded in cavity of component carrier
EP3723459A1 (en) 2019-04-10 2020-10-14 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with high passive intermodulation (pim) performance
US11462509B2 (en) * 2019-10-29 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with electronic device in cavity substrate and method for forming the same
EP3866187A1 (en) * 2020-02-12 2021-08-18 Infineon Technologies Austria AG A semiconductor device comprising an embedded semiconductor die and a method for fabricating the same
CN115763400A (en) * 2022-11-24 2023-03-07 成都海光集成电路设计有限公司 Chip fan-out packaging method and chip fan-out packaging part
CN118039597A (en) * 2024-01-17 2024-05-14 苏州纳芯微电子股份有限公司 Buried chip substrate structure and manufacturing method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW546800B (en) * 2002-06-27 2003-08-11 Via Tech Inc Integrated moduled board embedded with IC chip and passive device and its manufacturing method
TWI260079B (en) * 2004-09-01 2006-08-11 Phoenix Prec Technology Corp Micro-electronic package structure and method for fabricating the same
TWI283050B (en) * 2005-02-04 2007-06-21 Phoenix Prec Technology Corp Substrate structure embedded method with semiconductor chip and the method for making the same
TWI308382B (en) * 2006-07-25 2009-04-01 Phoenix Prec Technology Corp Package structure having a chip embedded therein and method fabricating the same
TWI301663B (en) * 2006-08-02 2008-10-01 Phoenix Prec Technology Corp Circuit board structure with embedded semiconductor chip and fabrication method thereof
TWI392070B (en) * 2008-05-05 2013-04-01 Unimicron Technology Corp Package substrate having semiconductor component embedded therein and fabrication method thereof
TWI407542B (en) * 2008-06-19 2013-09-01 Unimicron Technology Corp Substrate having semiconductor chip embedded therein and fabrication method thereof
KR101058621B1 (en) * 2009-07-23 2011-08-22 삼성전기주식회사 Semiconductor package and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI556395B (en) * 2015-03-25 2016-11-01 恆勁科技股份有限公司 Electronic package and method of fabricating the same

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