201222724 六、發明說明： 【發明所屬之技術領域】 本發明係提供一種雙鑲嵌製程，尤指一種可以應用於超 低介電常數(ultra low-k)材料之雙鑲嵌製程。 【先前技術】 雙鑲敌製程（dual damascene process)是一種能同時形成 一金屬導線以及一通孔插塞(via plug)之上下堆疊内連線結 構的方法。雙鑲嵌結構是用來連接半導體晶片中各層間的不 同元件與導線’並利用其周圍的金屬層間介電材料(inter metal dielectrics)及内層介電材料(inter layer dielectrics)來與 其他元件相隔離。由於在製備雙鑲嵌結構時，最後還會進行 一道化學機械研磨製程(chemical mechanical polish, CMP)， 使半導體晶片表面變的很平坦，非常利於後續各種沉積及微 影（photo-lithography)等製程的進行，以製備結構良好的多重 金屬内連線（multilevel interconnects)，因此雙鑲嵌結構被廣 泛地應用在積體電路的製程上。 此外，銅雙鑲嵌技術搭配低介電常數(l〇w-k)介電層更為 目前所知對於高積集度、高速(high-speed)邏輯積體電路晶片 製造以及針對深次微米（deep sub-micro meter)半導體製程最 佳的金屬内連線解決方案。這是由於銅具有低電阻值（比鋁 201222724 低30%)以及較佳抗電致遷（electromigration resistance)的特 性，而低介電常數材料則可幫助降低金屬導線間之電容效應 所造成的RC延遲(RC delay)，由此可知，低介電常數材料搭 配銅金屬雙鑲嵌内連線技術在積韙電路製程中顯得日益重 要0 然而，習知雙鑲嵌製程需要多次反覆的上光阻、底抗反 射層塗佈、曝光、顯影、顯影後檢驗(after develpping inspection，ADI)、蝕刻以及蝕刻後檢驗（after etching inspection，ΑΕΙ)等步驟才能夠完成。這在積體電路製程的關 鍵尺寸（critical dimension，CD)縮小演進至深次微米甚至奈 米（nanometer，1 nm〜100 nm)等級時，不但十分費時、耗費成 本’同時也造成產能以及圖案轉移的精確度下降。尤其是當 進行製程異常所需的重工(rework)步驟時，更會嚴重影響金 屬層間電層的扣备，發生介電常數劣化(dieiectric constant, k value，degradation)或關鍵尺寸變異（critica丨 dimensi〇n variation)等問題，造成介電層發生線路變形（linedist〇rti〇n) 或產生脆裂（fragile)的狀況，使得原先應為直線之溝渠或者 通孔(via hole)產生扭曲（wiggling)的情況，進而影響後續金屬 化製程的良率。 因此隨著積體電路的發展日趨精密與複雜，如何提昇雙 镶肷製紅的良率，疋目刖積體電路製程中重要的課題。 201222724 【發明内容】 _之製作供-種可應用於超低介電常 根據本::所請專利範圍係提供一種雙鑲嵌 首絲成-介電層於_基底上 _該介電層上，且該第一圖案化遮=一= 材:Γ介電層上並覆蓋該第-圖案化遮“ 化遮罩於該介電層上，且該第二圖案化遮罩 接著於該第二圖案化遮罩十形成-第二開 节第1料二孔與㈣—開孔具有—特定間距，最後利用 Θ第-圖案化遮罩當作朗遮罩，以 二開孔移除部份之該材料層與部份之料電層。第 =於本發明係於預定形成雙鑲嵌圖案的介電層上方設 ^止層、材料層與護層等，因此介電層完全不會受到 乍溝渠與通孔(viahG丨e)之圖案化遮罩所f的糊、清潔、 步驟、以及顯影後檢驗(AD_刻後檢驗(aei)發 =吊時的重工步驟所影響，進而可有效確保金屬層間介電 層與雙鑲嵌圖案的品質，提高良率。 【實施方式】 201222724 為使熟習本發明所屬技術領域之一般技藝者能更進一 步了解本發明，下域列舉本發明之數個触實施例，並配 合所附圖式，詳細說明本發明的構成内容及所欲達成之功 效0 請參閱第1圖至第10圖，第i圖至第1〇圖係為本發明 所提供之雙鑲嵌製作方法之-較佳實施例的示意圖。如第ι 圖所示，首先提供-基底⑽，如砍基底、切基底、或石夕 覆絕緣（3山(：〇11-011-丨11如以01*，3〇1)基底等，基底1〇〇表面上 形成有至少兩導電件102、104，且該兩導電件102、⑽之 間另形成有-絕緣材料層106用以電性隔離此兩導電件 102、104。其中，導電件1〇2、1〇4可為下列中至少一者： 金屬氧化物半導體(metal_0Xlde semie〇nduct〇r，M〇s)電晶體 元件的汲極/源極與閘極、電阻、直通矽晶穿孔 (Thr〇ugh-Sillcon Vla，TSV)、換雜區、金屬導線層等；絕緣 材料層1G6可為層間介電層或淺溝渠隔離(sti)等，且視產品 設計與製程需求’導電件m、1(M與基底⑽之間另可形 成有至少一層間介電層（圖未示）。 接著於基底100表面上依序形成一蓋層1〇8、一介電層 110以及一第一圖案化遮罩112。其中，蓋層⑽係為一選 擇性形成的材料層’用以保護導電件1G2、1G4並可加強後 續幵/成之介電層110的附著力。蓋層⑽的材質例如是氮化 201222724 矽（SiN)、氧化矽（SiO)、碳化矽（sic)、氮碳化矽（siCN)或氮 氧化矽（SiON)等，較佳者，蓋層108為一含氮的介電層，但 並不以此為限。 介電層110可包含單層或多層的介電材質，其係選用自 介電常數低於3.5的無機類或有機類兩種低介電常數材料。 例如含氟石夕氧化物（fluorine-doped oxide，FSG)、有機石夕玻璃 (organosilicate，OSG)、芳香族熱固性聚合物（ar〇matic thermosets polymers)、無機含氫矽酸鹽（hydrogen silsesquioxane，HSQ，SiO:H)、甲基矽酸鹽（methyl silsesquioxane，MSQ, SiO:CH3)、混合有機矽氧烷聚合物 (Hybrid Organic Siloxane Polymer, HOSP)、氫摻雜聚矽酸鹽 (hydrio polysilsesquioxane，H-PSSQ)、曱基摻雜聚石夕酸鹽 (methyl polysilsesquioxane，M-PSSQ)、苯基摻雜聚石夕酸鹽 (phenyl polysilsesquioxane，P-PSSQ)或多孔性凝膠（porous sol-gel)等等’較佳者’介電層no為一具超低介電常數(ultra low-k，ULK)的材料(例如k<2.5)。另外，若根據其形成的方 式又可分成化學氣相沉積(CVD)、電漿加強化學氣相沈積 (plasma enhanced chemical vapor deposition, PECVD) ' 高密 度電聚化學氣相沈積(high density plasma CVD)或旋塗式塗 佈法(Spin-on)等方式所製成，但並不以此為限。 第一圖案化遮罩112具有一開口 120，用來定義雙鑲嵌 201222724 結構中溝渠開口的位w， 於兩導雷件⑽ 此開σ 120的相對位置約略對應 、1〇4之間並部分重叠此兩導電件102、104。 -，-圖案化遮罩112可為單層遮罩或為多 = 結構’且其可包含金屬料或非金屬遮 =兩f合。在本較佳實施财，第—㈣化遮罩ιΐ2 二夕層遮軍’例如可包含一鈦層心、一氮化鈦層⑽ 氧化物層n2c等的多層堆疊結構。而其製作方式例 如為先依序全面性形成鈦層心、氮化鈦層咖以及氧化 =U2c以構成一遮罩層’然後再進行一光阻塗佈與微影 製程，以於其上形成一圖案化的光阻層（圖未示）’接著進行 一1 虫刻製程以進行一圖案轉移，以於遮罩層中峨開口 f形成第—圖案化遮軍112。此外，視產品設計與製程需 求’第-圖案化遮罩m與介電層11〇之間另可選擇性形成 有-蝕刻停止層114 ’例如氮氧化邦讀)等，用來當作對 第-圖案化遮罩112進行圖案轉移時的㈣阻障層以保護其 下方的介電層110。此外’若在進行第一圖案化遮罩ιΐ2的 顯影後檢驗(ADI)或蝕刻後檢驗(AEI)發生異常時，本較佳實 施例可直接進行-重：!！步驟，且由於介電層則上方設置有 触刻停止層m，因此介電層11G完全不會受到製備第—圖 案化遮罩112所需的触刻、清潔、去光阻等步驟以及顯影後 檢驗(ADI)或蝕刻後檢驗(AEI)發生異常時的重工步驟所影 響，而可確保介電層的品質。 201222724 隨後如第2圖與第3圖所示，於基底100表面上依序再 形成一材料層130以及一第二圖案化遮罩140，並覆蓋於第 一圖案化遮罩112、蝕刻停止層114與介電層110之上。其 中’材料層130可為含C、Η、Ο的高分子材料，例如旋塗 碳材硬遮罩層（Carbon -spin on hardmask，C-S0H)，但並不以 此為限。而第二圖案化遮罩14〇具有一第一開孔18〇，用來 疋義雙鑲嵌結構中通孔(via hole)的位置’且此第一開孔18〇 的位置約略位於兩導電件1〇2、1〇4之一，例如導電件1〇4 的正上方。 在本較佳實施例中，第二圖案化遮罩14〇係可為—多層 遮罩或一單層遮罩，例如為單一氧化物層。而其製作方式例 如為先以化學氣相沉積法形成一矽氧化合物當作遮罩層 140a，然後再於其上形成一圖案化的光阻層15()，並進行一 蝕刻製程以進行一圖案轉移，以於遮罩層14〇a中蝕刻出第 一開孔180，形成第二圖案化遮罩14〇。且視產品設計與製 # 程需求，第二圖案化遮罩14〇與材料層130之間另可選擇性 形成有一護層160，例如氮化矽(siN)等，用來當作對第二圖 案化遮罩140進行圖案轉移時的蝕刻停止層以保護其下方的 材料層130。而圖案化的光阻層15〇與第二圖案化遮罩14〇 之間另可選擇性开；^成有一第一底抗反射層（B arc) 170，例如 氮氧化矽（Si〇N)等。 10 201222724 ^第4圖與第$圖所示’接著 、” 微影製程，於美店1ΠΛ t /儿積、光阻塗佈與 _以及： 上依序形成-第二底抗反· 圖案化的光阻層200，並覆蓋4 " 14〇、護層⑽血材料# μ覆盘在第一圖案化遮罩 層200當作逆| ]用圖案化的光阻 -制16Gt_料止層，來進行另 餘刻製程以進行另一圖案轉移，以 =仃另 的位置，=二Γ用來定義雙鑲⑽^ HM之另Γ 的位置約略位於兩導電件⑽、 之另—者’例如導電件102的正上方。 值得注意的是，第二開孔22〇與第 具有一特定間距，且此特 ^ 且並 ⑸伽解㈣。心本較佳實施例可適 田凋整先阻層150、光阻層2 、 二庙浐只如成弟底抗反射層170與第 -ml 220曰夂0的厚度，使得其在形成第一開孔180與第 自的轉程時，便同時消耗殆盡;當然亦 完全去除殘留的光阻層⑼與第一底 :果，二7〇、光阻層2〇0與第二底抗反射層190。此外， 2圖與第5圖所㈣步砸於相獻顯影後檢 時L或㈣後檢驗(AEI)發生異常時’本較佳實施例可隨 時進仃所需進行的重工步驟 _亭止層n4'材料層:二=電層110上方設置有 — 射十屠130與護層⑽，因此介電層11〇 元王不會受到第2圖與第5圖所她刻、清潔、去光阻等 201222724 步驟以及顯影後檢驗(ADI)或蝕刻後檢驗(ΑΕΙ)發生異常時的 重工步驟所影響而發生介電常數劣化(k value degradation)或 關鍵尺寸變異等問題，進而可確保金屬層間介電層與·雙鑲嵌 圖案的品質。 在完成顯影後檢驗(ADI)步驟確認第一開孔180與第二 .開孔220的佈局圖案無誤之後，接著如第6圖所示，利用第 二圖案化遮罩140當作蝕刻遮罩來蝕刻護層160，以將第二 圖案化遮罩140中第一開孔180與第二開孔220的圖案轉移 至護層160中。 之後如第7圖所示，利用第二圖案化遮罩140以及護層 160當作蚀刻遮罩來部分蚀刻材料層130、触刻停止層114 與介電層110，以將第一開孔180與第二開孔220的圖案繼 續向下轉移至材料層130、蝕刻停止層114以及介電層110 中，並於介電層110中相對應形成第一通孔180a與第二通 孔220a。同樣地，本較佳實施例可適當調整第二圖案化遮罩 140與護層160的厚度以及蝕刻參數，使得其在形成第一通 孔180a與第二通孔220a的蝕刻製程時，便同時消耗殆盡； 當然亦可再結合清洗製程，以完全去除殘餘的第二圖案化遮 罩140與護層160。然後第8圖所示，進行一剝除製程，例 如可通入含有二氧化碳、一氧化碳或氫氣等之氣體，完全去 除剩餘的材料層130，以曝露具有開口 120圖案的第一圖案 12 201222724 具有第一通孔18〇3與第二通孔220a圖案的触 r μ、如第9圖所示，利用第一圖案化遮罩112以及蝕刻 :止層m當作I虫刻遮罩來领刻介電層11〇與蓋層1〇8，以 ’開口 120的圖案繼續向下轉移至介電们ίο中，並同時將 第通孔驗與第二通孔22〇a的圖案繼續向下轉移至介電 :=與蓋層108 t ’而分別曝露導電件1〇4與丨 雙鑲嵌圖案250的製程。 '旱〜的是本較佳實施例之第一圖案化遮罩m係為 一多層堆疊遮罩’其包含鈦層心以及氮化鈦層112b等融 刻速率不同於介電層UG、蓋層⑽以及儀刻停止層114的 =遮罩材質，而相對具有較高的㈣選擇比。因此在完成 雙鑲嵌圖案250的製程時，第一圖案化遮罩ιΐ2的氧化物層201222724 VI. Description of the Invention: [Technical Field] The present invention provides a dual damascene process, especially a dual damascene process that can be applied to ultra low-k materials. [Prior Art] A dual damascene process is a method of simultaneously forming a metal wire and a via interconnect structure on a via plug. The dual damascene structure is used to connect different components and wires ' between layers in a semiconductor wafer and is isolated from other components by intermetallic dielectrics and inter-layer dielectrics. Since a chemical mechanical polish (CMP) is finally used in the preparation of the dual damascene structure, the surface of the semiconductor wafer is flattened, which is advantageous for various subsequent deposition and photo-lithography processes. This is done to prepare well-structured multilevel interconnects, so the dual damascene structure is widely used in the process of integrated circuits. In addition, copper dual damascene technology with a low dielectric constant (l〇wk) dielectric layer is now known for high-accumulation, high-speed logic integrated circuit chip fabrication and for deep submicron (deep sub -micro meter) The best metal interconnect solution for semiconductor processes. This is because copper has low resistance (30% lower than aluminum 201222724) and better resistance to electromigration resistance, while low dielectric constant materials can help reduce the RC caused by the capacitive effect between metal wires. RC delay, it can be seen that the low dielectric constant material with copper metal dual damascene interconnect technology is becoming more and more important in the process of accumulation circuit. However, the conventional dual damascene process requires multiple times of overlying photoresist. The bottom anti-reflective layer coating, exposure, development, after develpping inspection (ADI), etching, and post-etch inspection (ΑΕΙ) steps can be completed. This is not only time-consuming and costly when the critical dimension (CD) of the integrated circuit process is scaled down to the deep sub-micron or nanometer (1 nm to 100 nm) level, which also causes capacity and pattern transfer. The accuracy is reduced. Especially when the rework step required for the process abnormality is carried out, the electrical layer of the metal layer is seriously affected, and the dielectric constant deterioration (dieiectric constant, k value, degradation) or critical size variation (critica丨dimensi) occurs. 〇n variation) and other problems, causing line deformation (linedist〇rti〇n) or fragile conditions in the dielectric layer, causing distortion (wiggling) in the original ditch or via hole. The situation, which in turn affects the yield of subsequent metallization processes. Therefore, with the development of integrated circuits becoming more and more sophisticated and complex, how to improve the yield of double-inlaid red, and to focus on the important issues in the circuit process. 201222724 [Summary of the Invention] _ The production of the _ can be applied to ultra-low dielectric often according to this:: The scope of the patent is to provide a dual-embedded first wire into a dielectric layer on the _ substrate _ the dielectric layer, And the first patterned mask is on the dielectric layer and covers the first patterned mask on the dielectric layer, and the second patterned mask is followed by the second pattern. The mask 10 is formed - the second opening, the first material, the second hole, and the (four) - the opening have a specific spacing, and finally the first-patterned mask is used as the lang mask, and the second opening is used to remove the portion. The material layer and part of the material layer. The invention is based on the dielectric layer which is intended to form the dual damascene pattern, and the dielectric layer, the material layer and the protective layer, etc., so that the dielectric layer is completely free from the trenches and Through-hole (viahG丨e) patterned mask, paste, cleaning, steps, and post-development inspection (AD_ post-inspection (aei) hair = heavy-duty steps during lifting, which can effectively ensure the metal layer The quality of the dielectric layer and the dual damascene pattern improves the yield. [Embodiment] 201222724 A person skilled in the art can further understand the present invention. The following is a list of several embodiments of the present invention, and the composition of the present invention and the desired effect are described in detail with reference to the drawings. Please refer to FIG. 1 to FIG. 10, the first to the first drawings are schematic views of a preferred embodiment of the dual damascene fabrication method provided by the present invention. As shown in Fig. 1a, a substrate (10) is first provided, such as a substrate, a substrate, and a substrate. Or a stone-covered insulation (3 mountain (: 〇11-011-丨11 such as 01*, 3〇1) substrate, etc., at least two conductive members 102, 104 are formed on the surface of the substrate 1 ,, and the two conductive An insulating material layer 106 is further formed between the members 102 and (10) for electrically isolating the two conductive members 102, 104. The conductive members 1〇2, 1〇4 may be at least one of the following: a metal oxide semiconductor (metal_0Xlde semie〇nduct〇r, M〇s) The drain/source and gate of the transistor element, resistance, through-thickness perforation (Thr〇ugh-Sillcon Vla, TSV), changeover area, metal wire layer, etc. The insulating material layer 1G6 may be an interlayer dielectric layer or a shallow trench isolation (sti), etc., depending on product design and process requirements At least one interlayer dielectric layer (not shown) may be formed between the conductive members m, 1 (M and the substrate (10). Then, a cap layer 1 〇 8 and a dielectric layer 110 are sequentially formed on the surface of the substrate 100. And a first patterned mask 112. The cap layer (10) is a selectively formed material layer 'to protect the conductive members 1G2, 1G4 and to enhance the adhesion of the subsequent dielectric layer 110. The material of the layer (10) is, for example, nitridation 201222724 矽 (SiN), yttrium oxide (SiO), yttrium carbide (sic), lanthanum oxynitride (siCN) or cerium oxynitride (SiON). Preferably, the cap layer 108 is one. Nitrogen-containing dielectric layer, but not limited to this. The dielectric layer 110 may comprise a single layer or a plurality of layers of dielectric materials selected from inorganic or organic low dielectric constant materials having a dielectric constant of less than 3.5. For example, fluorine-doped oxide (FSG), organosilicate (OSG), ar〇matic thermosets polymers, and hydrogen silsesquioxane (HSQ) , SiO: H), methyl silsesquioxane (MSQ, SiO: CH3), Hybrid Organic Siloxane Polymer (HOSP), hydrogen-doped polysilicate (Hydrio polysilsesquioxane, H -PSSQ), methyl polysilsesquioxane (M-PSSQ), phenyl polysilsesquioxane (P-PSSQ) or porous sol-gel The 'better' dielectric layer no is an ultra low-k (ULK) material (eg k<2.5). In addition, according to the manner in which it is formed, it can be further divided into chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and high density plasma CVD. Or by spin-on method, but not limited to this. The first patterned mask 112 has an opening 120 for defining the position w of the trench opening in the dual damascene 201222724 structure, and the relative positions of the two guide members (10) of the open σ 120 are approximately corresponding, between 1 and 4 and partially overlapping. The two conductive members 102, 104. -, - The patterned mask 112 can be a single layer mask or a multi-structure' and it can comprise a metal material or a non-metal mask. In the preferred embodiment, the first (fourth) mask ιΐ2 Ershi layer shields may include, for example, a multilayer structure of a titanium core, a titanium nitride layer (10) oxide layer n2c, and the like. The manufacturing method is, for example, firstly forming a titanium layer core, a titanium nitride layer, and an oxide layer = U2c to form a mask layer, and then performing a photoresist coating and lithography process to form thereon. A patterned photoresist layer (not shown) is then subjected to a patterning process to effect a pattern transfer to form a first patterned mask 112 in the opening opening f in the mask layer. In addition, depending on the product design and process requirements, a first-patterned mask m and a dielectric layer 11A may be selectively formed with an etch stop layer 114, such as a nitrogen oxide state, for use as a pair- The patterned mask 112 performs a (four) barrier layer during pattern transfer to protect the dielectric layer 110 underneath. Further, if an abnormality occurs in the post-development inspection (ADI) or post-etch inspection (AEI) of the first patterned mask ι 2, the preferred embodiment can be directly performed - weight: !! Step, and since the dielectric layer is provided with a etch stop layer m above, the dielectric layer 11G is completely unaffected by the steps of engraving, cleaning, photoresist removal, and the like after the preparation of the first patterned mask 112 The quality of the dielectric layer is ensured by the rework steps in the case of an abnormality in the inspection (ADI) or post-etch inspection (AEI). 201222724 Then, as shown in FIG. 2 and FIG. 3, a material layer 130 and a second patterned mask 140 are sequentially formed on the surface of the substrate 100, and covered by the first patterned mask 112 and the etch stop layer. 114 is over the dielectric layer 110. The material layer 130 may be a polymer material containing C, lanthanum or lanthanum, such as a carbon-spin on hard mask (C-S0H), but is not limited thereto. The second patterned mask 14 〇 has a first opening 18 〇 for deciding the position of the via hole in the dual damascene structure and the position of the first opening 18 约 is approximately located between the two conductive members One of 1〇2, 1〇4, for example, directly above the conductive member 1〇4. In the preferred embodiment, the second patterned mask 14 can be a multi-layer mask or a single layer mask, such as a single oxide layer. The preparation method is, for example, first forming an oxide compound by chemical vapor deposition as the mask layer 140a, then forming a patterned photoresist layer 15 thereon, and performing an etching process to perform a process. The pattern is transferred to etch the first opening 180 in the mask layer 14〇a to form a second patterned mask 14〇. Depending on the product design and manufacturing requirements, a second protective layer 160, such as tantalum nitride (siN), may be selectively formed between the second patterned mask 14 and the material layer 130 to serve as the second pattern. The mask 140 performs an etch stop layer during pattern transfer to protect the material layer 130 beneath it. The patterned photoresist layer 15 is further selectively opened between the second patterned mask 14 and the first patterned anti-reflective layer (B arc) 170, such as yttrium oxynitride (Si〇N). Wait. 10 201222724 ^ Figure 4 and Figure # 'Continue,' lithography process, Yumeidian 1 ΠΛ t / child product, photoresist coating and _ and: on the order formation - second bottom anti-reverse · patterning Photoresist layer 200, and covering 4 " 14 〇, sheath (10) blood material # μ coated disk in the first patterned mask layer 200 as inverse | ] with patterned photoresist - 16Gt_ material stop layer , to carry out another engraving process for another pattern transfer, to = another position, = two to define the position of the double inlay (10) ^ HM is located approximately in the two conductive members (10), the other - ' Directly above the conductive member 102. It is worth noting that the second opening 22 has a specific spacing from the first, and the special and (5) gamma (4). The preferred embodiment of the present invention can be adapted to the first resist layer. 150, the photoresist layer 2, the two temples only like the thickness of the anti-reflective layer 170 and the first -ml 220 曰夂 0, so that when the first opening 180 and the first self-turning, it is consumed Exhaustion; of course, completely remove the residual photoresist layer (9) and the first bottom: fruit, two 7 〇, photoresist layer 2 〇 0 and second bottom anti-reflection layer 190. In addition, Figure 2 and Figure 5 Steps after the development of the post-development development L or (4) post-test (AEI) anomalies 'this preferred embodiment can be carried out at any time to carry out the required rework steps _ pavilion layer n4' material layer: two = electric layer 110 The top is set up - 射十屠130 and sheath (10), so the dielectric layer 11 〇元王 will not be subjected to the 2nd and 5th drawings of her engraving, cleaning, photoresist removal, etc. 201222724 steps and post-development inspection (ADI) Or the post-etching inspection (ΑΕΙ) is caused by the rework step when an abnormality occurs, and the problem of dielectric constant deterioration (k value degradation) or critical dimension variation occurs, thereby ensuring the quality of the inter-metal dielectric layer and the double damascene pattern. After the post-development inspection (ADI) step confirms that the layout patterns of the first opening 180 and the second opening 220 are correct, then, as shown in FIG. 6, the second patterned mask 140 is etched as an etch mask. The protective layer 160 is configured to transfer the pattern of the first opening 180 and the second opening 220 in the second patterned mask 140 into the sheath 160. Thereafter, as shown in FIG. 7, the second patterned mask 140 is utilized. And the protective layer 160 is used as an etch mask to partially etch the material layer 130, and the etch stop The layer 114 and the dielectric layer 110 continue to transfer the patterns of the first opening 180 and the second opening 220 downward into the material layer 130, the etch stop layer 114, and the dielectric layer 110, and in the dielectric layer 110. Correspondingly, the first through hole 180a and the second through hole 220a are formed correspondingly. Similarly, the preferred embodiment can appropriately adjust the thickness of the second patterned mask 140 and the cover layer 160 and the etching parameters so that the first pass is formed. When the etching process of the hole 180a and the second through hole 220a is exhausted, the cleaning process may be combined with the cleaning process to completely remove the residual second patterned mask 140 and the protective layer 160. Then, as shown in FIG. 8, a stripping process is performed, for example, a gas containing carbon dioxide, carbon monoxide or hydrogen gas is introduced, and the remaining material layer 130 is completely removed to expose the first pattern 12 having the pattern of the opening 120. 201222724 has the first The contact r μ of the pattern of the through hole 18〇3 and the second through hole 220a, as shown in FIG. 9 , uses the first patterned mask 112 and the etching: the stop layer m is used as the I insect mask to engrave the dielectric The layer 11〇 and the cap layer 1〇8 continue to be transferred downward into the dielectric ίο in the pattern of the opening 120, and at the same time, the pattern of the first via hole and the second via hole 22〇a is further transferred downward to the middle layer. The process of exposing the conductive member 1〇4 and the 丨 dual damascene pattern 250 to the cap layer 108 t′, respectively. 'Dry~ is the first patterned mask m of the preferred embodiment is a multi-layer stack mask' which includes a titanium layer core and a titanium nitride layer 112b, etc., which has a different etch rate than the dielectric layer UG, the cover The layer (10) and the etch stop layer 114 have a mask material and a relatively high (four) selection ratio. Therefore, when the process of the dual damascene pattern 250 is completed, the oxide layer of the first patterned mask ι 2
Uc會消耗殆盡，而基底1〇〇上僅會留存鈦層及氛化 鈦層112b。 接續再於雙職㈣25G中填滿導電㈣，使其電連接 於導電件104與1〇2，形成雙鎮嵌結構。例如先利用化學氣 相沈積(CVD)或物理氣相沈積(pvmf鑛製程依序形成一 阻障層26Q及—晶種層（圖未示），然後再電卿成一銅金屬 層280。其中，阻障層可由鈕(Ta)、氮化鈕(tamalum，TaN)、 13 201222724 鈦(Ti)、或氮化鈦(TiN)等不同組合所組成之複合式擴散隊^ 28〇 最後存 層’具有雙層或三層式疊層結構，用以防止銅金屬廣 銅離子向外遷移（migration)而擴散出介電層110中 進行一平坦化製程，去除雙鑲嵌圖案250之外的導電讨科 並同時移除殘存鈦層112a及氮化鈦層112b，直炱蝕刻 層Π4或介電層11〇的頂面，如第1〇圖所示。此皆爲 相關技藝者與通常知識者所熟知，故在此不多加賛述 上述之較佳實施例主要是以部分通孔優先 (partial-via-first)製程，但本發明亦可整合於溝渠優先 (trench-first)製程、通孔優先(via-first)製程、以及自4 (self-aligned)製程等雙鑲嵌製程中。 综上所述，本較佳實施例可隨時進行所需進行的重The Uc is depleted, and only the titanium layer and the titanium oxide layer 112b remain on the substrate. The connection is then filled with the conductive (4) in the dual-function (4) 25G, which is electrically connected to the conductive members 104 and 1〇2 to form a double-town embedded structure. For example, a barrier layer 26Q and a seed layer (not shown) are sequentially formed by chemical vapor deposition (CVD) or physical vapor deposition (pvmf process), and then a copper metal layer 280 is formed. The barrier layer may be a composite diffusion layer composed of a button (Ta), a nitride button (tamalum, TaN), 13 201222724 titanium (Ti), or titanium nitride (TiN), etc. a double-layer or three-layer laminated structure for preventing copper metal ions from migrating outwardly and diffusing out of the dielectric layer 110 for a planarization process, and removing the conductive discussion outside the dual damascene pattern 250 At the same time, the remaining titanium layer 112a and the titanium nitride layer 112b are removed, and the top surface of the etch layer 4 or the dielectric layer 11 is directly etched, as shown in FIG. 1 , which is well known to those skilled in the art. Therefore, it is not mentioned here that the preferred embodiment described above is mainly a partial-via-first process, but the present invention can also be integrated into a trench-first process and a via-first (via). -first) process, and dual damascene processes such as 4 (self-aligned) process. In summary, this The preferred embodiment can perform the required weight at any time
0 IΊ承刻 驟’且由於預定形成雙鑲嵌圖案的介電層上方設置項 ^ “丨镇1 止層、材料層與護層等，因此介電層完全不會受到$ 第5圖所述的蝕刻、清潔、去光阻等步驟以及顯影後檢而發 (ADI)或蝕刻後檢驗(AEI)發生異常時的重工步驟戶/t # ^ 生介電常數劣化或關鍵尺寸變異等問題，進而玎於弟 化遮罩及第二圖案化遮罩及護層中分別形成品質良奸’ & 口、第一開孔與第二開孔的佈局圖案。最後再伴隨後續白’ 刻製程一齊轉移至介電層中，故能有效避免發生介電常數劣 化(k value degradation)或關鍵尺寸變異（CD variation)等問 14 201222724 圖案的品質與製程良 通’大巾田而金屬層間介電層與雙镶私 率。 實施例，凡依本發明申請專 皆應屬本發明之涵蓋範圍。 以上所述僅為本發明之較佳 利範圍所做之均等變化與修飾， 【圖式簡單說明】 第1圖至第10圖為本發明之雙鑲嵌製程的示意圖。 【主要元件符號說明】 100 基底 106 絕緣材料層 110 介電層 112a 鈦層 112c 氧化物層 120 開口 140 第二圖案化遮罩 150、 20〇光阻層 170 第一底抗反射層 190 第一底抗反射層 180a 第一通孔 250 雙鑲嵌圖案 28Q. 鋼金屬層 102 、 1〇4 導電件 108 蓋層 112 第一圖案化遮罩 112b 氮化鈦層 114 蝕刻停止層 130 材料層 140a 遮罩層 160 護層 180 第一開孔 220 第二開孔 220a 第二通孔 260 阻障層 15The dielectric layer is completely unaffected by the first layer of the dielectric layer that is intended to form the dual damascene pattern, such as the "stop layer, the material layer and the cladding layer, etc." Etching, cleaning, photoresist removal, etc., and rework steps when an abnormality occurs after the development (ADI) or post-etch inspection (AEI) occurs, and the problem of deterioration of the dielectric constant or critical dimension variation is caused. In the younger mask and the second patterned mask and the protective layer, a layout pattern of the quality of the ''ample', the first opening and the second opening is formed respectively. Finally, the subsequent whitening process is transferred to the subsequent whitening process. In the dielectric layer, it is effective to avoid the occurrence of dielectric constant degradation (k value degradation) or critical size variation (CD variation). 14 201222724 Pattern quality and process Liangtong 'Dai Tengtian and metal interlayer dielectric layer and double The present invention is intended to be within the scope of the present invention. The above description is only the equivalent variation and modification of the preferred range of the present invention, [Simplified Description] Figure to Figure 10 is a double of the present invention Schematic diagram of the embedded process. [Main component symbol description] 100 substrate 106 insulating material layer 110 dielectric layer 112a titanium layer 112c oxide layer 120 opening 140 second patterned mask 150, 20 〇 photoresist layer 170 first bottom anti-reflection Layer 190 first bottom anti-reflection layer 180a first through hole 250 dual damascene pattern 28Q. steel metal layer 102, 1 〇 4 conductive member 108 cap layer 112 first patterned mask 112b titanium nitride layer 114 etch stop layer 130 material Layer 140a mask layer 160 sheath 180 first opening 220 second opening 220a second through hole 260 barrier layer 15