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TW201227899A - Substrate strip with thinned plating layer at mold gate - Google Patents

Substrate strip with thinned plating layer at mold gate Download PDF

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Publication number
TW201227899A
TW201227899A TW99146435A TW99146435A TW201227899A TW 201227899 A TW201227899 A TW 201227899A TW 99146435 A TW99146435 A TW 99146435A TW 99146435 A TW99146435 A TW 99146435A TW 201227899 A TW201227899 A TW 201227899A
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Taiwan
Prior art keywords
layer
plating
substrate strip
substrate
metal layer
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TW99146435A
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Chinese (zh)
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TWI416687B (en
Inventor
Wen-Jeng Fan
Tsai-Chuan Yu
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Powertech Technology Inc
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Priority to TW99146435A priority Critical patent/TWI416687B/en
Publication of TW201227899A publication Critical patent/TW201227899A/en
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Publication of TWI416687B publication Critical patent/TWI416687B/en

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Abstract

Disclosed is a substrate strip with thinned plating layer at mold gate. A winding plating line, for example a wire frame having wavy winding, is disposed on a molding surface of the substrate body and connected with a mold gate metal layer disposed on the same surface. A pattern metal layer including connecting pads is disposed on another surface of the substrate body. The thickness of the plating layer on the mold gate metal layer is smaller than the thickness of the plating layer on the connecting pads OF the pattern metal layer by plating through the winding plating line. Accordingly, there can be thinned thickness of plating layer on the mold gate metal layer but still kept enough thickness of plating layer on package active area to reduce cost.

Description

201227899 六、發明說明: 【發明所屬之技術領域】 • 纟發明係有關於半導體封裝裝置之部件,特別係有關 於一種薄化注澆口表面電鍍層之基板條結構。 【先前技術】 按,基板條常運用於大量生產半導體封裝製程作為 晶片載板。以往在製作基板條的線路時,除了在基板條 之植球面形成有用以電性連接之線路之外,亦會在基板 •條之模封面形成與注洗口對應之金屬層,以便於在:封 作業之後分離基板條與注逢口之外的的廢膠體,有助於 脫模動作之進行。一般而言,在基板條之線路與注淹口 金屬層製作完成之後,會再於基板條兩表面上各形成— 防銲層(solder mask),以覆蓋線路與電鍍線,但顯露出 位於植球面之線路層之接墊與位於模封面之注澆口金屬 層。其中,線路層之接墊與注澆口金屬層皆以所需的電 φ鍍線連接,可提供一電位,以對接墊與注澆口金屬層進 行電鍍製程。然而,由於注澆口金屬層與其連接之電鍍 層皆不屬於半導體封裝構造之内部元件,而是僅為了脫 模動作能夠順利進行而設置。因此,形成於注澆口金屬 層上之電鍍層厚度為影響電鑛製程之成本因素之一。 如美國專利編號US 6,861,764 B2號「WIRING SUBSTRATE HAVING POSITION INFORMATION」,揭示 一種習知基板條,以無電鍍銅方式形成一導電層,使得 該導電層能彼覆於基板條之上下表面。接著,經曝光顯 201227899 影製程’以濕蝕刻方式圖案化該導電層以形成包含電鍍 線之線路結構,該線路結構另包含用以連接銲球之= 墊。再覆蓋防銲層於導電層之上,並圖案化該防銲層以 顯露出部分之導電層,其中顯露之部分包含了位在不同 表面之接墊與注澆口金屬層’注澆口金屬層位於基板條 之一侧邊並在由複數個基板單元所構成之模封區域之 卜之後以電鍍方式形成一鎳金層(即電鍍層),使其 形成於接墊與注澆口金屬層上,藉由鎳金層之設置可防 止由銅材質之導電層的顯露表面發生氧化,亦可增加銲 接時的接合強度。然而,在同一電鑛步驟中在注濟口金 屬層上之錄金層與在接塾上之錄金層通常具有相同之厚 度’在注澆口金屬層上之鎳金層在封膠完成後皆會被 為廢料而被切除。因此,若能控制形成於注燒口金屬層 上之鎳金層的厚度,將可有效降低成本。 g 【發明内容】 有鑒於此,本發明之主要目的係在於提供一種 % D 主 U ^ 上 面電鍍層之基板條結構,可薄化於注澆口金屬層 ^電錄層厚度,但仍保持封裝件主動區上之電: 夠的厚度,從而降低基板條成本。 本發明之次一目的係在於提供一種薄化注澆口表面 鍍層之基板條結構,使得注澆口金屬層上之電鍍 度向内遞減。 终 案本發明的目的及解決其技術問題是採用以下技術方 、來實現的。本發明揭示一種薄化注澆口表面電鍍層之 .Γ 201227899 基板條結構’主要包含一基板條本體、一注澆口金屬層、 一圖案化金屬層、一曲折電鍍線、一第一電鍍層以及一 第二電鍍層。該基板條本體内係形成有複數個一體構成 且呈矩陣排列之基板單元。該注澆口金屬層係設於該基 板條本體之一第一表面上。該圖案化金屬層係設於該基 板條本體之一第二表面上,該圖案化金屬層係包含有複 數個電鍍線匯流排、複數個電鍍導線與複數個接墊,其 中該些電鍍線匯流排係設置於該些基板單元之外,而該 些電鍍導線與該些接墊係設置於該些基板單元内,並且 藉由該些電鍍導線電性連接該些電鍍線匯流排至該些接 墊。該曲折電鍍線係設於該基板條本體之該第一表面上 並連接至該注澆口金屬層。該第一電鍍層係形成於該注 澆口金屬層上。該第二電鍍層係形成於該些接墊上,藉 由該曲折電鍍線使該第一電鍍層之厚度係小於該第二電 鍍層之厚度。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的薄化注澆口表面電鍍層之基板條結構中,該 第一電鍵層與該第二電鍵層係可由同一電鍍製程所形 成。 在前述的薄化注澆口表面電鍍層之基板條結構中,該 曲折電錄線係可位於該些基板單元與該注澆口金屬層之 間。 9 在前述的薄化注洗口表面電鍍層之基板條結構中,該 5 201227899 曲折電鍍線係可為一波形曲折之電鍍線框,並圍繞在該 些基板單元之外。 在前述的薄化注澆口表面電鍍層之基板條結構中,該 曲折電鍍線係可藉由複數個等距排列之短導線並聯至該 注澆口金屬層。 在前述的薄化注澆口表面電鍍層之基板條結構中,可 另包含有一第一防銲層,係形成於該基板條本體之該第 一表面上’以覆蓋該曲折電鍍線但顯露該注澆口金屬層。 在前述的薄化注澆口表面電鍍層之基板條結構中,可 另包含有一第二防銲層’係形成於該基板條本體之該第 一表面上’以覆蓋該些電鍍線匯流排與該些電鍍導線但 顯露該些接墊。 在刚述的薄化注澆口表面電鍍層之基板條結構中,該 第防銲層係可具有-開孔’以顯露該第-表面在該些 基板單元内之部位。201227899 VI. Description of the Invention: [Technical Field of the Invention] The invention relates to a component of a semiconductor package device, and more particularly to a substrate strip structure for thinning a surface of a gate. [Prior Art] According to the substrate strip, the substrate strip is often used for mass production of a semiconductor package process as a wafer carrier. In the past, when the circuit of the substrate strip was fabricated, in addition to forming a circuit for electrically connecting the ball-forming surface of the substrate strip, a metal layer corresponding to the filling port was formed on the cover of the substrate and the strip to facilitate: After the sealing operation, the separation of the substrate strip and the waste colloid other than the filling opening facilitates the demolding operation. Generally, after the circuit of the substrate strip and the metal layer of the flood-filling layer are completed, a solder mask is formed on both surfaces of the substrate strip to cover the wiring and the plating line, but the substrate is exposed. The pad of the spherical circuit layer and the metal layer of the gate of the mold cover. Wherein, the pad of the circuit layer and the metal layer of the gate are connected by a required electric φ plating line, and a potential is provided to perform an electroplating process on the butt pad and the gate metal layer. However, since the gate metal layer and the plating layer to which it is connected are not part of the internal components of the semiconductor package structure, they are provided only for the smooth release operation. Therefore, the thickness of the plating layer formed on the gate metal layer is one of the cost factors affecting the electric ore processing. For example, U.S. Patent No. 6,861,764 B2, "WIRING SUBSTRATE HAVING POSITION INFORMATION", discloses a conventional substrate strip in which a conductive layer is formed by electroless copper plating so that the conductive layer can cover the lower surface of the substrate strip. Next, the conductive layer is patterned by wet etching through exposure to form a wiring structure including a plating line, and the wiring structure further includes a pad for connecting the solder balls. The solder resist layer is overlaid on the conductive layer, and the solder resist layer is patterned to expose a portion of the conductive layer, wherein the exposed portion includes the pads on the different surfaces and the gate metal layer 'gate metal The layer is located on one side of the substrate strip and is formed by electroplating to form a nickel-gold layer (ie, a plating layer) on the side of the substrate strip formed by the plurality of substrate units, so as to be formed on the pad and the gate metal layer. Further, by the arrangement of the nickel-gold layer, oxidation of the exposed surface of the conductive layer made of copper can be prevented, and the bonding strength at the time of soldering can be increased. However, in the same electric ore step, the gold layer on the metal layer of the metallization is generally the same thickness as the gold layer on the joint. The nickel-gold layer on the metal layer of the gate is after the sealing is completed. They will all be cut off for scrap. Therefore, if the thickness of the nickel gold layer formed on the metal layer of the burner is controlled, the cost can be effectively reduced. g SUMMARY OF THE INVENTION In view of the above, the main object of the present invention is to provide a substrate strip structure of a % D main U ^ upper plating layer, which can be thinned to the gate metal layer and the thickness of the electro-recording layer, but still maintain the package. The electricity on the active area: sufficient thickness to reduce the cost of the substrate strip. A second object of the present invention is to provide a substrate strip structure for thinning the surface of a gate, such that the degree of plating on the gate metal layer decreases inwardly. The object of the present invention and solving the technical problems thereof are achieved by the following techniques. The invention discloses a thinned gate surface plating layer. Γ 201227899 The substrate strip structure 'mainly comprises a substrate strip body, a gate metal layer, a patterned metal layer, a zigzag plating line, a first plating layer And a second plating layer. The substrate strip body is formed with a plurality of substrate units integrally formed and arranged in a matrix. The gate metal layer is disposed on a first surface of the substrate strip body. The patterned metal layer is disposed on a second surface of the substrate strip body, and the patterned metal layer comprises a plurality of electroplated wire bus bars, a plurality of plated wires and a plurality of pads, wherein the plated wires are converged The galvanic wires are disposed outside the substrate units, and the plating wires and the pads are disposed in the substrate units, and the plating wires are electrically connected to the wires by the plating wires. pad. The zigzag plating line is disposed on the first surface of the substrate strip body and connected to the gate metal layer. The first plating layer is formed on the gate metal layer. The second plating layer is formed on the pads, and the thickness of the first plating layer is smaller than the thickness of the second plating layer by the zigzag plating line. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing substrate strip structure for thinning the gate surface plating layer, the first electric key layer and the second electric key layer may be formed by the same electroplating process. In the foregoing substrate strip structure for thinning the gate surface plating layer, the zigzag electric recording line may be located between the substrate unit and the gate metal layer. 9 In the foregoing substrate strip structure for thinning the surface of the surface of the nozzle, the 5 201227899 zigzag plating line may be a zigzag-plated wire frame and surround the substrate units. In the foregoing substrate strip structure for thinning the gate surface plating layer, the zigzag plating line may be connected in parallel to the gate metal layer by a plurality of equidistantly arranged short wires. In the foregoing substrate strip structure for thinning the gate surface plating layer, a first solder resist layer may be further formed on the first surface of the substrate strip body to cover the zigzag plating line but revealing the Note the gate metal layer. In the foregoing substrate strip structure for thinning the gate surface plating layer, a second solder resist layer may be further formed on the first surface of the substrate strip body to cover the plating line bus bar and The electroplated wires are exposed but the pads are exposed. In the substrate strip structure of the thinned gate surface plating layer just described, the first solder resist layer may have an opening to expose a portion of the first surface within the substrate unit.

由JsA上^^ 案可以看出,本發明之薄化注洗口表面 電鑛層之基板條結構,具有以下優點與功效: 由於曲折電鍍線之 可藉由將曲折電鍍線連接至注澆口金屬層之特定組 合關係作為其中之-枯浙丰贤 長度較長, 金屬層之第 之接墊之第 所以可藉由曲折電鍍線使形成於注洗口 —電錄層厚度小於形成於圖案化金屬層 —電鑛層厚度。因此,可薄化於注洗口 金屬層上之電鍍層厚度但仍保持封裝件主動區上 之電鍵層有足备&广 疋夠的厚度,從而降低基板條成本β 201227899 二、可藉由曲折電鍍線之特定組合關係作為其中之一技 術手段,由於曲折電鍍線係可位於基板單元與注澆 口金屬層之間’進而減少通過曲折電锻線之電流 量,故可使注澆口金屬層上之電鍍層厚度向内遞減。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例,然應 注意的是,該些圖示均為簡化之示意圖,僅以示意方法 來說明本發明之基本架構或實施方法,故僅顯示與本案 有關之7L件與組合關係,圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例 與/、他相關尺寸比例或已誇張或是簡化處理,以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計,詳細之元件佈局可能更為複雜。 依據本發明之一具體實施例,一種薄化注澆口表面電 鍍層之基板條結構舉例說明於第1圖繪示其第一表面之 示意圖、第2圖繪示其第一表面之局部放大示意 圖第3圖綠示其第二表面之局部放大示意圖以及第々a 至c圖之局部截面示意圖。該薄化注澆口表面電鑛層 板條、、Ό構1 〇 〇係主要包含一基板條本體11 〇、一注 /堯金屬層120、一圖案化金屬層130、一曲折電鑛線 140 第—電鑛層1 50與一第二電鍵層1 6〇。 叫參閱第1圖所示,該基板條本體11〇内係形成有複 數個—體構成且呈矩陣排列之基板單元丨丨丨,該些基板 單元111係為保留於半導體封裝構造内的基板部位,用 201227899It can be seen from the JSA case that the substrate strip structure of the thinned injection surface electro-chemical layer of the present invention has the following advantages and effects: Since the zigzag plating line can be connected to the gate by bending the zigzag plating line The specific combination relationship of the metal layer is one of them - the length of the dry Zhejiang Fengxian is long, and the first layer of the metal layer can be formed on the injection port by the zigzag electroplating line - the thickness of the lithography layer is smaller than that formed in the patterning Metal layer - thickness of the electric ore layer. Therefore, the thickness of the plating layer on the metal layer of the nozzle can be thinned while still maintaining the thickness of the key layer on the active area of the package, thereby reducing the cost of the substrate strip β 201227899 As a technical means of the special combination relationship of the zigzag electroplating line, since the zigzag electroplating line can be located between the substrate unit and the gate metal layer, thereby reducing the amount of current passing through the meandering electric forging line, the gate metal can be made. The thickness of the plating on the layer decreases inward. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the 7L parts and combinations related to the case are displayed. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios and/or their related size ratios are exaggerated or Simplify the process to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to an embodiment of the present invention, a substrate strip structure for thinning a gate surface plating layer is illustrated in FIG. 1 and a partial enlarged view of the first surface thereof. Fig. 3 is a partially enlarged schematic view showing a second surface thereof and a partial cross-sectional view of the second to cth views. The thinned gate surface electro-metal layer slab, and the Ό1 〇〇 system mainly comprises a substrate strip body 11 〇, a 尧/尧 metal layer 120, a patterned metal layer 130, and a zigzag electric ore line 140. The first electric layer 1 50 and the second electric layer 16 6 . Referring to FIG. 1 , the substrate strip body 11 is formed with a plurality of substrate units 构成 arranged in a matrix, and the substrate units 111 are substrate portions remaining in the semiconductor package structure. With 201227899

以承載與電性連接晶片。該些基板單it 111 t間係定義 出複數個縱交錯的切割道(如圖中虛線所示),並在模 封之後y依據該些切割道切割該基板條本體11 〇,依該 二基板單疋U1的大小分離成各式半導體封裝構造。詳 細而5,如第4 A至4C圖所示,該基板條本體i i 〇係具 有第表面與一第二表面113,並且該第一表面 〃該第—表面丨13係為該基板條本體兩相對應 之表面其中,該第—表面112係作為提供予封膠體形 成之模封表面’而該第二表φ 113係作為對外電性連接 之植球面。在一較佳實施例中,該基板條本體110之材 料係可選用高分子樹脂材料,例如:FR_4環氧樹脂(fr_4 e^poxy)。或者,為了適合特殊應用需求,亦可選用其它 咼性能的樹脂材料,例如:聚亞醯胺(ρι)樹脂、三氮雜 苯雙馬來醯亞胺(BT)樹脂。此外,該基板條本體ιι〇係 可另具有複數個中央槽孔114,其係對準在該些基板單 元"…央部位’並且該些中央槽孔係由該第一表面 "2貫穿至該第二表面113’用以作為打線連接之通道, 以適用於窗口型球格陣列封裝。 請參閱第h 2、4八及4B圖所示,該注洗口金屬 120係設於該基板條本體之該第一表面112上。 注淹口金屬層12G的材質可為鋼。在—較佳實施例中 該注涛口金屬们20係、配置於該基板條本體ιι〇預定 行注繞作業之-侧邊’通常是在該些基板單元⑴ 外,並且具有不被防銲層覆蓋之表面,該表面更形成 8 201227899 厚度為HI之該第一電鍍層150。待在上下模具合模之後 可對應至模具注澆口之位置,故在注澆作業完成後可藉 由該注澆口金屬層120及其表面的該第一電鍍層15〇之 設置,可防止封膠體全面黏固於該基板條本體110之側 邊’而有助於脫模作業之進行。更具體地,如第4A與 4B圖所示’該薄化注澆口表面電鍍層之基板條結構1 〇〇 係可另包含有一第一防銲層171,係形成於該基板條本 體110之該第一表面Π2上’以覆蓋該曲折電鑛線140 鲁但顯露該注澆口金屬層120,故可防止該第一電鍍層ι5〇 形成於該曲折電鍍線丨4〇,更能夠限制該注澆口金屬層 120之被電鍍區域,進而免除不必要之電鍍材料浪費。 此外’該第一防銲層m係可具有一開孔173,以顯露 該第一表面112在該些基板單元111内之部位(如第1圖 所示)’而藉由該開孔1 73之設置’更能夠增加該些基板 單元111與模封膠體之間的结合力。 • 再如第4C圖所示,該第二電鍍層160係形成於該圖 案化金屬層130之接墊133上。請參閱第3圖所示,其 繪示出該基板條本體11〇之^一第二表面113,以完整呈 現該圖案化金屬層丨30於該第二表面113上之配置情 形故上述第二電鍍層省略而未顯示於第3圖中。由第 3圖並對照第4C圖可知,該圖案化金屬層1 3〇係設於該 基板條本體u〇之該第二表面n3上,也就是說,該圖 案化金屬層130與該注澆口金屬層120係配置於該基板 條本體110之不同表面。丨中,該圖案化金屬130係 201227899 包含有複數個電鍛線匯流排131、複數個電鑛導線132 與複數個接墊133,表示上述所列元件是屬於相同材質 的同一層線路結構。其中該些電鍍線匯流排丨3 !係設置 於該些基板單元111之外,例如:本實施例中,該些電 鍍線匯流排131位於該基板條本體在該些基板單元Ui 之間之切割道内;在不同實施例中,電鍵線匯流排亦可 設置於貫穿該些中央槽孔114之位置。該些電鍍線匯流 排1 3 1之型態除了直線也可以是波形曲折或「之」形曲 鲁折。而該些電鍍導線132與該些接墊133係設置於該些 基板單元111内’並且該些電鍍導線132更延伸連接至 該些電鍍線匯流排1 3 1,藉由該些電鑛導線1 3 2電性連 接該些電鍵線匯流排1 3 1至該些接墊1 3 3。故該些電鍵 線匯流排1 3 1係作為電鑛接整時的主要導線,用以傳遞 電流至該些基板單元11 1内,並且經由該些電鍍導線1 3 2 將電流導通至該些接墊丨3 3。在一較佳型態中,如第4C φ 圖所示’在該基板條本體110上形成該圖案化金屬層130 之後’可另形成一第二防銲層172於該第二表面113上, 以覆蓋該些電鍍線匯流排1 3 1與該些電鍍導線1 3 2,並 且該第二防銲層i 72係具有複數個開口,用以顯露出該 些接墊133。因此,藉由該第二防銲層丨72之設置,可 防止該第二電鍍層16〇形成於該些電鍍線匯流排131與 該些電鍍導線132上,進而降低製造成本《其中,該第 二防鮮層1 7 2之開口係可小於該些接墊1 3 3,使該些接 墊 133 為銲罩界定墊(s〇lder mask defined,SMd)。或者, 10 201227899 墊133,使該 mask defined, 該第二防銲層172之開口亦可大於該些接 些接墊133係為非銲罩界定墊(n〇n_s〇ider SMD)。To carry and electrically connect the wafer. The substrate sheets define a plurality of longitudinally scribed scribe lines (shown by broken lines in the figure), and after molding, y cut the substrate strip body 11 according to the dicing lines, according to the two substrates The size of the single turn U1 is separated into various semiconductor package configurations. In detail, as shown in FIGS. 4A to 4C, the substrate strip body ii has a first surface and a second surface 113, and the first surface 〃 the first surface 丨 13 is the substrate strip body Corresponding surfaces, wherein the first surface 112 serves as a molding surface for providing a sealant and the second surface φ 113 serves as a spherical surface for external electrical connection. In a preferred embodiment, the material of the substrate strip body 110 may be a polymer resin material such as FR_4 epoxy resin (fr_4 e^poxy). Alternatively, in order to suit the needs of a particular application, other resin materials of bismuth properties such as polyamidoline (ρι) resin, triazapine bismuthimide (BT) resin may also be used. In addition, the substrate strip body ιι can further have a plurality of central slots 114 aligned with the central portion of the substrate unit and the central slots are penetrated by the first surface " The second surface 113' is used as a channel for wire bonding to be applied to a window type ball grid array package. Referring to Figures h 2, 4 and 4B, the sprue metal 120 is disposed on the first surface 112 of the substrate strip body. The material of the flooded metal layer 12G may be steel. In the preferred embodiment, the metallurgical metal 20 series, disposed on the side of the substrate strip body ι 〇 predetermined winding operation, is generally outside the substrate unit (1) and has no solder resist The surface of the layer covering, the surface further forming the first plating layer 150 having a thickness of HI 201227899. After the upper and lower molds are clamped, the position corresponding to the mold gate can be corresponding, so that after the pouring operation is completed, the gate metal layer 120 and the surface of the first plating layer 15 can be prevented. The encapsulant is fully adhered to the side of the substrate strip body 110 to facilitate the demolding operation. More specifically, as shown in FIGS. 4A and 4B, the substrate strip structure 1 of the thinned gate surface plating layer may further include a first solder resist layer 171 formed on the substrate strip body 110. The first surface Π2 is formed to cover the gate metal layer 120 to cover the gate metal layer 120, so that the first plating layer ι5〇 can be prevented from being formed on the meandering plating line 〇4〇, and the limitation can be further restricted. The plated area of the gate metal layer 120 is injected, thereby eliminating unnecessary waste of plating material. In addition, the first solder resist layer m may have an opening 173 to expose a portion of the first surface 112 in the substrate unit 111 (as shown in FIG. 1), and the opening 1 73 The setting 'is more able to increase the bonding force between the substrate unit 111 and the molding compound. • As shown in Fig. 4C, the second plating layer 160 is formed on the pads 133 of the patterned metal layer 130. Referring to FIG. 3, the second surface 113 of the substrate strip body 11 is shown to completely present the arrangement of the patterned metal layer 30 on the second surface 113. The plating layer is omitted and is not shown in FIG. It can be seen from FIG. 3 and FIG. 4C that the patterned metal layer 13 is disposed on the second surface n3 of the substrate strip body u, that is, the patterned metal layer 130 and the pouring The metallization layer 120 is disposed on different surfaces of the substrate strip body 110. In the case, the patterned metal 130 system 201227899 includes a plurality of electric forging wire bus bars 131, a plurality of electric ore wires 132 and a plurality of pads 133, indicating that the elements listed above are of the same layer structure belonging to the same material. The plating line bus bar !3 is disposed outside the substrate unit 111. For example, in the embodiment, the plating wire bus bars 131 are located between the substrate strip body and the substrate unit Ui. In the different embodiments, the electric wire line busbars may also be disposed at positions penetrating the central slots 114. The pattern of the electroplated wire busbars 1 3 1 may be a zigzag or a zigzag curve in addition to a straight line. The plating wires 132 and the pads 133 are disposed in the substrate units 111 and the plating wires 132 are further extended to the plating wire bus bars 1 3 1 by the electric ore wires 1 3 2 electrically connect the plurality of key line bus bars 1 3 1 to the pads 1 3 3 . Therefore, the plurality of key line busbars 1 3 1 are used as main conductors for electric ore finishing, for transferring current to the substrate units 11 1 , and conducting current to the plurality of vias through the plating wires 1 3 2 Pad 3 3 . In a preferred embodiment, a second solder resist layer 172 may be additionally formed on the second surface 113 after the patterned metal layer 130 is formed on the substrate strip body 110 as shown in FIG. 4C φ. The plating wire busbars 133 and the plated wires 1 32 are covered, and the second solder resist layer i 72 has a plurality of openings for exposing the pads 133. Therefore, by the arrangement of the second solder resist layer 72, the second plating layer 16 is prevented from being formed on the plating line bus bar 131 and the plating wires 132, thereby reducing the manufacturing cost. The opening of the second anti-fresh layer 172 may be smaller than the pads 133, such that the pads 133 are sweller pads defined (SMd). Alternatively, 10 201227899 pad 133, the pad is defined, and the opening of the second solder resist layer 172 may be larger than the plurality of pads 133 as non-weld masking pads (n〇n_s〇ider SMD).

請再參閱第}與2圖所示,該曲折電鐘線i4〇係設於 該基板條本體110之該第一表面112上並連接至該注繞 口金屬層12G。其中’該曲折電錄線14()係可藉由複數 個等距排列之短導線並聯至該注濟口金屬層12〇。 通常該些短導、線141係配置於每一注繞口之位置。而該 曲折電鍍、線為反覆彎φ,在—固定距離下比起習知 直線形電鑛線的線長更長,可達到兩倍以上進而增加 了本身之電阻值,故可減少電鍍時所流入的電流量。詳 細而言’該曲折電鑛線14G係可作為電料用以傳遞電 流至該注澆口金屬層12〇之主要導線。在一較佳型態 中’該曲折電鍍線14G係可為—波形曲折之f鍍線框: 並圍繞在該些基板單元U1之外。尤佳地,波形曲折的 方式為方形波,在每一波峰與波谷各提供兩個直角彎 折藉以產生寄生效應,進而干擾與延遲電流。在一具 體型態中’該曲折電鍵線14G亦可變更為梳狀或鑛齒狀 之曲折型態。在電鍍製程中’由外部導線將電流經由該 基板條本體ι1〇之接點導入至該基板條本體11〇内部 時,由於該曲折電鍍線140係可位於該些基板單元m 與m堯口金屬層12〇之間’並且該曲折電鑛線14〇具 有較大的電阻值,使得所導入之電流較不易往電阻值較 大之該曲折電鍍線140流通,進而減少通過該曲折電鍍 201227899 線140之電流量。因此,可使形成於該注洗口金屬層I]。 上之電鐘層厚度向内朝向基板單元方向遞減,即可省去 在注濟口非主要功能區的電鍍層厚度。 請參閱第4A至4C圖所示,該第一電鍍層15〇係形 成於該'主澆口金屬層120上,並且該第二電鍍層160係 形成於該些接# 133 ±。如上所述’由於該曲折電鍍線 140之長度加長,而大幅地增加本身之電阻值,所以在 電鍍時所流入該曲折電鍍線14〇之電流量會較低於流入 該圖案化電鑛層之電流量。根據電解定律、電化當量以 及電流效率公式,可以導出電鑛層之厚度與電流密度係 為正比關係,其中「電流密度」係指通過單位面積的電 流量。所以,如果在單位面積相同之條件下,流入的電 流量越大,則所形成電鍍層之厚度也越大。因此,藉由 該曲折電鍍線1 40能使該第一電鍍層150之厚度H1 (如 第 圖所示)係小於該第二電鑛層160之厚度Η2(如第 4C圖所示)。故而該第一電鍍層15〇與該第二電鍍層16〇 在同—電鍍製程中形成’其中’該基板條結構1〇〇在單 體化分離之前係多個一體配置於一基板面板 panel)(圖中未繪出)中,為矩陣排列,進而使故除了可簡 化電鍍製程之外,更能縮短電鍍製程之時間。 綜上可知,本發明藉由將該曲折電鍍線140連接至該 注澆口金屬層120之特定組合關係作為其中之_技術手 段,由於該曲折電鍍線14〇之曲折型態而使其本身長度 增加’所以可利用該曲折電I線⑷使形成於該注洗口 12 201227899 金屬層120之該第一電鍍層15〇之厚度hi小於形成於 該圖案化金屬層13〇之該些接墊133之該第二電鍍層 16〇之厚度H2。因此,可薄化於該注澆口金屬層12〇上 之電鍍層厚度,但仍保持封裝件主動區上之電鍍層有足 夠的厚度’從而降低基板條成本。 以上所述,僅是本發明的較佳實施例而已,並非對本 發明作任何形式上的限制,雖然本發明已以較佳實施例 揭露如_L然:而並非用以限定本發明,任何熟悉本項技 術者,在不脫離本發明之技術範圍内,所作的任何簡單 修改、等效性變化與修#,均仍屬⑨本發明的技術範圍 内。 【圖式簡單說明】 第1圖·依據本發明之一具體實施例的一種薄化注澆口 表面電鍍層之基板條結構之第一表自之上視示 意圖。 第2圖:依據本發明 伞赞月之具體實施例的薄化注澆口表面 電鑛層之基板條結構之第—表面之局部放大示 意圖。 第3圖:依據本發明 發月之*體實施例的薄化注洗口表面 電鍍層之基板條結構 心弟一表面之局部放大示 意圖。 第4A至4C圖:依據本發明之— 具體貫施例的薄化注澆 口表面電鍍層之基板# 株、、口構之局部截面示意 ’其中(A)為注洗口全麗通沾 贪屬層的局部剖切,(B) 201227899 為曲折電鍍線的局部剖切,(c)為多個接墊的局 部剖切。 【主要元件符號說明】 100 薄 化 注 洗 口表1 S電鍍層之基板條結構 110 基板條 本 體 111 基 板 單 元 112 第一 表面 113 114 中 央 槽 孔 120 注 洗 口 金 屬層 130 圖 案 化 金 屬層 131 電 鍍 線 匯 流排 132 電鍍 導線 133 140 曲 折 電 鍍 線 141 短 導 線 150 第 一 電 鍍 層 160 第二 電鍍層 171 第 一 防 銲 層 172 第二 防銲層 173 第二表面 接墊 開孔 H1 第一電鍍層厚度 H2 第二電鍍層厚度 14Referring to FIGS. 1 and 2, the zigzag clock line i4 is disposed on the first surface 112 of the substrate strip body 110 and connected to the wrap metal layer 12G. Wherein the zigzag electric recording line 14() can be connected in parallel to the metallization layer 12〇 by a plurality of equidistantly arranged short wires. Usually, the short guide wires 141 are disposed at the position of each of the injection ports. The zigzag plating and the line are reverse bending φ, which is longer than the line length of the conventional linear electric ore line at a fixed distance, and can be doubled or more to increase the resistance value thereof, thereby reducing the plating time. The amount of current flowing in. In detail, the tortuous electric ore line 14G can be used as an electric material to transfer current to the main conductor of the gate metal layer 12〇. In a preferred form, the meander lined wire 14G can be a wrap-around f-plated wire frame: and surrounds the substrate unit U1. More preferably, the meandering of the waveform is a square wave, providing two right-angle bends at each peak and valley to create parasitic effects, which in turn interfere with the delay current. In the one-piece type, the meandering electric wire 14G can also be changed to a meandering shape of a comb shape or a mineral tooth shape. In the electroplating process, when a current is introduced from the contact of the substrate strip body ι1 to the inside of the substrate strip body 11 by an external wire, the zigzag plating line 140 can be located at the substrate unit m and the m-mouth metal. Between the layers 12〇' and the zigzag electric ore line 14〇 has a large resistance value, so that the introduced current is less likely to flow to the zigzag plating line 140 having a larger resistance value, thereby reducing the pass through the zigzag plating 201227899 line 140 The amount of current. Therefore, it can be formed in the metal layer I] of the rinsing port. The thickness of the upper electric clock layer decreases inward toward the substrate unit, so that the thickness of the plating layer in the non-main functional area of the injection hole can be omitted. Referring to Figures 4A through 4C, the first plating layer 15 is formed on the 'main gate metal layer 120, and the second plating layer 160 is formed on the portions 133 ±. As described above, since the length of the zigzag plating line 140 is lengthened and the resistance value thereof is greatly increased, the amount of current flowing into the zigzag plating line 14 at the time of electroplating is lower than that flowing into the patterned electrowinning layer. Electricity flow. According to the electrolysis law, the electrochemical equivalent, and the current efficiency formula, it can be derived that the thickness of the electric ore layer is proportional to the current density, where "current density" refers to the current per unit area. Therefore, if the inflowing electric current is larger under the same unit area, the thickness of the formed plating layer is also larger. Therefore, the thickness H1 of the first plating layer 150 (as shown in the figure) can be made smaller than the thickness Η2 of the second electric ore layer 160 (as shown in Fig. 4C) by the meandering plating line 140. Therefore, the first plating layer 15 and the second plating layer 16 are formed in the same electroplating process, wherein the substrate strip structure 1 is integrally disposed on a substrate panel panel before being singulated. In the case of (not shown), the matrix is arranged, so that the electroplating process can be shortened in addition to simplifying the electroplating process. In summary, the present invention has a specific combination relationship of the meandering plating line 140 to the gate metal layer 120 as a technical means thereof, and the length of the zigzag plating line 14 is its own due to its meandering shape. Therefore, the thickness of the first plating layer 15 formed on the metal layer 120 of the rinsing port 12 201227899 can be made smaller than the pads 133 formed on the patterned metal layer 13 by using the zigzag electric line (4). The thickness of the second plating layer 16 is H2. Therefore, the thickness of the plating layer on the gate metal layer 12A can be thinned, but the plating layer on the active region of the package is maintained to have a sufficient thickness to reduce the cost of the substrate strip. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, although the present invention has been disclosed in the preferred embodiments, and is not intended to limit the invention. It is still within the technical scope of the present invention to make any simple modifications, equivalent changes, and repairs made by those skilled in the art without departing from the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a first view of a substrate strip structure for thinning a gate surface in accordance with an embodiment of the present invention, as viewed from above. Fig. 2 is a partially enlarged plan view showing the surface of the substrate strip structure of the electrowinning layer according to the embodiment of the present invention. Fig. 3 is a view showing the surface of the substrate of the electroplated layer in accordance with the embodiment of the present invention. 4A to 4C: a partial cross-section of a substrate of a thinned gate-casting surface according to the present invention, and a partial cross-section of the mouth structure, wherein (A) is a rinsing mouth Partial sectioning of the genus layer, (B) 201227899 is a partial sectioning of the zigzag plating line, and (c) is a partial sectioning of the plurality of pads. [Major component symbol description] 100 Thinned injection port table 1 S-plated substrate strip structure 110 Substrate strip body 111 Substrate unit 112 First surface 113 114 Central slot 120 Note Wash metal layer 130 Patterned metal layer 131 Plating Wire bus bar 132 plating wire 133 140 zigzag plating wire 141 short wire 150 first plating layer 160 second plating layer 171 first solder resist layer 172 second solder resist layer 173 second surface pad opening H1 first plating layer thickness H2 second plating thickness 14

Claims (1)

201227899 _ 七、申請專利範圍: 1、 一種薄化注澆口表面電鍍層之基板條結構,包含: 一基板條本體,該基板條本體内係形成有複數個一 體構成且呈矩陣排列之基板單元; 一注澆口金屬層’係設於該基板條本體之一第一表 面上; 一圖案化金屬層’係設於該基板條本體之一第二表 面上,該圖案化金屬廣係包含有複數個電鐘線匯 流排、複數個電鍍導線與複數個接墊,其中該些 電鍍線匯流排係設置於該些基板單元之外,而該 些電鍍導線與該些接墊係設置於該些基板單元 内,並且藉由該些電鍍導線電性連接該些電鍍線 匯流排至該些接墊; 一曲折電鍍線’係設於該基板條本體之該第一表面 上並連接至該注濟口金屬層; • 一第一電鍍層’係形成於該注澆口金屬層上;以及 一第二電鍍層’係形成於該些接墊上,藉由該曲折 電鑛線使該第一電鑛層之厚度係小於該第二電鑛 層之厚度。 2、 根據申請專利範圍第1項之薄化注澆口表面電鍵層 之基板條結構’其中該第一電鍍層與該第二電鍍層 係由同一電鑛製程所形成。 3、 根據申請專利範圍第2項之薄化注澆口表面電鍍層 之基板條結構’其中該曲折電鍍線係位於該些基板r 15 201227899 單元與該注澆口金屬層之間。 根據申請專利範圍第1、2或》項之薄化注洗口表 面電鍍層之基板條結構,其中該曲折電鍛線係為一 波形曲折之電鍍線框’並圍繞在該些基板單元之外。 5 8 根據申請專利範圍第4項之薄化注澆口表面電鑛層 之基板條結構’其中該曲折電鍍線係藉由複數個等 距排列之短導線並聯至該注澆口金屬層。 根據申請專利範圍第4項之薄化注、、在^ ± 九口表面電鍍層 之基板條結構’另包含有一第一防經a 防如層,係形成於 該基板條本體之該第一表面上,ijj m ^ 復蓋該曲折電鍍 線但顯露該注澆口金屬層。 根據申請專利範圍第6項之薄化注濞π * 兀u表面電鍵層 之基板條結構’另包含有一第二防銲 叶增,係形成於 該基板條本體之該第二表面上,以霜絮4 復盖該些電鍍線 匯流排與該些電鍍導線但顯露該些接塾。 根據申請專利範圍第7項之薄化注液 表面電鍍層 之基板條結構,其中該第一防銲層係 、 ’、丹有—開孔, 以顯露該第一表面在該些基板單元内之部位 16201227899 _ VII. Patent application scope: 1. A substrate strip structure for thinning a gate surface plating layer, comprising: a substrate strip body, wherein the substrate strip body is formed with a plurality of substrate units integrally formed and arranged in a matrix a gate metal layer is disposed on a first surface of the substrate strip body; a patterned metal layer is disposed on a second surface of the substrate strip body, the patterned metal strip includes a plurality of electric clock wire bus bars, a plurality of plated wires and a plurality of pads, wherein the plated wire bus bars are disposed outside the substrate units, and the plating wires and the pads are disposed on the plurality of pads In the substrate unit, the electroplating wires are electrically connected to the pads by the electroplated wires; a zigzag electroplating line is disposed on the first surface of the substrate strip body and connected to the pad a metal layer; a first plating layer is formed on the gate metal layer; and a second plating layer is formed on the pads, the first electrode is made by the tortuous electric mine Layer The thickness is less than the thickness of the second electrical layer. 2. The substrate strip structure of the thinned gate surface electrode bond layer according to claim 1 of the patent application, wherein the first plating layer and the second plating layer are formed by the same electric ore processing. 3. A substrate strip structure for thinning a gate surface plating layer according to item 2 of the patent application scope, wherein the meander plating line is located between the substrate r 15 201227899 unit and the gate metal layer. a substrate strip structure for thinning a surface of a surface of a beaker according to claim 1, 2 or 2, wherein the meandering electric forging line is a corrugated electroplated wire frame 'and surrounds the substrate units . 5 8 The substrate strip structure of the thinning gate surface electrowinning layer according to item 4 of the patent application scope wherein the zigzag plating line is connected in parallel to the gate metal layer by a plurality of equidistantly arranged short wires. According to the thinning note of the fourth aspect of the patent application, the substrate strip structure of the nine-neck surface plating layer further includes a first anti-corrosion layer formed on the first surface of the substrate strip body. Upper, ijj m ^ covers the zigzag plating line but reveals the metal layer of the gate. According to the sixth aspect of the patent application, the substrate strip structure of the π* 兀u surface electro-bonding layer further includes a second solder-proof blade formed on the second surface of the substrate strip body to be frosted The batt 4 covers the electroplated wire bus bars and the electroplated wires but reveals the contacts. The substrate strip structure of the thinned liquid-filled surface plating layer according to Item 7 of the patent application, wherein the first solder resist layer, ', Dan has an opening, to expose the first surface in the substrate units Part 16
TW99146435A 2010-12-28 2010-12-28 Substrate strip with thinned plating layer at mold gate TWI416687B (en)

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TWI283472B (en) * 2005-12-30 2007-07-01 Walton Advanced Eng Inc Chip package having a slot type metal film carrying a wire-bonding chip
KR100797670B1 (en) * 2006-06-12 2008-01-23 삼성전기주식회사 Formation Method of Plating Line for Printed Circuit Board
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US10988853B2 (en) 2016-01-12 2021-04-27 Jfe Steel Corporation Stainless steel sheet including Ni and O-containing coating on surface and method for producing stainless steel sheet

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