201225286irw 36189twf,oc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件及其製造方法，且特 別是有關於一種氮化物半導體模板(nitride semiconductor template)及其製造方法。 【先前技術】 目如’於石夕基板上成長半極化(semipolar)氮化物半導 體（如氮化鎵半導體層）時，氮化鎵半導體層的缺陷密度 大約在108個/平方公分至1〇9個/平方公分之間。由於(〇〇〇1) 氮化鎵多重量子井（GaN MQW)具有較大自發極化場 (spontaneous polarization field)，故發光效率不佳。半極化 氮化鎵多重量子井(semipolar GaN MQW)具有較低的自發 極化場，故具有較佳的發光效率以及波長穩定性。在習知 技術中二成長半極化氮化鎵半導體的方法之一是將氮化録 半導體薄膜成長於矽基板上，但由於氮化鎵半導體與矽基 板=晶格常數衫隨，使得氮化鎵半導體之質難 :，升此外，由於氮化鎵半導體與矽基板之間的熱膨脹 異兩達54% ’因此造成應力過大而產生晶片ΐ曲、 度受以的::使得氮化鎵糊在魏板上之成長厚 氮化触舰树絲減以晶品質良好之 業界亟欲解決、龜裂等現象，實為目前產 201225286 u m 叫71TW 36189twf.doc/n 【發明内容】 本申請案提供一種氮化物半導體模板及其擊造 法，以有效改善氮化物半導體層與基板之間的應力問題。 本申請案提供一種氮化物半導體模板，其包括一美 板、一罩幕層（masklayer)、一第一氮化物半導體層、—二 電材料層以及第二氮化物半導體層。基板具有多個溝渠^ 各溝渠具有一底面一第一傾斜側壁以及一第二傾斜側=。 罩幕層覆蓋第一傾斜側壁，並將第二傾斜側壁暴露。第— 氮化物半導體層配置於基板與罩幕層上，其中第一氮化= 半導體層填入溝渠並與第一傾斜側壁接觸，第一氮化物 導體層具有多個孔洞(voids) ’孔洞位於溝渠外並暴露出 幕層的部份區域’且第—氮化物半導體層具有多個奈米 (nano-rods)。介電材料層覆蓋奈米柱之側壁，並將奈米'柱 之頂表面暴露，且介電材㈣未填滿婦奈餘之間的* 間。第二氮化物半導體層覆蓋奈米柱之頂表面，而第二= 化物半導體層未完全填人奈錄之間，且各該底面與該 二說化物半導體層的_，g，d方向之夾角介於27。至29= 間3 心 f申請案另提供一種氮化物半導體模板的製 法，匕括:於一基板上形成多個溝渠，各溝渠具有 ，^了傾^壁以及-第二傾斜側壁；於基板上形成-於傾斜側壁’並將第二傾斜側壁暴露； :巧:、罩幕層上形成_第一氮化物半導體層，以使第— 氮1 匕物半導體層填人辟並與第-麟，其中第 -此化物半導體層具有多個孔洞，孔洞位於溝渠外並暴露 201225286 --------1 fW 36189twf.doc/n ^罩幕層的部份區域；於第—氮化物半導體層上形成多個 ^柱·’於奈米柱之表面上形成—共形之介電材料層；將 各奈米柱之縣面上的部分介電材料層移除，以將各奈米 柱之頂表©暴露；於各奈米柱之頂表面上形成—第二氮化 物半導體層，以及於奈米柱上形成—第二氮化物半導體 層’其巾第二氮化物半導體層未完全填人奈米柱之間，且 各底面與$二氮化物半導體層的(G，G，G1)方向 27°至29°之間。 為讓本申請案之上述和其他目的、特徵和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 ° 【實施方式】 圖1A至圖1L為本申請案一實施例之氮化物半導體模 板的製造流程示意圖。請參照圖1A，提供一基板1〇〇，在 本實施例中，基板100例如為一矽(001)基板，且此矽基板 之(001)係往（M0)方向傾斜約8。。接著，於基板1〇〇上形 成"電層1丨〇，此介電層11〇例如為氮化梦、氧化石夕或 其他適於作為韻刻阻擔層(etch st0p iayei：)之材質。此外， 介電層110例如係藉由電漿化學氣相沈積(PECVD)方式沈 積於基板100之上表面。 請參照圖1B，於介電層110上形成一圖案化光阻層 PR。詳言之，本實施例例如係先藉由旋轉塗佈(spin c〇ating) 的方式於介電層110上全面性地形成一光阻層，隨後，再 藉由微影製程（即曝光顯影製程）將光阻層圖案化，以形 201225286 rjiyyuuylTW 36189twf.doc/n ft，PR。在本實施例中’圖案化光阻層PR例 約為1微米，而相鄰條狀圖案之間的= 凊參照圖1C’以圖案化光阻層PR為罩 ==，蓋之介電請，以== 所覆 ^ , t>Lt'直到基板100之表面被暴露出 二二=s，圖案化介電層11Ga是藉由乾式#刻方式 二阻’層PRC可知’圖案化介電層_之圖案係與圖案 化先阻層PR之圖案對應。 請參照圖1D’在形成圖案化介電層u 阻層PR。隨後，以圖案化介電層11Qa為罩^ ί 案化介電層11〇a所覆蓋之部分基板漏，以於 =成多個溝渠TR。在本實施例中，溝渠TR例 化刻方式形成，所使㈣㈣賴如為氫氧 液。在本實施例中，各溝渠叹具有-底面B 之扯伸方二側壁S1以及一第二傾斜側壁S2,而各溝渠TR η δ彼此實質上平行’且各溝㉟^的深度以列如 係枝0.8微米至15微米之間。 S1 ^^(111) 5 ^ 之為矽(-1·11)，而底面Β則為矽(ooi)。換言 於63。至61。^側壁S1與對應之底面Β之炎角例如係介 之办間，而各第二傾斜側壁S2與對應之底面B > 〇係介於45。至47。之間。舉例而言，各第一傾斜 201225286 36189twf.doc/n 側壁SI與對應之底面B之夾角為62 7。201225286irw 36189twf, oc/n VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a nitride semiconductor template and a method of fabricating the same . [Prior Art] When a semi-polar nitride semiconductor such as a gallium nitride semiconductor layer is grown on a substrate, the defect density of the gallium nitride semiconductor layer is about 108/cm 2 to 1 〇. 9 / square centimeter. Since the (〇〇〇1) gallium nitride multiple quantum well (GaN MQW) has a large spontaneous polarization field, the luminous efficiency is not good. The semi-polarized GaN MQW has a lower spontaneous polarization field and therefore has better luminous efficiency and wavelength stability. In the prior art, one of the methods for growing a semi-polarized gallium nitride semiconductor is to grow a nitride semiconductor film on a germanium substrate, but since the gallium nitride semiconductor and the germanium substrate = lattice constant, the nitride is nitrided. The quality of gallium semiconductors is difficult: In addition, due to the thermal expansion between the gallium nitride semiconductor and the germanium substrate, the difference between the two is 54%, which causes the stress to be too large and the wafer is distorted and affected: The growth of the thick nitriding touch ship shreds on the Wei board is reduced by the fact that the crystal quality is good, and the cracks and other phenomena are actually produced. 201225286 um is called 71TW 36189twf.doc/n. [Invention] The present application provides a A nitride semiconductor template and a method of fabricating the same to effectively improve the stress problem between the nitride semiconductor layer and the substrate. The present application provides a nitride semiconductor template comprising a slab, a mask layer, a first nitride semiconductor layer, a second material layer, and a second nitride semiconductor layer. The substrate has a plurality of trenches. Each of the trenches has a bottom surface, a first inclined sidewall, and a second sloped side. The mask layer covers the first sloped sidewall and exposes the second sloped sidewall. The first nitride semiconductor layer is disposed on the substrate and the mask layer, wherein the first nitride=semiconductor layer is filled into the trench and is in contact with the first inclined sidewall, and the first nitride conductor layer has a plurality of voids. A portion of the curtain layer is exposed outside the trench and the first nitride semiconductor layer has a plurality of nano-rods. The dielectric material layer covers the sidewall of the nanocolumn and exposes the top surface of the nano-column, and the dielectric material (4) is not filled between the *. The second nitride semiconductor layer covers the top surface of the nano column, and the second semiconductor film layer is not completely filled between the mesas, and the angle between the bottom surface and the _, g, d direction of the second semiconductor layer Between 27. Further, a method for preparing a nitride semiconductor template is provided by: forming a plurality of trenches on a substrate, each trench having a tilting wall and a second inclined sidewall; Forming the slanted sidewalls and exposing the second slanted sidewalls; singularly: forming a first nitride semiconductor layer on the mask layer to fill the first nitrogen semiconductor layer with The first semiconductor layer has a plurality of holes, and the holes are located outside the trench and expose a portion of the mask layer of 201225286 --------1 fW 36189 twf.doc/n ^; the first nitride semiconductor layer Forming a plurality of ^ pillars on the surface of the nano-column to form a conformal layer of dielectric material; removing a portion of the dielectric material layer on each county surface of each nano-column to remove each nano-column The top surface is exposed; a second nitride semiconductor layer is formed on the top surface of each nano column, and a second nitride semiconductor layer is formed on the nano column. The second nitride semiconductor layer of the substrate is not completely filled. Between the nanopillars, and each bottom surface is 27° from the (G, G, G1) direction of the di-nitride semiconductor layer. Between 29°. The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] FIG. 1A to FIG. 1L are schematic diagrams showing a manufacturing process of a nitride semiconductor template according to an embodiment of the present application. Referring to FIG. 1A, a substrate 1 is provided. In the embodiment, the substrate 100 is, for example, a 001 (001) substrate, and the (001) of the 矽 substrate is inclined by about 8 in the (M0) direction. . Next, an electric layer 1 丨〇 is formed on the substrate 1 , and the dielectric layer 11 〇 is, for example, a nitride dream, an oxidized oxide eve, or other material suitable as a resist layer (etch st0p iayei:). . Further, the dielectric layer 110 is deposited on the upper surface of the substrate 100 by, for example, plasma chemical vapor deposition (PECVD). Referring to FIG. 1B, a patterned photoresist layer PR is formed on the dielectric layer 110. In detail, in this embodiment, for example, a photoresist layer is integrally formed on the dielectric layer 110 by spin coating, and then by a lithography process (ie, exposure development). Process) The photoresist layer is patterned to form 201225286 rjiyyuuylTW 36189twf.doc/n ft, PR. In the present embodiment, the patterning photoresist layer PR is about 1 micrometer, and the = between the adjacent strip patterns is referred to as FIG. 1C' with the patterned photoresist layer PR as a mask ==, and the dielectric of the cover is used. Covered by == ^, t>Lt' until the surface of the substrate 100 is exposed to two or two = s, and the patterned dielectric layer 11Ga is known by the dry-type two-resistance layer PR. The pattern of _ corresponds to the pattern of the patterned first resist layer PR. Referring to FIG. 1D', a patterned dielectric layer u resist layer PR is formed. Subsequently, a portion of the substrate covered by the dielectric layer 11A is masked by the patterned dielectric layer 11Qa to form a plurality of trenches TR. In the present embodiment, the trench TR is formed in an etched manner, so that (4) (4) is such as an oxyhydrogen solution. In this embodiment, each of the trenches has a side wall S1 and a second inclined side wall S2 of the bottom surface B, and each of the trenches TR η δ is substantially parallel to each other' and the depth of each of the grooves 35 is as follows. The branches are between 0.8 microns and 15 microns. S1 ^^(111) 5 ^ is 矽(-1·11), and the bottom Β is oo (ooi). In other words, at 63. To 61. ^ The sidewall S1 and the corresponding underside of the underside are, for example, interposed, and each of the second inclined sidewalls S2 and the corresponding bottom surface B > To 47. between. For example, each of the first slopes 201225286 36189 twf.doc/n has an angle of 62 7 between the side wall SI and the corresponding bottom surface B.
v ’而各第二倾斜相，I 壁S2與對應之底面B之夾角為46.7〇。 一 請參照SI 1E，於基板1〇〇上形成一罩幕層^ 第二傾斜側壁S1並將第-傾斜側壁S1暴露 = 中，罩幕層12〇彳選擇性地覆蓋於底面B之部分 在本實施例中’罩幕層U0的形成方法包 令 励傾斜-角度，並對基板議妨—蒸鑛製程 層m能夠選擇性地沈積於各溝$ TR之第二傾斜側壁幻 上或者選擇性地沈積於第二傾斜側壁S2以及底面B之部 分區域上。由於基板動係傾斜-角度，故罩幕層12〇^ 易沈積於第-傾斜側壁S1上。值得注意的是，基板1〇〇 之傾斜角度跟第一傾斜側壁S1與對應之底面B之夾角相 關’此領域具有通常知識者可根據第一傾斜側壁S1與對 應之底面B之夾角決定出基板100在蒸鍍過程中之傾&角 度。此外，底面B上疋否沈積有罩幕層120也與基板1〇〇 之傾斜角度有關，此領域具有通常知識者可透過基板1〇〇 之傾斜角度的調整來控制罩幕層120的分佈範圍。舉例而 言，罩幕層i2〇之材質例如為氮化石夕(Si0x)、氧化石夕(SiNx) 或其他不易於在其上進行磊晶之材質。 請參照圖1F與圖1G，在完成罩幕層12〇之製作後， 接著進行一磊晶製程以於基板1〇〇以及罩幕層丨2〇上形成 半極化之第一氮化物半導體層130,第一氮化物半導體層 130的形成方式例如為金屬有機物化學氣相沈積(M〇CVD) 製程。在磊晶製程的初期，第一氮化物半導體層130會於 第一傾斜側壁S1以及未被罩幕層12〇覆蓋之底面B成長 201225286 r^ivyuuylTW 36189twf.doc/n 以填滿溝渠TR..... 日衣狂Μ下沏，死谷 >冓渠TR成長出來的各第一氮化物半導體層13〇會會逐漸 靠近而接觸’以形成有孔洞130a，且孔洞13〇a位於溝渠 TR之外並暴露出罩幕層120的部份區域；在蟲晶製程^ 後期，第一氮化物半導體層130會持續成長〇8微米至12 微米。在本實施例中，第一氮化物半導體層13〇 翁 化鎵(GaN)半導體層，第一氮化物半導體層13〇中孔洞13加 的高度h例如係介於0.7微米至！·〇微米之間，第一氮化 物半導體層130的最大厚度T (即底面B至第一氮化物半 導體層130之上表面的距離）例如介於2 5微米至3 5 米之間，而第一氮化物半導體層13〇的最小厚度t (即孔 =、130a的頂端至第一氮化物半導體層13〇之上表面的距 離J介於0.8微米至1.2微米之間。 接著將搭配圖1H至圖1K詳細說明奈米柱13合 示於圖1J與圖1Κ中）的製造方法。 、曰 带二^圖出與，U ’於第一氮化物半導體層130上 「鎳曰150 ’接著對鎳層15〇進行 導體層13〇上形成錄群(Nicl 的厚度例如係介於刚埃至_ = 形成i規ί Γίΐ過約850°c之熱退火處理(anneai㈣)以 130之上表面上，且日;;•群 係'於第一氮化物半導體層 平方公分。 且鎳群150a之分佈密度不低於1〇8個/ 3月參照圖1J與圖1K，以錄群l5〇a為罩幕，移除未被 鎳群撕所覆蓋之部分第—氮化物半導體層⑽，以於錄 201225286 --------】TW 36189tw£doc/n 群150a下方形成奈米柱130b，如圖1Jr所示。在本實施例 中，第一氮化物半導體層130’之各奈米柱130b之高度例 如係介於0.5微米至0.75微米之間，各奈米柱13〇b之寬 度例如係介於30奈米至500奈米之間，且奈米柱13肋之 分佈在、度不低於1〇8個/平方公分。然而，此領域具有通常 知識者可根據實際設計需求而更動，奈米柱13%之高度、 寬度以及密度。 在形成奈米柱130b之後，將鎳群150a移除，如圖1K 所示。在將鎳群15〇a移除之後，本實施例可進一步於奈米 柱130b之表面上形成一共形(c〇nf〇rmal)之薄介電材料層 16〇，之後再將奈米柱130b之頂表面上的部分介電材料^ 160移除’以將奈米柱130b之頂表面暴露。從圖丨反可知曰， 介電材料層僅覆蓋奈米柱13%的側壁，但未填滿 的奈米柱130b之間的空間。 ,請參照圖1L，於奈妹丨通之頂表面上繼續成長一 半極化之第二氣化物半導體層14G，其中第二氮化物 體層140係覆蓋於奈錄13%的頂表 半導體層糾會技獻奈錄1鳥之_^= 得注意的是’底面B與第二氮化物半導體層 = :向之爽角介於27。至29。之間，而較佳為28。。舉例而，二” 第-氮化物半導體層14G例如係藉由混合氣相蟲' (Hydnde Vapor Phase Epitaxy，HVPE)m形成。 支術 在本實施例中’第二氮化物半導體層l4 係介於3微米至300微米之間。然而， =度例如 二氮化物半導體層140之厚度。此領域具有i常知 201225286 F51990091TW 36189twf.doc/n 可根據實際設計需求更動第二氮化物半導體層14〇之 度。此外’第二氮化物半導體層14〇可以是未_之氮化 鎵半導體層、N型摻雜之氮化鎵半導體層，或者是二者之 組合。v ′ and each of the second inclined phases, the angle between the I wall S2 and the corresponding bottom surface B is 46.7 〇. Referring to SI 1E, a mask layer ^ second inclined sidewall S1 is formed on the substrate 1 and the first inclined sidewall S1 is exposed to be in the middle, and the mask layer 12 is selectively covered on the bottom surface B. In the present embodiment, the method for forming the mask layer U0 includes the tilt-angle of the excitation, and the substrate is discussed. The steaming process layer m can be selectively deposited on the second inclined sidewall of each trench $TR or alternatively. The ground is deposited on a portion of the second inclined side wall S2 and the bottom surface B. Since the substrate is tilted-angled, the mask layer 12 is easily deposited on the first inclined sidewall S1. It should be noted that the inclination angle of the substrate 1〇〇 is related to the angle between the first inclined side wall S1 and the corresponding bottom surface B. The person skilled in the art can determine the substrate according to the angle between the first inclined side wall S1 and the corresponding bottom surface B. 100 tilt & angle during evaporation. In addition, whether or not the mask layer 120 is deposited on the bottom surface B is also related to the tilt angle of the substrate 1 . In this field, the distribution of the mask layer 120 can be controlled by a person skilled in the art through the adjustment of the tilt angle of the substrate 1 . . For example, the material of the mask layer i2 is, for example, a nitride (Si0x), a cerium oxide (SiNx) or other material that is not easily epitaxially formed thereon. Referring to FIG. 1F and FIG. 1G, after the fabrication of the mask layer 12 is completed, an epitaxial process is performed to form a semi-polarized first nitride semiconductor layer on the substrate 1 and the mask layer 2 130. The formation of the first nitride semiconductor layer 130 is, for example, a metal organic chemical vapor deposition (M〇CVD) process. In the initial stage of the epitaxial process, the first nitride semiconductor layer 130 is grown on the first inclined sidewall S1 and the bottom surface B not covered by the mask layer 12〇 201225286 r^ivyuuylTW 36189twf.doc/n to fill the trench TR... . . . , the first nitride semiconductor layer 13 成长 成长 & , , TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR A portion of the mask layer 120 is exposed and exposed; at the end of the process, the first nitride semiconductor layer 130 continues to grow from 8 microns to 12 microns. In the present embodiment, the first nitride semiconductor layer 13 is a gallium (GaN) semiconductor layer, and the height h of the holes 13 in the first nitride semiconductor layer 13 is, for example, 0.7 μm! Between the micron, the maximum thickness T of the first nitride semiconductor layer 130 (ie, the distance from the bottom surface B to the upper surface of the first nitride semiconductor layer 130) is, for example, between 25 μm and 35 m, and The minimum thickness t of a nitride semiconductor layer 13 (ie, the distance J from the top of the hole = 130a to the upper surface of the first nitride semiconductor layer 13 is between 0.8 μm and 1.2 μm. Next, it will be matched with FIG. 1H to Fig. 1K illustrates in detail the manufacturing method of the nanocolumn 13 shown in Fig. 1J and Fig. 1). And the U 2 is formed on the first nitride semiconductor layer 130 by "nickel 曰 150 ' and then the nickel layer 15 〇 is formed on the conductor layer 13 ( (the thickness of the NiCl is, for example, between To _ = form i ί Γ ΐ ΐ 约 850 850 约 约 约 约 anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne anne 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 The distribution density is not less than 1〇8/3. Referring to FIG. 1J and FIG. 1K, a portion of the first-nitride semiconductor layer (10) not covered by the nickel group tear is removed by using the recording group l5〇a as a mask. Recorded 201225286 --------] TW 36189 tw doc / n formed below the group 150a nano column 130b, as shown in Figure 1Jr. In this embodiment, the first nitride semiconductor layer 130' of each nano The height of the column 130b is, for example, between 0.5 micrometers and 0.75 micrometers, and the width of each nanocolumn 13〇b is, for example, between 30 nm and 500 nm, and the distribution of the ribs of the nanocolumn 13 is Not less than 1〇8/cm2. However, the general knowledge in this field can be changed according to the actual design requirements, the height of the column is 13%, the width and the density. After forming the nanocolumn 130b, the nickel group 150a is removed, as shown in Fig. 1K. After removing the nickel group 15〇a, the present embodiment can further form a conformal shape on the surface of the nanocolumn 130b ( The thin dielectric material layer 16〇 of the c〇nf〇rmal) is then removed by removing a portion of the dielectric material ^160 on the top surface of the nanocolumn 130b to expose the top surface of the nanocolumn 130b. It can be seen that the dielectric material layer covers only 13% of the sidewalls of the nano-pillar, but the space between the unfilled nano-pillars 130b. Please refer to Figure 1L, and continue to grow half on the top surface of Nai Meitong. The polarized second vaporized semiconductor layer 14G, wherein the second nitrided object layer 140 is covered by the 13% of the top surface semiconductor layer of the Nailu. And the second nitride semiconductor layer =: the refresh angle is between 27 and 29, and preferably 28. For example, the second" nitride-nitride semiconductor layer 14G is, for example, by mixing the fungus '(Hydnde Vapor Phase Epitaxy, HVPE)m is formed. In this embodiment, 'the second nitride semiconductor layer l4 is between 3 micrometers and 300 micrometers. However, the degree is, for example, the thickness of the di-nitride semiconductor layer 140. This field has the general knowledge of 201225286 F51990091TW 36189twf.doc/n, which can change the degree of the second nitride semiconductor layer 14 according to actual design requirements. The di-nitride semiconductor layer 14A may be a gallium nitride semiconductor layer, an N-type doped gallium nitride semiconductor layer, or a combination of the two.
從圖1L可知’本申請案之氮化物半導體模板包括基 板100、罩幕層120、第-氮化物半導體層13〇，以及第二 氮化物半導體層140。基板1〇〇具有多個溝渠TR，各溝渠 TR具有底面B、第-傾斜側壁S1以及第二傾斜側壁幻 罩幕層120覆蓋第二傾斜側壁S2，並將第一傾斜側壁 暴露。當然、，罩幕層12G可以選擇性地覆蓋於底面B的部 份區域上。第一氮化物半導體層13〇，配置於基板1〇〇與罩 幕層120上’其中第一氮化物半導體層13〇，填入溝渠 並與第-傾斜側壁S1接觸，第—氮化物半導體層⑽，具 有多個孔洞130a，而孔洞13〇a位於溝渠TR外並暴露出 幕層120的部份區域’且第一氮化物半導體層130,具有多 個奈米柱130b。第二氮化物半導體層刚覆蓋奈米柱 130b，且第二氮化物半導體層14〇未完全填入奈米柱㈣ 之間的空間内。 承上所述’在本申請案之氮化物半導體模板中，孔洞 130a以及相鄰奈米枝13〇b之間的空間具 半導㈣13G，相異之折射率。錢是孔洞1施^-I 化物半導體=30,之間的折射率差異，還是奈米柱· 之間的空間與f —気化物半導體層13G，之間的折射率差 異，都有助於崎H因此本Ψ 板可應用於發光元件(如發光二極體、雷射二極二jr 201225286As is apparent from Fig. 1L, the nitride semiconductor template of the present application includes the substrate 100, the mask layer 120, the first-nitride semiconductor layer 13A, and the second nitride semiconductor layer 140. The substrate 1 has a plurality of trenches TR, each trench TR having a bottom surface B, a first-sloping sidewall S1, and a second oblique sidewall mask layer 120 covering the second sloped sidewall S2 and exposing the first sloped sidewall. Of course, the mask layer 12G can selectively cover the portion of the bottom surface B. The first nitride semiconductor layer 13 is disposed on the substrate 1 and the mask layer 120, wherein the first nitride semiconductor layer 13 is filled in the trench and is in contact with the first oblique sidewall S1, and the first nitride semiconductor layer (10) having a plurality of holes 130a, and the holes 13〇a are located outside the trench TR and exposing a partial region of the curtain layer 120 and the first nitride semiconductor layer 130 has a plurality of nano-pillars 130b. The second nitride semiconductor layer just covers the nano-pillar 130b, and the second nitride semiconductor layer 14 is not completely filled in the space between the nano-pillars (4). According to the above description, in the nitride semiconductor template of the present application, the space between the hole 130a and the adjacent nano-strips 13〇b has a semi-conductive (four) 13G, which has a different refractive index. The difference in refractive index between the hole 1 and the semiconductor semiconductor = 30, or the difference in refractive index between the space between the nano-pillar and the f-telluride semiconductor layer 13G, all contribute to the H Therefore, the board can be applied to light-emitting elements (such as light-emitting diodes, laser diodes, jr 201225286)
J1TW 36189twf.doc/n 場效電晶體(MOSFET)、高電子移動率電晶體 M 件中，以提昇前述之元件的效能。 ）寺兀 此外，在本申請案之氮化物半導體模板中，孔洞130a 以及奈米柱130b可以有效降低第一氮化物半導體層i3〇, 與第二氮化物半導體層14〇的應力，有助於增加成長的 度以及改善缺陷密度。 雖然本申請案已以較佳實施例揭露如上，然其並非用 以限疋本申請案，任何熟習此技藝者，在不脫離本申請案 之精神和範圍内’當可作些許之更動與潤飾’因此本申請 案之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖il為本申請案一實施例之氮化物半導體模 板的製造流程示意圖。 【主要元件符號說明】 100 :基板 110 :介電層 ll〇a :圖案化介電層 12〇 :罩幕層 13〇 ' 130’ ：第―氮化物半導體 130a :孔洞 130b :奈米柱 140 ·第一氮化物半導體 150 :鎳層 12 201225286 ^^lyyuuylTW 36189twf.doc/n 150a :鎳群 160 :介電材料層 PR :圖案化光阻層 TR :溝渠 B :底面 51 :第一傾斜側壁 52 :第二傾斜側壁 d :深度 T:最大厚度 t :最小厚度J1TW 36189twf.doc/n Field Effect Transistor (MOSFET), High Electron Mobility Transistor M device to enhance the performance of the aforementioned components. In addition, in the nitride semiconductor template of the present application, the hole 130a and the nano-pillar 130b can effectively reduce the stress of the first nitride semiconductor layer i3〇 and the second nitride semiconductor layer 14 Increase the degree of growth and improve the density of defects. Although the present application has been disclosed in the above preferred embodiments, it is not intended to limit the application, and those skilled in the art can make a few changes and refinements without departing from the spirit and scope of the present application. 'The scope of protection of this application is therefore subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1 are schematic diagrams showing the manufacturing process of a nitride semiconductor template according to an embodiment of the present application. [Description of main component symbols] 100: Substrate 110: Dielectric layer 11A: Patterned dielectric layer 12A: Mask layer 13〇' 130': First-nitride semiconductor 130a: Hole 130b: Nano column 140 · First nitride semiconductor 150 : nickel layer 12 201225286 ^^lyyuuylTW 36189twf.doc/n 150a : nickel group 160 : dielectric material layer PR : patterned photoresist layer TR : trench B : bottom surface 51 : first inclined sidewall 52 : Second inclined side wall d: depth T: maximum thickness t: minimum thickness