[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TW201218383A - Thin film transistor and pixel structure having the thin film transistor - Google Patents

Thin film transistor and pixel structure having the thin film transistor Download PDF

Info

Publication number
TW201218383A
TW201218383A TW100116496A TW100116496A TW201218383A TW 201218383 A TW201218383 A TW 201218383A TW 100116496 A TW100116496 A TW 100116496A TW 100116496 A TW100116496 A TW 100116496A TW 201218383 A TW201218383 A TW 201218383A
Authority
TW
Taiwan
Prior art keywords
thin film
film transistor
layer
channel layer
source
Prior art date
Application number
TW100116496A
Other languages
Chinese (zh)
Other versions
TWI476931B (en
Inventor
Chen-Yi Wu
Yih-Chyun Kao
Chun-Yao Huang
Original Assignee
Au Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Au Optronics Corp filed Critical Au Optronics Corp
Priority to TW100116496A priority Critical patent/TWI476931B/en
Priority to US13/180,555 priority patent/US8304778B2/en
Publication of TW201218383A publication Critical patent/TW201218383A/en
Application granted granted Critical
Publication of TWI476931B publication Critical patent/TWI476931B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

A thin film transistor and a pixel structure having the thin film transistor. The thin film transistor is disposed on a substrate and includes a gate, a gate insulation layer, a source, a channel layer, and a drain. The gate insulation layer covers on the gate and the substrate. The source is disposed on a portion of the gate insulation layer. The source is disposed on a portion of the gate insulation layer. The channel layer is disposed on the gate insulation layer and covers a portion of the source located above the gate. The drain is disposed on the channel layer and electrically connected to the channel layer.

Description

201218383 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種薄膜電晶體與晝素結構，且特別 是有關於一種通道長度可隨不同需求而調整的薄膜電晶體 與具有此薄膜電晶體的晝素結構。 【先前技術】 近年來，由於半導體製程技術的進步，薄膜電晶體的 製造越趨容易與快速。薄膜電晶體的應用相當廣泛，例如 • ……口。门…•狀电鉬菔收晶顯不器(thin film transistor liquid crystal displayer，TFT LCD)等。以薄膜電晶 體液晶顯示ϋ為例，薄膜電晶體可作為充電或放電的開關 來控制各晝素的顯示。 一 的技術中’薄膜電晶體的源極與汲極係採用同 案化而成。源極與汲極之_水平距離至少 ϊί源極與汲極彼此分離。也就是說，目 極時，源極無極之二2==源， 薄膜電晶體的通道長度以及配置面積也^小二=’ 高，薄膜電日ίΓί 件特性的要求越來越 制了薄膜電晶體的發展。 、輪出電流的提升而限 201218383 【發明内容】 十。^發明提供一種薄膜電晶體，其源極與汲極之間的距 離可隨不同需求而調整，甚至小於微影钱刻製程所能 的極限。 < 本發明提供一種畫素結構，其薄膜電晶體具有理想的 輸出電流。 曰本發明提供一種薄膜電晶體，配置於一基板上。薄膜 電晶體包括閘極、閘極絕緣層、源極、通道層以及汲極。、 ，極絕緣層覆蓋於閘極及基板上。源極配置於部份問極絕 緣層上。通道層配置於閘極絕緣層上，且覆蓋閘極上方之 部分源極。汲極配置於通道層上且電性連接於通道層。 上在本發明之一實施例中，上述之薄膜電晶體更包含— 保濩層。保護層覆蓋源極、通道層與閘極絕緣層，且保言雀 層具有至少一孔洞暴露部份通道層。具體而言，汲極係經 由孔洞電性連接通道層。在—實施例中，孔洞可以是位= 閘極與通道層之正上方。 、 在本發明之一實施例中，上述之薄膜電晶體更包含一 保護層，其覆蓋源極、通道層與汲極。此外，通道層例如 更覆蓋閘極絕緣層。 θ σ 在本發明之一實施例中，上述之汲極更覆蓋閘極絕 層上。 在本發明之一實施例中，上述之源極接觸通道層的— 源極接觸區與汲極接觸通道層的一汲極接觸區在平行於美 板的一水平距離大於等於零。 土 4 201218383 在本發明之一實施例中， 源極接觸區與刪通道層的===: 板的水平轉小於3〃m。 闕£在千仃於基 屬氧中’上述之通道層的材質包括金 物半導體二半導體。舉例來說’金屬氧化 導電^發明之—實施财，上述㈣包括透明 屬。在本制之-實施财，上狀難㈣f包括金 的材ί本發明之—實施例中，上述之源極與汲極具有相同 本發明另提出—種晝素結構，包括如前所述之薄膜 曰曰體以及畫素電極。晝素電極電性連接於汲極。 -膜f本發日月之—實闕中，上述之晝素電極和汲極為同 基於上述，本發明利用不同層導電層製作薄膜電 的源極與汲極’並且源極與汲極分別在通道層前後製作而 成一本發明的薄膜電晶體中，源極與沒極之間的水平距離 不受製程極限的限制，因此通道長度可以隨不同需求 整以具有理想的載子遷料。如此-來，具有本發明之; 膜電晶體的晝素結構可以有更好的反應速率。 ^為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 、 201218383 【實施方式】 圖1繪示為本發明第一實施例的薄膜電晶體剖面示意 圖。請參照圖1，薄膜電晶體1〇〇配置於基板10上。薄膜 電晶體100包括閘極U0、閘極絕緣層120、源極130、通 道層140、保護層150以及汲極160。閘極11〇配置於基板 10上，而閘極絕緣層120覆蓋於閘極11〇及基板10上。 源極130配置於部份閘極絕緣層120上。通道層14〇配置 於閘極絕緣層120上，且覆蓋閘極110上方之部分源極130 以及部份的閘極絕緣層120。保護層150覆蓋源極130、通 道層140以及未被源極130、通道層140所覆蓋的閘極絕 緣層120。及極160配置於通道層140上方。此外，保護 層150具有暴露出部分通道層140的孔洞152，以使沒極 160透過孔洞152接觸通道層140並且電性連接於通道層 140。 在本實施例中，各元件的製作順序依序為閘極U〇 絕緣層120、源極130、通道層140、保護層150以及汲才 160。閘極11〇的材質可以是金屬或其他的導電材料。通王 層140的材質可以是非晶矽半導體材料、金屬氧化物半去 體材^、有機半導體材料等，其中金屬氧化物半導體材冲 可以是銦鎵鋅氧化物(Indium_Gallium Zinc 〇乂血，£ 另外，源極130與汲極160的材質例如可選自於金屬、七 月，電材料、金屬合金等導電材料，其中透明導電材料s 以疋銦錫氧化物。由於製作的步驟不同，源極⑽斑糾 ⑽可以選用相同材質加以製作，或是分別使用不同啦 6 201218383 貝加以製作。當然，上述的材質僅是舉例說明之用，並非 用限定本發明。 源極130與汲極160是採用不同膜層在不同的製作步 驟中製作而成的，其中通道層14〇疊置於源極13〇上，而 及極160璧置於通道層14〇上。因此，源極與汲極16〇 的相對位置不受製程精度的限制而可隨不同需求來調整。 具體而言，源極130接觸通道層14〇的源極接觸區132與 汲極160接觸通道層140的汲極接觸區162在平行於基板 10的水平距離d可以小於3μιη。在其他的實施方式中，源 極130接觸通道層140的源極接觸區132與汲極16〇接觸 通道層140的汲極接觸區162在平行於基板1〇的水平距離 d Τ以洛在大於荨於零的任何數值。相較於習知以同一導 電材料層在同一個圖案化步驟中製作源極與汲極時需使源 ，與汲極之間至少相隔3μιη的技術而言，本實施例的薄膜 电曰日體100在設計源極130與沒極相對位置時舍 彈性。 田 、，一般而言，源極接觸區132與汲極接觸區162之間的 水平距離d縮小，則薄膜電晶體1〇〇的通道長度(channel length)將隨之縮減。反之，源極接觸區132與汲極接觸區 162&間的水平距離d增加時，薄膜電晶體1〇〇的通道長度 將ik之增加。在本實施例中，源極接觸區132與汲極 區162間的水平距離以受到特定限制，所以薄膜電晶體 γοο*的通逭長度可隨不同需求的設計而調整。除此之外， 4膜電晶體刚中，通道層⑽位於汲極⑽與閘極⑽201218383 VI. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor and a halogen structure, and in particular to a thin film transistor with a channel length that can be adjusted according to different needs and has the same The crystal structure of the crystal. [Prior Art] In recent years, the manufacture of thin film transistors has become easier and faster due to advances in semiconductor process technology. Thin film transistors are used in a wide variety of applications, such as • ports. The door ... is a thin film transistor liquid crystal display (TFT LCD). Taking thin film electro-crystal liquid crystal display as an example, the thin film transistor can be used as a charging or discharging switch to control the display of each element. In the technique of the first embodiment, the source and the drain of the thin film transistor are formed in the same manner. The source and drain have a horizontal distance of at least ϊί source and drain are separated from each other. That is to say, when the target is extremely, the source is infinitely 2 == source, the channel length and the configuration area of the thin film transistor are also small == high, and the requirements of the characteristics of the film are increasingly thin. The development of crystals. , the increase in the current of the wheel is limited to 201218383 [Summary] Ten. The invention provides a thin film transistor in which the distance between the source and the drain can be adjusted to different requirements, even less than the limits of the lithography process. < The present invention provides a pixel structure in which a thin film transistor has an ideal output current. The present invention provides a thin film transistor disposed on a substrate. The thin film transistor includes a gate, a gate insulating layer, a source, a channel layer, and a drain. , the insulating layer covers the gate and the substrate. The source is placed on the partial insulation layer. The channel layer is disposed on the gate insulating layer and covers a portion of the source above the gate. The drain is disposed on the channel layer and electrically connected to the channel layer. In an embodiment of the invention, the thin film transistor further comprises a protective layer. The protective layer covers the source, the channel layer and the gate insulating layer, and the protective layer has at least one hole exposing a portion of the channel layer. Specifically, the drain is electrically connected to the channel layer via the holes. In an embodiment, the holes may be directly above the bit = gate and channel layers. In an embodiment of the invention, the thin film transistor further includes a protective layer covering the source, the channel layer and the drain. Furthermore, the channel layer covers, for example, the gate insulating layer. θ σ In one embodiment of the invention, the above-described drain is more overlying the gate insulator. In an embodiment of the invention, the source contact region of the source contact channel layer and the drain contact region of the drain contact channel layer have a horizontal distance parallel to the US plate greater than or equal to zero. Soil 4 201218383 In one embodiment of the invention, the source contact area and the channel layer are ===: the horizontal rotation of the board is less than 3 〃m.在 In the base oxygen, the material of the channel layer described above includes a metal semiconductor semiconductor. For example, 'metal oxide conduction> invention--implementation, the above (4) includes transparent genus. In the present invention, the implementation of the financial, the upper form is difficult (4) f includes the material of the gold. In the embodiment of the invention, the source and the drain are the same as the present invention. Thin film body and pixel electrode. The halogen electrode is electrically connected to the drain. - The film f is the same as the above, the above-mentioned halogen electrode and the crucible are based on the above, the present invention uses different layers of the conductive layer to make the source and the drain of the thin film, and the source and the drain are respectively In the thin film transistor of the invention, the horizontal distance between the source and the electrode is not limited by the process limit, so the channel length can be adjusted to have an ideal carrier relocation according to different requirements. As such, it has the present invention; the halogen structure of the membrane transistor can have a better reaction rate. The above described features and advantages of the present invention will be more apparent from the following description. [Embodiment] FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to a first embodiment of the present invention. Referring to FIG. 1, a thin film transistor 1 is disposed on a substrate 10. The thin film transistor 100 includes a gate U0, a gate insulating layer 120, a source 130, a channel layer 140, a protective layer 150, and a drain 160. The gate 11 is disposed on the substrate 10, and the gate insulating layer 120 covers the gate 11 and the substrate 10. The source 130 is disposed on a portion of the gate insulating layer 120. The channel layer 14 is disposed on the gate insulating layer 120 and covers a portion of the source 130 and a portion of the gate insulating layer 120 above the gate 110. The protective layer 150 covers the source 130, the channel layer 140, and the gate insulating layer 120 that is not covered by the source 130 and the channel layer 140. The pole 160 is disposed above the channel layer 140. In addition, the protective layer 150 has a hole 152 exposing a portion of the channel layer 140 such that the gate 160 is in contact with the channel layer 140 and electrically connected to the channel layer 140. In this embodiment, the order of fabrication of the elements is sequentially the gate U 〇 insulating layer 120, the source 130, the channel layer 140, the protective layer 150, and the cymbal 160. The material of the gate 11〇 may be metal or other conductive material. The material of the king layer 140 may be an amorphous germanium semiconductor material, a metal oxide semi-destructive material, an organic semiconductor material, etc., wherein the metal oxide semiconductor material may be indium gallium zinc oxide (Indium_Gallium Zinc blood, £ in addition The material of the source 130 and the drain 160 may be selected, for example, from a conductive material such as a metal, a July, an electric material, or a metal alloy, wherein the transparent conductive material s is a tantalum indium tin oxide. The source (10) is different due to the steps of fabrication. The spot correction (10) can be made of the same material, or it can be made by using the different materials. Of course, the above materials are for illustrative purposes only and are not intended to limit the invention. The source 130 and the drain 160 are different. The film layer is fabricated in different fabrication steps, wherein the channel layer 14 is stacked on the source 13 , and the pole 160 璧 is placed on the channel layer 14 。. Therefore, the source and the drain are 16 〇 The relative position is not limited by the precision of the process and can be adjusted according to different requirements. Specifically, the source contact region 132 of the source 130 contacting the channel layer 14 is in contact with the drain of the channel layer 140. The horizontal distance d of the contact region 162 parallel to the substrate 10 may be less than 3 μm. In other embodiments, the source 130 contacts the source contact region 132 of the channel layer 140 and the drain contact region of the drain 16 〇 contact channel layer 140. 162 is at any horizontal value d 平行 parallel to the substrate 1 Τ 洛 在 any value greater than 荨 zero. Compared to the conventional source of the same conductive material in the same patterning step to make the source and the drain need to make the source In the technique of at least 3 μm between the drain and the drain, the thin film enamelled body 100 of the present embodiment is elastic when designing the source 130 and the poleless relative position. Field, in general, the source contact region 132 When the horizontal distance d between the contact region 162 and the drain is reduced, the channel length of the thin film transistor 1 将 will be reduced. Conversely, the level between the source contact region 132 and the drain contact region 162 & When the distance d is increased, the channel length of the thin film transistor 1 将 is increased by ik. In the present embodiment, the horizontal distance between the source contact region 132 and the drain region 162 is specifically limited, so the thin film transistor γοο* The length of the overnight can be Design needs adjustment. In addition, just 4 film transistors, the channel layer located ⑽ ⑽ drain and gate ⑽

S 7 201218383 之間的結構設計有助於降低汲極i6〇與閛極11()間的電容 搞合效應因此’ 4膜電晶體100的間極·^及極寄生電容較 小而有助於提昇薄膜電晶體1〇〇的電性特性。 圖2繪示為本發明第二實施例的薄膜電晶體剖面示耷 圖。請參照圖2,薄膜電晶體200配置於基板1〇上。薄= 電晶體1〇〇包括閘極110、閘極絕緣層120、源極13〇、通 道層140、保護層250以及汲極160。閘極11〇配置於基^ 10上，而閘極絕緣層120覆蓋於閘極11〇及基板ι〇^。 源極130配置於部份閘極絕緣層12〇上。通道層14〇配置 於閘極絕緣層12G上，且覆蓋閘極110上方之部分源極 13〇保4層25〇覆蓋源極13〇、通道層⑽以及未被源極 130、通道層140所覆蓋的閘極絕緣層12〇。沒極160配置 於通道層M0上方。此外，保護層25〇具有孔洞⑸，以 ί ==透過孔洞152接觸^道層140並且電性連接於 於仵二=?實施例與第一實施例的主要差異在 二:同152所設置的位置。在本實施例中， ΪΙΓιίηΙ是位於閘極m與通道層140之正上方。此 接觸H展1觸通道層140的源極接觸區132與汲極160 距離=二:的〉及極接觸區1621平行☆基板10的水平 距離d例如為零。如μ L可以是由通道a t —來電0的通道長度 的通^ ;4〇:膜厚而決定。因此’薄膜電晶體 來達到所件=效軸如絲子遷移速率提升 201218383 由於源極130與没極160撻田 ㈣〇與汲極可以選用相= 使用不同的材質加以製作。舉例而、▲乍’或是分別 的材質例如可選自於金屬、透：，，極13G與及極160 其中透明導電材料可以是銦錫氧化：。二:屬The structural design between S 7 201218383 helps to reduce the capacitance effect between the drain electrode i6〇 and the drain electrode 11(). Therefore, the inter-electrode and the parasitic capacitance of the 4-film transistor 100 are small and help. Improve the electrical properties of the thin film transistor. 2 is a cross-sectional view of a thin film transistor according to a second embodiment of the present invention. Referring to FIG. 2, the thin film transistor 200 is disposed on the substrate 1A. Thin = transistor 1 〇〇 includes gate 110, gate insulating layer 120, source 13 〇, channel layer 140, protective layer 250, and drain 160. The gate 11 is disposed on the substrate 10, and the gate insulating layer 120 covers the gate 11 and the substrate ι. The source 130 is disposed on a portion of the gate insulating layer 12A. The channel layer 14 is disposed on the gate insulating layer 12G, and a portion of the source 13 over the gate 110 is protected by 4 layers 25 〇 covering the source 13 〇, the channel layer (10), and the source 130 and the channel layer 140. Covered gate insulating layer 12〇. The poleless 160 is arranged above the channel layer M0. In addition, the protective layer 25 has a hole (5), and the contact layer 140 is contacted through the hole 152 and electrically connected to the second layer. The main difference between the embodiment and the first embodiment is two: the same as the setting of 152. position. In the present embodiment, ΪΙΓιίηΙ is located directly above the gate m and the channel layer 140. The source contact region 132 of the contact H-channel 1 channel layer 140 is parallel to the drain electrode 160 and the pole contact region 1621 is parallel. The horizontal distance d of the substrate 10 is, for example, zero. For example, μ L can be determined by the channel length of the channel a t — the length of the channel of the incoming call 0 ; 4 〇: film thickness. Therefore, the thin film transistor can achieve the increase of the effective axis, such as the filament migration rate. 201218383 Since the source 130 and the immersed 160 挞田 (4) 〇 and 汲 can be selected phase = use different materials. For example, ▲乍' or a separate material may be selected, for example, from metal, through:, pole 13G and pole 160. The transparent conductive material may be indium tin oxide: Two: genus

與汲極刚的材質可以—者為金屬，另—者為透明導j 〇 料’也可以同時為金屬，或是同時為透明導電：电 圖3繪示為本發明第三實施例的薄膜電晶 思圖。請參照圖3 ’薄膜電晶體30G配置於基板^面I =有;於基板1G上的間極liG、閘極絕緣層 、源極130、通道層140以及汲極35〇。另外 晶體300還包括保護層36〇，其覆蓋住源極13〇、通道層 140以及汲極35〇。在本實施例中，源極⑽接觸於通道層 140接近基板1〇的一側’而汲極35〇接觸於通道層14〇遠 離基板10的-側。源極130與沒極35〇在不同製作步驟中 以不同膜層製作而成。因此’源極13〇與汲極35〇的材質 可以彼此相同也可以彼此不同。 此外，源極130與汲極350的相對位置不受製程精度 的限制。源極130接觸通道層14〇的源極接觸區132與汲 極350接觸通道層14〇的汲極接觸區352在平行基板1〇 的水平距_d可以是大於等於零的任何數值。所以，設計 者可以按照所需的元件特性來調整水平距離d的大小以獲 得所需的通道長度。此外，薄膜電晶體3〇〇的閘極11()與 ;及極350之間設有通道層140，因此薄膜電晶體3〇〇的閘 201218383 極·汲極寄生電容較小而具有理想的電性特性。 圖4繪示為本發明第四實施例的薄膜電晶體剖面示意 圖。請參照圖4，薄膜電晶體400配置於基板1〇上，其包 括，閘極11。、_絕緣層12〇、源極13。'通道層14〇、 保，層150以及汲極46〇。薄膜電晶體4〇〇與前述的薄膜 電晶體100大致相同，兩者的主要差異在於汲極460更包 括延伸部462。此外，汲極460的延伸部462例如位於閘 極110以及通道層丨4〇正上方，延伸部462和通道層 之間有保護層150，此結構可產生額外的雙閘極效應，可 以得到更高的電流輸出。 薄膜電Ba體400將源極130與汲極460以不同的膜層 加以製作。所以，源極13〇與汲極46〇的相對位置不受製 程精度的影響。製作薄膜電晶體4〇〇時，可以依照所需的 條件改變源極130與汲極460的相對位置以獲得理想的通 道長度。此外，源極13〇與汲極46〇之間的距離縮小，薄 膜電晶體400的配置面積也隨之縮小，而有助於提升元件 配置密度。 圖5繪示為本發明之一實施例的晝素結構示意圖。請 參照圖5 ’晝素結構5〇〇包括薄膜電晶體51〇以及畫素電 極520。薄膜電晶體51〇包括閘極g、源極s以及汲極D。 晝素電極520電性連接汲極D。具體而言，薄膜電晶體51〇 在剖面上的设計可以採用前述實施例中的薄膜電晶體 100、200、300以及400任一種結構。也就是說，源極s 以及沒極D係由不同膜層製作而成的，且源極s以及汲極 201218383 D的材質可以是相同的或是彼此不同。薄膜電晶體510可 以藉由改變源極S以及汲極D之間的相對位置以實現不同 的通道長度，而不受限於製程精度。因此，薄膜電晶體51〇 可具有理想的電性特性而使晝素結構5〇〇的反應速率符合 所需。 在本實施例中，畫素電極520的材質可以是透明導電 材料也可以是金屬，或是上述材料之組合。晝素電極 可與汲極D同時製作，因此晝素電極52〇的材質可與汲極 D的材質相同。不過，本實施例不侷限於將晝素電極52〇 與汲極D同時製作的實施方式。在其他的實施方式中，晝 素電極520與汲極D可以分別使用不同步驟加以製作。 圖6繪示為本發明第五實施例的薄膜電晶體的示意 圖。請參照圖6，薄膜電晶體600配置於基板10上。薄膜 電晶體600包括閘極11〇、閘極絕緣層12〇、源極13〇、通 道層140、保護層15〇、沒極160以及緩衝層670與680。 閘極110、閘極絕緣層12〇、源極no、通道層14〇、保護 層150以及汲極160之間的相對關係可參照於第一實施例 的相關描述。另外，緩衝層670配置於源極no與通道層 140之間’而缓衝層680配置於汲極160與通道層14〇之 間。具體而言，源極130可以透過緩衝層670連接於通道 層140而汲極160可以透過缓衝層680連接於通道層14〇。 因此’在本實施例中，源極130與汲極16〇可選擇性地不 直接接觸於通道層140 ’而分別接觸於緩衝層670與680。 也就是說’緩衝層670與680分別地夾於源極13〇與通道 201218383 層I40之間以及源極160與通道層i4〇之間。 缓衝層670與680的材質可以是任何半導體，使金屬 材料的源極13G/汲極16G與氧化物半導體材料的通道層 140間形成歐姆接觸的材料，例如奸型摻雜的igz〇。因 此’緩衝層670與680的配置有助於降低源極13〇盥汲極 160連接於通道層14〇的接觸阻抗。緩衝層67〇 * _可 ，分別使用製作_ 130與汲極16〇的光罩加以製作，或 是使用其他的光罩來製作。 值得提的疋，缓衝層670與680可以選擇性地廊用 於前述第-至第四實施例的薄膜電晶體中也可以應用二圖 m素結構中的電晶體中，以降低金屬材料與氧化物半 導體材料之間的接觸阻抗。另外，本實施例的薄膜電晶體 600可以制於其他的電路結構巾，例如圖7所繪示的電 路。圖7的電路結構700包括電晶體710、720以及模相 730、7仙。電晶體71〇例如可以是前述多個實施例中的直 中個相電晶體，且電晶體71〇與72〇可以連接至模组 730以及模組74〇tJ另外，模組73〇與模組74〇例如連接至 電源Vss以及線路G⑻。當然，以上電路結構7〇〇僅是声 例說明-種電路設計而已，上述實施例所描述的薄曰 體可以應祕其他設計方柄電路賴或是晝素結構中。 綜上所述，本發明採用不同膜層分別製作源極與这 極且，極與及極分別在通道層先後製作而成。薄Q 2的=長度不受製_度的限制n賴電晶體名 通迢長度上的設計富有·，其中通道長度甚至可以制 12 201218383 至等於通道層的膜厚。另外，源極與汲極間的水平距離可 以進一步縮減至零而有助於縮小薄膜電晶體的配置面積。 本电明除了可以提尚薄膜電晶體在設計上的彈性外，使用 本發明之薄膜電晶體的晝素結構可以具有理想的反應速 率0 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖u會示為本發明第-實施例的薄膜電晶體剖面示音、 B ° ^ 圖2!會示為本發明第二實施例的薄膜電晶體剖面示竞 SI 〇 意圖 圖。 圖 圖3繪示為本發明第三實施例的薄膜電晶體的剖面示 〇 圖4綠示為本發明第四實施例的面示意 圖5繪示為本發明之一實施例的書夸 ^ λ I結構示意圖。 圖6繪示為本發明第五實施例的_電晶體的示意 構 圖7繪示為本發明一實施例的電路择 201218383 【主要元件符號說明】 ίο:基板 100、200、300、400、510 ' 600 :薄膜電晶體 110、G :閘極 120 :閘極絕緣層 130、S :源極 132 :源極接觸區 140 :通道層 150、250、360 :保護層 152 :孔洞 160、350、460、D :汲極 162、352 :汲極接觸區 462 :延伸部 500 :晝素結構 520 :晝素電極 670、680 :緩衝層 700 :電路結構 710、720 :電晶體 730、740 :模組 d:水平距離The material of the crucible may be metal, and the transparent material may be metal at the same time or transparent at the same time: electrograph 3 shows the thin film of the third embodiment of the present invention. Jing Si map. Referring to Fig. 3, the thin film transistor 30G is disposed on the substrate surface I = Yes; the interpole lithium Li on the substrate 1G, the gate insulating layer, the source 130, the channel layer 140, and the drain 35 〇. Further, the crystal 300 further includes a protective layer 36A covering the source 13A, the channel layer 140, and the drain 35A. In the present embodiment, the source (10) is in contact with the side of the channel layer 140 which is close to the substrate 1 and the gate 35 is in contact with the channel layer 14 from the side of the substrate 10. The source 130 and the gate 35 are fabricated in different layers in different fabrication steps. Therefore, the materials of the source 13 〇 and the drain 〇 35 可以 may be the same as each other or different from each other. In addition, the relative position of the source 130 and the drain 350 is not limited by the process accuracy. The horizontal contact distance _d of the source contact region 132 of the source 130 contacting the channel layer 14〇 and the drain contact region 352 of the drain layer 350 contacting the channel layer 14〇 at the parallel substrate 1〇 may be any value greater than or equal to zero. Therefore, the designer can adjust the horizontal distance d according to the required component characteristics to obtain the desired channel length. In addition, the channel layer 140 is provided between the gate 11() and the electrode 350 of the thin film transistor 3, so that the gate transistor of the thin film transistor 3〇〇201218383 has a small parasitic capacitance and has an ideal electric power. Sexual characteristics. Fig. 4 is a cross-sectional view showing a thin film transistor of a fourth embodiment of the present invention. Referring to FIG. 4, the thin film transistor 400 is disposed on the substrate 1A, which includes the gate 11. , _ insulating layer 12 〇, source 13 . 'Channel layer 14 〇, guarantee, layer 150 and 〇 46 〇. The thin film transistor 4 is substantially the same as the above-described thin film transistor 100, and the main difference between the two is that the drain 460 further includes the extending portion 462. In addition, the extension 462 of the drain 460 is located, for example, directly above the gate 110 and the channel layer 丨4〇. There is a protective layer 150 between the extension 462 and the channel layer. This structure can generate an additional double gate effect, which can be obtained. High current output. The thin film electric Ba body 400 is formed by using a different film layer between the source 130 and the drain 460. Therefore, the relative position of the source 13 〇 and the drain 46 不受 is not affected by the process accuracy. When the thin film transistor is fabricated, the relative positions of the source 130 and the drain 460 can be changed to obtain the desired channel length in accordance with the required conditions. In addition, the distance between the source 13 〇 and the drain 46 缩小 is reduced, and the arrangement area of the thin film transistor 400 is also reduced, which contributes to an increase in component placement density. FIG. 5 is a schematic structural view of a halogen element according to an embodiment of the present invention. Referring to Fig. 5, the unitary structure 5 includes a thin film transistor 51A and a pixel electrode 520. The thin film transistor 51A includes a gate g, a source s, and a drain D. The halogen electrode 520 is electrically connected to the drain D. Specifically, the design of the thin film transistor 51 剖面 in the cross section can adopt any of the thin film transistors 100, 200, 300, and 400 in the foregoing embodiments. That is to say, the source s and the immersion D are made of different layers, and the materials of the source s and the bungee 201218383 D may be the same or different from each other. The thin film transistor 510 can achieve different channel lengths by changing the relative positions between the source S and the drain D without being limited by the process precision. Therefore, the thin film transistor 51 can have desirable electrical characteristics to make the reaction rate of the halogen structure 5 符合 as desired. In this embodiment, the material of the pixel electrode 520 may be a transparent conductive material or a metal, or a combination of the above materials. The halogen electrode can be fabricated at the same time as the drain D. Therefore, the material of the halogen electrode 52〇 can be the same as that of the drain D. However, the present embodiment is not limited to the embodiment in which the halogen electrode 52A and the drain D are simultaneously produced. In other embodiments, the germanium electrode 520 and the drain D can be fabricated using different steps, respectively. Fig. 6 is a view showing a thin film transistor of a fifth embodiment of the present invention. Referring to FIG. 6, the thin film transistor 600 is disposed on the substrate 10. The thin film transistor 600 includes a gate 11A, a gate insulating layer 12A, a source 13A, a channel layer 140, a protective layer 15A, a gate 160, and buffer layers 670 and 680. The relative relationship between the gate 110, the gate insulating layer 12A, the source no, the channel layer 14A, the protective layer 150, and the drain 160 can be referred to the related description of the first embodiment. Further, the buffer layer 670 is disposed between the source no and the channel layer 140, and the buffer layer 680 is disposed between the drain 160 and the channel layer 14A. Specifically, the source 130 may be connected to the channel layer 140 through the buffer layer 670 and the drain electrode 160 may be connected to the channel layer 14 through the buffer layer 680. Therefore, in the present embodiment, the source 130 and the drain 16 are selectively in contact with the channel layer 140' without contacting the buffer layers 670 and 680, respectively. That is, the buffer layers 670 and 680 are sandwiched between the source 13 〇 and the channel 201218383 layer I40 and between the source 160 and the channel layer i4 分别, respectively. The material of the buffer layers 670 and 680 may be any semiconductor such that the source 13G/drain 16G of the metal material forms an ohmic contact with the channel layer 140 of the oxide semiconductor material, such as a doped igz. Therefore, the configuration of the buffer layers 670 and 680 helps to reduce the contact resistance of the source 13 drain 160 connected to the channel layer 14A. The buffer layer 67 〇 * _ can be produced by using a photomask made of _130 and a drain 16 分别, or by using another reticle. It is worth mentioning that the buffer layers 670 and 680 can be selectively used in the thin film transistors of the foregoing first to fourth embodiments, and can also be applied to the transistors in the two-dimensional structure to reduce the metal material and Contact resistance between oxide semiconductor materials. In addition, the thin film transistor 600 of the present embodiment can be fabricated on other circuit construction tissues such as the circuit shown in FIG. The circuit structure 700 of Figure 7 includes transistors 710, 720 and modes 730, 7 sen. The transistor 71 can be, for example, a straight-phase phase transistor in the foregoing plurality of embodiments, and the transistors 71 and 72 can be connected to the module 730 and the module 74〇tJ, and the module 73 and the module 74〇 is connected, for example, to the power source Vss and the line G(8). Of course, the above circuit structure 7 is only an example of a circuit design, and the thin body described in the above embodiment can be applied to other designs of the square handle circuit or the pixel structure. In summary, the present invention uses different film layers to separately fabricate the source and the pole, and the pole and the pole are respectively fabricated in the channel layer. The length of the thin Q 2 is not limited by the degree of the system. The name of the transistor is rich in the length of the pass. The length of the channel can even be 12 201218383 to be equal to the film thickness of the channel layer. In addition, the horizontal distance between the source and the drain can be further reduced to zero to help reduce the area of the thin film transistor. In addition to the design flexibility of the thin film transistor, the halogen structure of the thin film transistor of the present invention can have a desired reaction rate. Although the present invention has been disclosed in the above embodiments, it is not used. The scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is defined by the scope of the appended claims. Subject to it. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a cross-sectional view of a thin film transistor according to a first embodiment of the present invention, and FIG. 2 is a schematic view of a thin film transistor according to a second embodiment of the present invention. Figure. FIG. 3 is a cross-sectional view showing a thin film transistor according to a third embodiment of the present invention. FIG. 4 is a cross-sectional view showing a fourth embodiment of the present invention. FIG. Schematic. 6 is a schematic structural diagram of a transistor according to a fifth embodiment of the present invention. FIG. 7 is a circuit diagram of 201218383 according to an embodiment of the present invention. [Main component symbol description] ίο: substrate 100, 200, 300, 400, 510 ' 600: thin film transistor 110, G: gate 120: gate insulating layer 130, S: source 132: source contact region 140: channel layer 150, 250, 360: protective layer 152: holes 160, 350, 460, D: drain 162, 352: drain contact region 462: extension portion 500: halogen structure 520: halogen electrode 670, 680: buffer layer 700: circuit structure 710, 720: transistor 730, 740: module d: Horizontal distance

Gn :線路 L:通道長度Gn: line L: channel length

Vss :電源Vss: power supply

Claims (1)

201218383 七、申請專利範圍： 體包—種薄膜電晶體，配置於—基板上，該薄膜電晶 —閘極； -閘極絕緣層’覆蓋於該閘極及該基板上； —源極，配置於部份該閘極絕緣層上； -通道層’配置於該_絕緣層上，且覆蓋該問極上 方之部分該源極；以及 一錄，配置於該通道層上且電性連接於該通道層。 2.如申請專利範圍第】項所述之薄膜電晶體，更包 括一緩衝層’配置於該源極與該通道層之間、該没極盘該 通道層之間以降低接觸阻抗。 入一3 中請專利範圍第1項所述之薄膜電晶體，更包 含一保護層，覆蓋該祕、該通道層與該閘極絕緣層，且 該保護層具有至少一孔洞暴露部份通道層。 4.如申請專利範圍第3項所述之薄膜電晶體，其中 該汲極經由該孔洞電性連接該通道層。 5，如申請專利範圍第3項所述之薄膜電晶體，其中 該汲極更包含有一配置於該閘極以及該通道層正上方之延 伸部。 6. 如申請專利範圍第5項所述之薄膜電晶體，其中 該延伸部及該通道層之間具有該保護層。 7. 如申請專利範圍第3項所述之薄膜電晶體，其 中，該孔洞是位於該閘極與該通道層之正上方。 S 15 201218383 利範圍第1項所述之薄膜電晶體，更包 _，覆蓋該源極、該通道層與該及極。 ▲ 9.如申凊專利範圍第8項所述之薄膜電晶體，其中 該通道層更覆蓋該閘極絕緣層上。 一 10.如申請專利範圍第8項所述之薄膜電晶體，其中 該汲極更覆蓋該閘極絕緣層上。 八 11·如申請專利範圍第1項所述之薄膜電晶體，其中 該源極接觸該通道層的一源極接觸區與該汲極通 層的一汲極接觸區在平行於該基板的一水平距離大於等於 零。 ' 12.如申請專利範圍第丨項所述之薄膜電晶體，其中 該源極接觸該通道層的—祕制區與概極接觸該通道 層的一汲極接觸區在平行於該基板的一水平距離小於 3μιη。 η•如申請專利範圍第1項所述之薄膜電晶體，其中 該通道層的材質包括-金屬氧化物半導體、或—非晶砍 導體。 14. 如申請專利範圍第13項所述之薄膜電晶體，其 中s亥金羼氧化物半導體包括銅鎵鋅氧化物。 15. 如申請專利範圍第丨項所述之薄膜電晶體，其中 該沒極的材質包括一透明導電材料。 16. 如申請專利範圍第1項所述之薄膜電晶體，其中 S亥汲極的材質包括金屬。 17. 如申請專利範圍第〗項所述之薄膜電晶體，其中 201218383 該源極與該汲極具有相同的材質。 18. —種晝素結構，包括： 如申請專利範圍第1項所述之薄膜電晶體；以及 一晝素電極，該晝素電極電性連接於該汲極。 19. 如申請專利範圍第18項所述之晝素結構，其中 該晝素電極和該汲極為同一膜層。 20. —種電路結構，包括如申請專利範圍第1項所述 的薄膜電晶體。 S 17201218383 VII, the scope of application for patent: body package - a thin film transistor, placed on the substrate, the film is electro-granular - gate - the gate insulating layer 'covers the gate and the substrate; - source, configuration a portion of the gate insulating layer; a channel layer disposed on the insulating layer and covering a portion of the source above the gate; and a recording portion disposed on the channel layer and electrically connected to the gate layer Channel layer. 2. The thin film transistor according to claim 5, further comprising a buffer layer disposed between the source and the channel layer and between the channel layer of the electrode pad to reduce contact resistance. The thin film transistor of claim 1, further comprising a protective layer covering the secret layer, the channel layer and the gate insulating layer, and the protective layer having at least one hole exposed portion of the channel layer . 4. The thin film transistor of claim 3, wherein the drain is electrically connected to the via layer via the via. 5. The thin film transistor of claim 3, wherein the drain further comprises an extension disposed on the gate and directly above the channel layer. 6. The thin film transistor of claim 5, wherein the protective layer is provided between the extension and the channel layer. 7. The thin film transistor of claim 3, wherein the hole is located directly above the gate and the channel layer. S 15 201218383 The thin film transistor of the first aspect of the invention, further comprising _, covering the source, the channel layer and the sum electrode. ??? 9. The thin film transistor of claim 8, wherein the channel layer further covers the gate insulating layer. 10. The thin film transistor of claim 8, wherein the drain further covers the gate insulating layer. The thin film transistor of claim 1, wherein a source contact region of the source contact the channel layer and a drain contact region of the gate pass layer are parallel to the substrate. The horizontal distance is greater than or equal to zero. 12. The thin film transistor of claim 2, wherein the source contacts the channel layer and the secret region contacts a drain contact region of the channel layer in parallel with the substrate. The horizontal distance is less than 3 μm. The thin film transistor according to claim 1, wherein the material of the channel layer comprises a metal oxide semiconductor or an amorphous cut conductor. 14. The thin film transistor according to claim 13, wherein the sigma gold oxide semiconductor comprises copper gallium zinc oxide. 15. The thin film transistor of claim 2, wherein the non-polar material comprises a transparent conductive material. 16. The thin film transistor according to claim 1, wherein the material of the S-thickness comprises a metal. 17. The thin film transistor of claim 1, wherein the source is the same material as the drain. 18. A halogen structure comprising: a thin film transistor according to claim 1; and a halogen electrode electrically connected to the drain. 19. The alizarin structure of claim 18, wherein the halogen electrode and the crucible are substantially the same film layer. 20. A circuit structure comprising a thin film transistor as described in claim 1 of the patent application. S 17
TW100116496A 2010-10-21 2011-05-11 Thin film transistor and pixel structure having the thin film transistor TWI476931B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW100116496A TWI476931B (en) 2010-10-21 2011-05-11 Thin film transistor and pixel structure having the thin film transistor
US13/180,555 US8304778B2 (en) 2010-10-21 2011-07-12 Thin film transistor and pixel structure having the thin film transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW99136001 2010-10-21
TW100116496A TWI476931B (en) 2010-10-21 2011-05-11 Thin film transistor and pixel structure having the thin film transistor

Publications (2)

Publication Number Publication Date
TW201218383A true TW201218383A (en) 2012-05-01
TWI476931B TWI476931B (en) 2015-03-11

Family

ID=45972209

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100116496A TWI476931B (en) 2010-10-21 2011-05-11 Thin film transistor and pixel structure having the thin film transistor

Country Status (2)

Country Link
US (1) US8304778B2 (en)
TW (1) TWI476931B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9859440B2 (en) 2014-12-03 2018-01-02 Hon Hai Precision Industry Co., Ltd. Thin film transistor and method of manufacturing same

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102779783B (en) * 2012-06-04 2014-09-17 北京京东方光电科技有限公司 Pixel structure, as well as manufacturing method and display device thereof
CN103048840B (en) * 2012-11-12 2015-04-01 京东方科技集团股份有限公司 Array substrate, manufacture method of array substrate, liquid crystal display panel and display device
TWM491180U (en) * 2014-05-08 2014-12-01 Chunghwa Picture Tubes Ltd Thin film transistor and pixel structure
TW201547029A (en) 2014-06-13 2015-12-16 Chunghwa Picture Tubes Ltd Thin film transistor
TW201601220A (en) 2014-06-20 2016-01-01 中華映管股份有限公司 Thin-film transistor and method for manufacturing the same
CN104241392B (en) 2014-07-14 2017-07-14 京东方科技集团股份有限公司 A kind of thin film transistor (TFT) and preparation method thereof, display base plate and display device
CN104157701B (en) * 2014-09-02 2017-09-01 深圳市华星光电技术有限公司 The preparation method and structure of oxide semiconductor TFT substrate
US9325279B1 (en) * 2014-10-06 2016-04-26 Cindy X. Qiu Integrated power device with a metal oxynitride active channel for power switching and microwave amplification
CN107851668B (en) * 2015-07-27 2021-08-06 夏普株式会社 Semiconductor device and method for manufacturing the same
JP2019040026A (en) * 2017-08-24 2019-03-14 株式会社ジャパンディスプレイ Display
CN108010917A (en) 2017-11-02 2018-05-08 中华映管股份有限公司 Active-device array basal plate and preparation method thereof

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849797A (en) * 1987-01-23 1989-07-18 Hosiden Electronics Co., Ltd. Thin film transistor
US5032883A (en) * 1987-09-09 1991-07-16 Casio Computer Co., Ltd. Thin film transistor and method of manufacturing the same
US5283456A (en) * 1992-06-17 1994-02-01 International Business Machines Corporation Vertical gate transistor with low temperature epitaxial channel
KR0165398B1 (en) * 1995-05-26 1998-12-15 윤종용 Vertical transistor manufacturing method
JPH09307114A (en) * 1996-05-17 1997-11-28 Fujitsu Ltd Thin film transistor, manufacture thereof and liquid crystal display device
KR100230595B1 (en) * 1996-12-28 1999-11-15 김영환 Lcd device and its manufactuaring method
KR20000003318A (en) * 1998-06-27 2000-01-15 김영환 Liquid crystal display unit having improving aperature ratio
KR100542310B1 (en) * 1998-12-30 2006-05-09 비오이 하이디스 테크놀로지 주식회사 Thin film transistor liquid crystal display
GB0017471D0 (en) * 2000-07-18 2000-08-30 Koninkl Philips Electronics Nv Thin film transistors and their manufacture
KR100679917B1 (en) * 2000-09-09 2007-02-07 엘지.필립스 엘시디 주식회사 Thin film transistor and the method of fabricating the same
EP1383179A2 (en) * 2002-07-17 2004-01-21 Pioneer Corporation Organic semiconductor device
TW588565B (en) * 2002-10-31 2004-05-21 Au Optronics Corp Active matrix organic light emitting diode and method of manufacturing the same
US7262463B2 (en) * 2003-07-25 2007-08-28 Hewlett-Packard Development Company, L.P. Transistor including a deposited channel region having a doped portion
US7205171B2 (en) * 2004-02-11 2007-04-17 Au Optronics Corporation Thin film transistor and manufacturing method thereof including a lightly doped channel
US7145174B2 (en) * 2004-03-12 2006-12-05 Hewlett-Packard Development Company, Lp. Semiconductor device
US7642573B2 (en) * 2004-03-12 2010-01-05 Hewlett-Packard Development Company, L.P. Semiconductor device
US7211825B2 (en) * 2004-06-14 2007-05-01 Yi-Chi Shih Indium oxide-based thin film transistors and circuits
US7208756B2 (en) * 2004-08-10 2007-04-24 Ishiang Shih Organic semiconductor devices having low contact resistance
US7863611B2 (en) * 2004-11-10 2011-01-04 Canon Kabushiki Kaisha Integrated circuits utilizing amorphous oxides
KR100647660B1 (en) * 2004-11-19 2006-11-23 삼성에스디아이 주식회사 A thin film transistor, and a flat panel display employing the same
TWI279916B (en) * 2005-01-31 2007-04-21 Au Optronics Corp TFT array substrate of a LCD, LCD panel and method of fabricating the same
US7948171B2 (en) * 2005-02-18 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
KR100647683B1 (en) * 2005-03-08 2006-11-23 삼성에스디아이 주식회사 Organic thin film transistor and flat display apparatus comprising the same
EP1724844A2 (en) * 2005-05-20 2006-11-22 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device, manufacturing method thereof and semiconductor device
US7754548B2 (en) * 2006-06-27 2010-07-13 Lg Display Co., Ltd. Thin film transistor, method of fabricating the same, and method of fabricating liquid crystal display device having the same
WO2008008648A2 (en) * 2006-06-29 2008-01-17 University Of Florida Research Foundation, Inc. Short channel vertical fets
US20080024702A1 (en) * 2006-07-27 2008-01-31 Chunghwa Picture Tubes, Ltd. Pixel structure and fabrication method thereof
JP2008091599A (en) * 2006-10-02 2008-04-17 Sony Corp Thin-film transistor, its manufacturing method and display unit
JP5111949B2 (en) * 2007-06-18 2013-01-09 株式会社日立製作所 Thin film transistor manufacturing method and thin film transistor device
US9640666B2 (en) * 2007-07-23 2017-05-02 GlobalFoundries, Inc. Integrated circuit employing variable thickness film
JP2009117619A (en) * 2007-11-06 2009-05-28 Idemitsu Kosan Co Ltd Method for manufacturing organic thin film transistor, and organic thin film transistor
US8049215B2 (en) * 2008-04-25 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor
JP4466763B2 (en) * 2008-05-14 2010-05-26 ソニー株式会社 Pattern forming method, semiconductor device manufacturing method, and display device manufacturing method
KR101547325B1 (en) * 2008-10-27 2015-08-26 삼성전자주식회사 Transistor and semiconductor device comprising the same
CN105552129B (en) * 2008-11-07 2019-05-28 株式会社半导体能源研究所 Semiconductor devices
US8114720B2 (en) * 2008-12-25 2012-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR101649225B1 (en) * 2009-03-24 2016-08-18 엘지디스플레이 주식회사 Organic Light Emitting Display Device and Method for fabricating the same
US8314421B2 (en) * 2009-06-01 2012-11-20 Qiu Cindy X Thin film transistors and circuits with metal oxynitride active channel layers
KR20110066370A (en) * 2009-12-11 2011-06-17 한국전자통신연구원 Oxide thin film transistor and method for manufacturing the same
KR101863941B1 (en) * 2010-06-08 2018-06-04 삼성디스플레이 주식회사 Thin film transistor with offset structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9859440B2 (en) 2014-12-03 2018-01-02 Hon Hai Precision Industry Co., Ltd. Thin film transistor and method of manufacturing same
TWI624874B (en) * 2014-12-03 2018-05-21 鴻海精密工業股份有限公司 Vertical transistor and method for manufacturing same

Also Published As

Publication number Publication date
TWI476931B (en) 2015-03-11
US8304778B2 (en) 2012-11-06
US20120097955A1 (en) 2012-04-26

Similar Documents

Publication Publication Date Title
TW201218383A (en) Thin film transistor and pixel structure having the thin film transistor
CN1913146B (en) Thin film conductor and method of fabrication
CN104752420B (en) The anti static device and its manufacture method of display device
US8791459B2 (en) Array substrate, manufacturing method of the same, and fabricating method of display device including the array substrate
US8853699B2 (en) Thin film transistor and method of forming the same
TW201005950A (en) Thin film transistor and method of manufacturing the same
US9632382B2 (en) Array substrate comprising a barrier layer pattern and the method for manufacturing the same, and liquid crystal display device
KR20100075026A (en) Thin film transistor array substrate and method of fabricating the same
TWI297548B (en) Pixel structure for flat panel display and method for fabricating the same
WO2014183422A1 (en) Thin-film transistor and preparation method therefor, and array substrate
KR20100076638A (en) Thin film transistor array substrate for x-ray detector and method of fabricating the same
US10510558B2 (en) Electronic device, thin film transistor, array substrate and manufacturing method thereof
TW200818510A (en) Thin film transistor array substrate, method of manufacturing the same, and display device
CN109638078B (en) TFT preparation method, TFT, OLED backboard and display device
US10833104B2 (en) Array substrate and its fabricating method, display device
US20120161131A1 (en) Thin-film transistor substrate and method of manufacturing the same
CN111244110B (en) Display panel and electronic device
TWI479574B (en) Tft array substrate and method for manufacturing the same
KR20120017352A (en) Thin film transistor panel and method of manufacturing for the same
US20080277721A1 (en) Thin film transistor, pixel structure and fabricating method thereof
US20150115273A1 (en) Array substrate, method for manufacturing the same and display device
TW200915573A (en) Thin film transistor, pixel structure and fabricating methods thereof
KR20020052562A (en) In-plane switching mode liquid crystal device and method for manufacturing the same
WO2016000363A1 (en) Low temperature poly-silicon thin film transistor array substrate and manufacturing method therefor and display device
CN110190071A (en) Display base plate and preparation method thereof, display device