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TW201142320A - Burn-in board, burn-in device and burn-in system (2) - Google Patents

Burn-in board, burn-in device and burn-in system (2) Download PDF

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Publication number
TW201142320A
TW201142320A TW099123266A TW99123266A TW201142320A TW 201142320 A TW201142320 A TW 201142320A TW 099123266 A TW099123266 A TW 099123266A TW 99123266 A TW99123266 A TW 99123266A TW 201142320 A TW201142320 A TW 201142320A
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TW
Taiwan
Prior art keywords
test
programmable logic
burn
burning
under test
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TW099123266A
Other languages
Chinese (zh)
Inventor
Akimasa Yuzurihara
Takeshi Kumagai
Kazuhiko Sato
Original Assignee
Japan Engineering Co Ltd
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Publication date
Application filed by Japan Engineering Co Ltd filed Critical Japan Engineering Co Ltd
Publication of TW201142320A publication Critical patent/TW201142320A/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Environmental & Geological Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The subject of the present invention is to reduce the overall time required for burn-in test. The burn-in board of the present invention includes: a plurality of programmable logic devices capable of varying the circuit structure based on the configuration data; and a plurality of sockets, which can be installed with devices under test and are connected to any one of the plurality of programmable logic devices, each of the plurality of programmable logic devices being connected to the plurality of sockets. Furthermore, each of the plurality of programmable logic devices is at least formed with circuit and memory according to the configuration data given before burn-in test. The circuit generates a test pattern for being supplied to the devices under test that have been installed in the sockets when proceeding with the burn-in test. From the plurality of devices under test connected to the programmable logic devices, the memory reads in parallel the output signals of the devices under test that have been installed in the sockets when proceeding with the burn-in test, and compares the same with a logic value. Then, the comparison result is used as a test result for being stored.

Description

201142320 六、發明說明： I：發明戶斤屬之技術領域3 技術領域 本發明係有關於一種預燒板、預燒裝置及預燒系統， 特別係有關於一種進行半導體裝置之預燒試驗的預燒板、 預燒裝置及預燒系統。 c先前技冬好3 背景技術 作為進行用以將電子零件等半導體裝置的初期故障 (initial failure)顯著化，而去除早期故障品之篩選試驗之一 種的預燒(Burn-In)試驗的裝置，係已知有預燒裝置。該預 燒裝置係半導體測試裝置之一種，將安裝有複數的受測裝 置(Device Under Test)之半導體裝置的預燒板收容於預燒 裝置内，並對受測裝置施加電壓而賦予電應力（electric stress)，並且同時對恆溫槽内部的空氣加熱而賦予預定溫度 的熱應力（thermic stress)，藉此使初期不良顯著化。又，在 該預燒試驗中，進行試驗如下，即，對受測裝置提供預定 的測試信號，進行受測裝置的動作測試，來測試受測裝置 是否有正常動作。 由於此種預燒裝置會連續進行長達數小時至數十小時 的預燒試驗，因此為了提高試驗效率，一般會將複數的受 測裝置安裝於1片預燒板，並且同時將複數的該預燒板收納 於預燒裝置來進行預燒試驗（可參照例如特開2005-265665 號公報）。 201142320 進行預燒試驗之際所需的測試型樣信號係由預燒裝置 所產生’並供給至安裝於預燒板上的受測裝置。而且，根 據該測試型樣信號使受測裝置進行動作後，預燒裝置會從 預燒板讀取來自受測裝置的其動作結果之輸出信號。預燒 裝置會將業經讀取的輸出信號與邏輯值作比較，來判定受 測裝置是否有正常動作。判定結果係顯示出例如，受測裝 置是否通過預燒試驗，且該判定結果會作為試驗結果而依 序累積於預燒裝置内的記憶體。又，該判定結果會作為試 驗結果而顯示於例如設置於預燒裝置的顯示器。 但是，由於受測裝置之半導體裘置的小型化，可裝載 於1片預燒板上的受測裝置數量因而增加。又，若在1片預 燒板上安裝多數受測裝置，便可謀求縮短整體預燒試驗時 間，且可謀求抑制製造成本。因此，增加可安裝於1片預燒 板上的受測裝置數量一事，可說是一般的期望。 另一方面，連接預燒裝置與預燒板的連接部之接腳(pin) 的數量係受到限制。因此，從預燒裝置對位於預燒板上的 所有受測裝置同時提供測試信號，且同時讀取輸出信號一 事，事實上是不可能的。因此，係將裝載於丨片預燒板上的 複數受測裝置區分成每一預定數量的受測裝置，構成複數 群組，且以群組單位依序對受測裝置提供測試信號，並且 同時由預燒裴置讀取來自受測裝置之輸出信號，進行動作 判疋並累積判定結果。即’必須依序切換每一群組，讀取 來自受測裝置之輸出信號，來進行預燒試驗。因此，增加 每1片預燒板所能安裝的受測裝置數量一事，係意指群組數 201142320 增加，且意指預燒試驗所需時間會變長。 又’裝載於預燒板上的受測裝置的數量若增加，則用 ^對受翁置提㈣試信錢錢㈣的數量亦會增加。 域配線的數量若增加’則錢配線的分歧數會變多，造 成信號波形容易產生失真(—叫。為了修正信號波形= 產生的失真’就必縣進行賴試驗之際，將供給至受測 裝置的時鐘頻率（clock frequency)抑制到很低，這也是造成 拉長預燒試驗所需時間的主要原因。 明内容】 發明揭示 發明欲解決之課題 因此’本發明係有鑑於前述課題而作成者，其目的在 於提供一種可謀求縮短預燒試驗所需時間的預燒板、預燒 裴置及預燒系統。 解決課題之手段 為解決前述課題，本發明之預燒板之特徵在於包含有： 複數可程式邏輯裝置’係根據組態資料而可變更電路 結構者，及 複數插座’係可安裝受測裝置，且連接於任一前述複 數可程式邏輯裝置者， 各前述複數可程式邏輯裝置均連接有複數的前述插 座， 每前述複數可程式邏輯裝置係根據在預燒試驗前供給 之組態資料，而至少形成有電路及記憶體，該電路係生成 201142320 供給至當進行預燒試驗之際已安裝於前述插座之受測裝置 的測試型樣者，該記憶體係從連接於該可程式邏輯裝置的 複數受測裝置，並行地讀取來自當進行預燒試驗之際已安 裝於前述插座之受測裝置的輸出信號並與邏輯值作比較， 然後將其結果作為試驗結果來加以儲存者。 此時，可構造成：前述組態資料係從設置於插入有該 預燒板之預燒裝置的測試控制裝置供給至前述可程式邏輯 裝置。 此外，可構造成：儲存於前述記憶體的前述試驗結果 係藉由前述測試控制裝置來讀取。 再者，可構造成：輸入來自前述受測裝置之輸出信號 的前述可程式邏輯裝置的I/O接腳、與供前述受測裝置輸出 輸出信號的插座的I/O接腳之間，係以1對1的對應關係連 接，且前述受測裝置輸出的輸出信號係並行地同時由可程 式邏輯裝置讀取。 此時，可構造成：供前述可程式邏輯裝置輸出前述測 試型樣信號的驅動接腳、與用以對前述受測裝置輸入前述 測試型樣信號的插座的驅動接腳之間，亦係以1對1的對應 關係連接。 或著，可構造成：供前述可程式邏輯裝置輸出前述測 試型樣信號的驅動接腳、與用以對前述受測裝置輸入前述 測試型樣信號的插座的驅動接腳之間，係屬對前述可程式 邏輯裝置之1根驅動接腳連接有複數驅動接腳的關係。 又，可構造成：前述記憶體内可儲存作為前述試驗結 201142320 果貝:"亥貝λ係顯示出受測裂置是否通過預燒試驗者。 或著，可構造忐.< χ ’則述記憶體内可儲存作為前述試驗 結果之資訊，該資訊係特定出受測裝置料良區塊者。 本毛月之預燒袭置，係可插入1或複數預燒板者，其特 徵在於： 前述預燒板包含有： 複數可私式遊輯敦置，係根據組態資料而可變更電路 結構者；及 複數插座’係可安褒受測裝置，且連接於任-前述複 數可程式邏輯裝置者， 月j述預k板的各前述複數可程式邏輯裝置均連接有複 數的前述插座，並且同時， X預k裝置^在f貞燒試驗射憎述複數可程式邏輯裝 置供給組態資料， 而在各前述複數可程式邏輯裝置形成電路及記憶體， 该電路係生成供給至當進行預燒試驗之際已安裝於前述插 座之受測裝置的測試型樣者，該記憶體係從連接於該可程 式邏輯裝置的複數受測裝置，並行地讀取來自當進行預燒 試驗之際已安裝於前述插座之受測裝置的輸出信號並與邏 輯值作比較，然後將其結果作為試驗結果來加以儲存者。 本發明之預燒系統，係包含有：1或複數預燒板、及可 插入前述預燒板的預燒裝置者，其特徵在於： 前述預燒板包含有： 複數可程式邏輯裝置’係根據組態資料而可變更電路 201142320 結構者；及 複數插座，係可安裝受測裝置，且連接於任一前述複 數可程式邏輯裝置者， 前述預燒板的各前述複數可程式邏輯裝置均連接有複 數的前述插座，並且同時， 前述預燒裝置會在預燒試驗前對前述複數可程式邏輯 裝置供給組態資料， 而在各前述複數可程式邏輯裝置形成電路及記憶體， 该電路係生成供給至當進行預燒試驗之際已安裝於前述插 座之丈測裝置的測試型樣者，該記憶體係從連接於該可程 式邏輯裝置的複數受測裝置，並行地讀取來自當進行預燒 試驗之際已安裝於前述插座之受測裝置的輸出信號並與邏 輯值作比較，然後將其結果作為試驗結果來加以儲存者。 本發明之預燒裝置之控制方法，該預燒裝置係插入 複數預燒板者法， 前述預燒板包含有： 複數可程式邏輯裝置，係根據組態資料而可變更電路 結構者；及 複數插座’係可安裝受測裝置，且連接於任—前述複 數可程式邏輯裝置者， 且前述預燒板的各前述複數可程式邏輯裝置均連接有 複數的前述插座， 該控制方法之特徵在於： 在預燒試驗前’從前述預燒裝置對前述複數可程式邏 201142320 輯裝置供給組態資料， 在各前述複數可程式邏輯裝置形成電路及記憶體，該 電路係生成供給至當進行預燒試驗之際已安裝於前述插座 之受測裝置的測試型樣者，該記憶體係從連接於該可程式 邏輯裝置的複數受測裝置，並行地讀取來自當進行預燒試 驗之際已安裝於前述插座之受測裝置的輸出信號並與邏輯 值作比較，然後將其結果作為試驗結果來加以儲存者。 本發明之預燒系統之控制方法之發明，該預燒系統係 包含有1或複數預燒板、及可插人前述預燒板的預燒裝置 者， 前述預燒板包含有： 複數可私式邏輯裝置’係根據組態資料而可變更電路 結構者；及 複數插座’係可安裝受測裝置，且連接於任一前述複 數可程式邏輯裝置者， 且前述預燒板的各前述複數可程式邏輯裝置均連接有 複數的前述插座， 該控制方法之特徵在於： 在預燒試驗前’從前述預燒裝置對前述複數可程式邏 輯裝置供給組態資料， 在各前述複數可程式邏輯裝置形成電路及記憶體，該 電路係生成供給至當進行預燒試驗之際已安裂於前述插座 之受測裝置的測試型樣者，該記憶體係從連接於气可疒式 邏輯裝置的複數受測裝置並行地讀取來自當進行預_>式驗 201142320 之際已安裝於前述插座之受測裝置的輸出信號並與邏輯值 作比較，然後將其結果作為試驗結果來加以儲存者。 圖式簡單說明 第1圖係本發明之一實施形態之預燒系統中的預燒裝 置之整體正視圖。 第2圖係用以說明在第1圖之預燒裝置内收納有預燒板 之狀態下的内部結構之一例的正視配置圖。 第3圖係顯示在第1圖之預燒裝置中，用以使必要的控 制信號或輸出信號在預燒裝置與受測裝置之間往返的内部 結構之一例的方塊圖。 第4圖係本發明之一實施形態之預燒板的俯視配置圖。 第5圖係說明使用組態資料對設置於預燒板上的可程 式邏輯裝置之内部電路進行設定時的電路結構之一例的方 塊圖。 第6圖係說明在第1圖之預燒系統中實行的預燒試驗實 行順序内容之一例的流程圖。 第7圖係作為第2實施形態來說明預燒板之變形例的預 燒板之正視配置圖。 第8圖係作為第3實施形態來說明使用組態資料對設置 於預燒板上的可程式邏輯裝置之内部電路進行設定時的電 路結構之一例的方塊圖。 L實施方式3 實施發明之最佳形態 以下，參照圖式來說明本發明之實施形態。另外，以 10 201142320 下說明之實施形態並不會對本發明之技術範圍造成限定。 [第1實施形態] 第1圖係本發明之一實施形態的預燒裝置10的整體正 視圖，顯示出門20關閉的狀態。第2圖係用以說明預燒裝置 10之内部結構之要部的正視配置圖，顯示出預燒裝置10内 插入有預燒板BIB的狀態。該等第1圖及第2圖所示之預燒裝 置10係半導體測試裝置之一種，且係藉由預燒裝置10及預 燒板BIB來構成本實施形態之預燒系統。 如該等第1圖及第2圖所示，本實施形態之預燒裝置1〇 的内部’透過業經隔熱壁30區隔之空間，形成有箱室40。 該箱室40之内部可收納1或複數的預燒板8出。 本實施形態中’如第2圖所示，每一載架CR均有預燒 板BIB收納於箱室40。即’各載架cr均形成有用以支撐預 燒板BIB的插槽50’且載架CR係在預燒板BIB插入至該插槽 5〇的狀態下，收藏於箱室40。本實施形態中，係構造成is 載架CR内可插入15片預燒板扭^。 又’本實施形態中’係構造成可將4台載架cr收藏於 箱至40。因此，藉由將4台載架CR收藏於箱室40，便可將 總計60片的預燒板BIB收納於箱室4〇内。惟，可收納於該箱 室4〇内的載架CR之台數或配置、載架CR_預燒板mB之 片數或配置，均可任意變更。 此外，亦可構造成不使用载架CR，而是將預燒板mB 直接收納於箱室40内。此時，將變成在箱室40内形成插槽 50，且將預燒板BIB直接插入至該插槽5〇。 11 201142320 如第1圖所示，該預燒裝置10設有2扇門20 ’且係構造 成藉由使門20呈現開啟狀態，便可使載架CR從箱室4〇出 入。又，該門20亦裝入有隔熱材’藉由使門20呈現關閉狀 態，便可構成一自周圍隔熱之空間的箱室40 ° 此外，如第2圖所示，本實施形態之預燒裝置10設有加 熱器60、及冷卻單元70〇又，箱室40内設有一延伸於其左 側、上側、右側的空氣循環通道DT，藉由設置於該空氣循 環通道DT的風扇80,令空氣循環通道DT内的空氣循環，而 構造成可對空氣進行循環、攪拌，以使箱室内的溫度均一 化。 冷卻單元70係由2台冷卻壓縮機72、及2台熱交換器74 所構成。本實施形態中，該冷卻單元70係採用利用冷媒的 冷卻方式。冷卻壓縮機72係用以循環冷媒的壓縮機，熱交 換器74係用以將冷媒的冷熱與箱室40内部的空氣進行交換 的交換器。2台熱交換器74係設置於空氣循環通道DT内。 因此，透過風扇70使空氣循環’藉此令業經循環之空氣在 熱交換器74進行冷卻，便可降低箱室40的内部溫度。 又，加熱器60係由例如電熱器所構成’其係構造成對 加熱器60供電便會發熱。在加熱器6〇發熱的狀態下’藉由 使空氣循環通道DT内的空氣循環’便可提高箱室40内的空 氣溫度。 另一方面，預燒裝置10的右側設有控制部CL。該控制 部CL係依據預定的設定或順序，控制該預燒裝置10來進行 預燒試驗。本實施形態中’係特別構造成在進行預燒試驗201142320 VI. Description of the invention: I: Technical field of inventions 3 Technical Field The present invention relates to a pre-burning plate, a pre-burning device and a pre-burning system, in particular to a pre-burning test for a semiconductor device. Burning plate, pre-burning device and pre-burning system. C. The prior art is a device for performing a burn-in test for removing an initial failure of a semiconductor device such as an electronic component and removing a screening test for an early defective product. A pre-burning device is known. The burn-in device is a type of semiconductor test device in which a burn-in board of a semiconductor device in which a plurality of device under test devices are mounted is housed in a burn-in device, and a voltage is applied to the device under test to impart electrical stress ( At the same time, the air inside the thermostatic chamber is heated to impart a thermomic stress at a predetermined temperature, whereby the initial failure is remarkable. Further, in the burn-in test, the test is performed by providing a predetermined test signal to the device under test and performing an operation test of the device under test to test whether or not the device under test has a normal operation. Since the pre-burning device continuously performs a calcination test for several hours to several tens of hours, in order to improve the test efficiency, a plurality of devices to be tested are generally mounted on one pre-burning plate, and at the same time, the plurality of pre-burning plates are simultaneously The calcining plate is stored in a calcining apparatus to perform a calcination test (see, for example, JP-A-2005-265665). 201142320 The test pattern signal required for the pre-firing test is generated by the pre-burning device and supplied to the device under test mounted on the pre-burning plate. Further, after the device under test is operated according to the test pattern signal, the burn-in device reads the output signal of the operation result from the device under test from the burn-in board. The burn-in device compares the read output signal with a logic value to determine if the device under test has normal operation. The result of the determination shows, for example, whether or not the device under test passes the burn-in test, and the result of the determination is accumulated as a result of the test in the memory in the burn-in device. Further, the result of the determination is displayed as a test result, for example, on a display provided in the burn-in device. However, due to the miniaturization of the semiconductor device of the device under test, the number of devices under test that can be loaded on one pre-burning plate is thus increased. Further, when a large number of devices to be tested are mounted on one pre-burning plate, the overall burn-in test time can be shortened, and the manufacturing cost can be suppressed. Therefore, it is a general expectation to increase the number of devices to be tested that can be mounted on one piece of pre-fired board. On the other hand, the number of pins connecting the connection portions of the burn-in device and the burn-in board is limited. Therefore, it is virtually impossible to simultaneously supply the test signals from all the devices under test on the pre-burning device from the pre-burning device and simultaneously read the output signals. Therefore, the plurality of devices under test on the enamel pre-burning plate are divided into each predetermined number of devices under test to form a plurality of groups, and the test signals are sequentially supplied to the device under test in groups, and at the same time The output signal from the device under test is read by the pre-burning device, and the operation is judged and the determination result is accumulated. That is, each group must be switched in order, and the output signal from the device under test is read to perform the burn-in test. Therefore, increasing the number of devices to be tested per one piece of pre-fired plate means that the number of groups 201142320 increases, and means that the time required for the burn-in test becomes longer. In addition, if the number of devices under test on the burn-in board increases, the number of money (4) for the testimony (4) will also increase. If the number of domain wirings increases, the number of divergence of the money wiring will increase, causing the signal waveform to be easily distorted (-called. In order to correct the signal waveform = the distortion generated), the county will supply the test to the test. The clock frequency of the device is suppressed to a very low level, which is also the main cause of the time required for the elongated burn-in test. The present invention discloses the problem to be solved by the invention. Therefore, the present invention is made in view of the aforementioned problems. An object of the present invention is to provide a calcining plate, a calcining device, and a calcining system which can reduce the time required for a calcination test. The object of the invention is to solve the above problems, and the calcining plate of the present invention is characterized by comprising: The plurality of programmable logic devices are those that can change the circuit structure according to the configuration data, and the plurality of sockets can be installed with the device under test, and are connected to any of the plurality of programmable logic devices, and each of the plurality of programmable logic devices A plurality of the aforementioned sockets are connected, and each of the plurality of programmable logic devices is configured according to a configuration data supplied before the burn-in test. Forming at least a circuit and a memory for generating a test pattern supplied to the device under test of the socket when the pre-burn test is performed, the memory system is from a plurality of connected to the programmable logic device The device under test reads the output signal from the device under test installed in the socket at the time of performing the burn-in test in parallel and compares it with the logical value, and then stores the result as a test result. The configuration data may be configured to be supplied from the test control device provided in the burn-in device in which the pre-burning plate is inserted to the programmable logic device. Further, the configuration may be configured to: store the test result stored in the memory. And being read by the test control device. Further, the I/O pin of the programmable logic device inputting the output signal of the device under test and the socket for outputting the output signal of the device under test may be configured. The I/O pins are connected in a one-to-one correspondence, and the output signals output by the device under test are simultaneously programmable by the programmable logic. At this time, the device can be configured to: a driving pin for outputting the test pattern signal by the programmable logic device, and a driving pin of a socket for inputting the test pattern signal to the device under test And may be connected in a one-to-one correspondence. Alternatively, it may be configured to: a driving pin for outputting the test pattern signal by the programmable logic device, and inputting the foregoing test pattern to the device under test The driving pin of the signal socket is connected to the driving pin of the programmable logic device by a plurality of driving pins. Further, the memory can be configured to be stored in the memory as the test node 201142320. Fruit shell: "Haibei λ system shows whether the tested crack passes the pre-burning test. Or, can construct 忐.< χ 'The memory can be stored as information of the above test results, the information system A specific block of the device under test is specified. The pre-burning attack of the Maoyue is capable of inserting 1 or a plurality of pre-burned boards, and the characteristics thereof are as follows: The pre-burning board includes: a plurality of privately-held travel magazines, which can change the circuit structure according to the configuration data. And the plurality of sockets can be connected to the device to be tested, and are connected to any of the plurality of programmable logic devices, and each of the plurality of programmable logic devices of the pre-k board is connected with a plurality of the aforementioned sockets, and At the same time, the X pre-k device is configured to supply the configuration data to the complex programmable logic device, and the circuit and the memory are formed in each of the plurality of programmable logic devices, and the circuit generates the supply to the pre-burning. At the time of the test, the test type of the device under test of the socket is installed, and the memory system is read from the plurality of devices under test connected to the programmable logic device in parallel, and is installed on the time when the burn-in test is performed. The output signal of the device under test of the aforementioned socket is compared with a logical value, and the result is stored as a test result. The pre-burning system of the present invention comprises: 1 or a plurality of pre-burning plates, and a pre-burning device insertable into the pre-burning plate, wherein: the pre-burning plate comprises: a plurality of programmable logic devices' The configuration data can be changed by the circuit 201142320; and the plurality of sockets can be installed with the device under test, and connected to any of the plurality of programmable logic devices, wherein each of the plurality of programmable logic devices of the pre-burning plate is connected a plurality of the aforementioned sockets, and at the same time, the pre-burning device supplies configuration data to the plurality of programmable logic devices before the burn-in test, and forms a circuit and a memory in each of the plurality of programmable logic devices, the circuit generates a supply The test pattern of the measuring device that has been installed in the socket at the time of performing the burn-in test, the memory system is read in parallel from the plurality of devices under test connected to the programmable logic device. The output signal of the device under test installed in the above socket is compared with the logic value, and the result is used as a test result. Survivors. The method for controlling a pre-burning device according to the present invention, wherein the pre-burning device is inserted into a plurality of pre-burning plate methods, wherein the pre-burning plate comprises: a plurality of programmable logic devices, wherein the circuit structure can be changed according to the configuration data; The socket is configured to mount a device under test and is connected to any of the plurality of programmable logic devices, and each of the plurality of programmable logic devices of the pre-burning plate is connected to a plurality of the sockets. The control method is characterized by: Before the pre-combustion test, the configuration data is supplied to the plurality of programmable logic devices 201142320 from the pre-burning device, and the circuit and the memory are formed in each of the plurality of programmable logic devices, and the circuit is generated and supplied to the pre-burn test. a test pattern of a device under test having been installed in the socket, the memory system being read in parallel from a plurality of devices under test connected to the programmable logic device from the time when the burn-in test is performed The output signal of the device under test of the socket is compared with the logic value, and the result is stored as a test result. The invention relates to a method for controlling a calcination system according to the present invention. The pre-burning system comprises one or a plurality of pre-burning plates, and a pre-burning device capable of inserting the pre-burning plate, wherein the pre-burning plate comprises: The logic device 'can change the circuit structure according to the configuration data; and the plurality of sockets can be installed with the device under test and connected to any of the plurality of programmable logic devices, and each of the foregoing plurality of pre-burning plates can be The program logic device is connected with a plurality of the foregoing sockets, and the control method is characterized in that: before the burn-in test, the configuration data is supplied to the plurality of programmable logic devices from the pre-burning device, and the plurality of programmable logic devices are formed in each of the plurality of programmable logic devices. a circuit and a memory for generating a test pattern supplied to a device under test that has been cracked at the socket when the burn-in test is performed, the memory system being tested from a plurality of connected to the gas-switchable logic device The device reads the output signals from the device under test installed in the aforementioned socket when the pre-test is performed 201142320 and compares it with the logic value, and then The result is stored as a test result. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a front elevational view showing a pre-burning apparatus in a burn-in system according to an embodiment of the present invention. Fig. 2 is a front elevational view showing an example of an internal structure in a state in which a calcining plate is housed in the calcining apparatus of Fig. 1. Fig. 3 is a block diagram showing an example of an internal structure for reciprocating a necessary control signal or output signal between the burn-in device and the device under test in the burn-in device of Fig. 1. Fig. 4 is a plan view showing a plan view of a burn-in board according to an embodiment of the present invention. Fig. 5 is a block diagram showing an example of a circuit configuration when an internal circuit of a programmable logic device provided on a burn-in board is set using a configuration data. Fig. 6 is a flow chart showing an example of the sequence of the pre-firing test performed in the burn-in system of Fig. 1. Fig. 7 is a front elevational view showing a pre-burning plate of a modified example of the burn-in plate as a second embodiment. Fig. 8 is a block diagram showing an example of a circuit configuration when an internal circuit of a programmable logic device provided on a burn-in board is set using a configuration data as a third embodiment. L. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. Further, the embodiment described in the following 10 201142320 does not limit the technical scope of the present invention. [First Embodiment] Fig. 1 is an overall front view of a calcining apparatus 10 according to an embodiment of the present invention, showing a state in which the door 20 is closed. Fig. 2 is a front elevational view showing the main part of the internal structure of the calcining apparatus 10, showing a state in which the burn-in board BIB is inserted into the calcining apparatus 10. The burn-in device 10 shown in Figs. 1 and 2 is a type of semiconductor test device, and the burn-in system of the present embodiment is constituted by the burn-in device 10 and the burn-in board BIB. As shown in the first and second figures, the interior of the calcining apparatus 1A of the present embodiment is formed by a space partitioned by the heat insulating wall 30 to form a tank chamber 40. The inside of the chamber 40 can accommodate one or a plurality of pre-burning plates 8 out. In the present embodiment, as shown in Fig. 2, each of the carriers CR has a pre-burning plate BIB housed in the case 40. That is, each of the carriers cr forms a slot 50' for supporting the pre-burning plate BIB, and the carrier CR is housed in the case 40 in a state where the pre-burning plate BIB is inserted into the slot 5''. In the present embodiment, it is configured such that 15 pieces of pre-fired plate twists can be inserted into the is-loaded frame CR. Further, in the present embodiment, it is configured such that four carriers cr can be stored in the case 40. Therefore, by storing the four carriers CR in the casing 40, a total of 60 pre-burning plates BIB can be accommodated in the casing 4. However, the number or arrangement of the carriers CR that can be accommodated in the chamber 4, and the number or arrangement of the carriers CR_the pre-burning plates mB can be arbitrarily changed. Further, it is also possible to configure the pre-burning plate mB to be directly housed in the casing 40 without using the carrier CR. At this time, the slot 50 is formed in the box chamber 40, and the burn-in board BIB is directly inserted into the slot 5''. 11 201142320 As shown in Fig. 1, the burn-in device 10 is provided with two doors 20' and is configured to allow the carrier CR to be ejected from the chamber 4 by bringing the door 20 into an open state. Further, the door 20 is also provided with a heat insulating material. By closing the door 20, a box 40° from a space for heat insulation of the surroundings can be formed. Further, as shown in Fig. 2, the present embodiment is The pre-burning device 10 is provided with a heater 60 and a cooling unit 70. The chamber 40 is provided with an air circulation passage DT extending on the left side, the upper side and the right side thereof. The fan 80 is disposed on the air circulation passage DT. The air in the air circulation passage DT is circulated, and is configured to circulate and agitate the air to uniformize the temperature inside the tank. The cooling unit 70 is composed of two cooling compressors 72 and two heat exchangers 74. In the present embodiment, the cooling unit 70 is a cooling method using a refrigerant. The cooling compressor 72 is a compressor for circulating a refrigerant, and the heat exchanger 74 is an exchanger for exchanging the cold heat of the refrigerant with the air inside the tank chamber 40. Two heat exchangers 74 are disposed in the air circulation passage DT. Therefore, the air is circulated by the fan 70, whereby the circulating air is cooled in the heat exchanger 74, whereby the internal temperature of the chamber 40 can be lowered. Further, the heater 60 is constituted by, for example, an electric heater, which is configured to generate heat when the heater 60 is supplied with power. The air temperature in the chamber 40 can be increased by circulating the air in the air circulation passage DT in a state where the heater 6 is heated. On the other hand, the control unit CL is provided on the right side of the calcining apparatus 10. The control unit CL controls the burn-in device 10 to perform a burn-in test in accordance with a predetermined setting or sequence. In the present embodiment, the structure is specially constructed to perform a burn-in test.

12 201142320 之際彳二制加熱器6〇或冷卻單元7〇，使預燒板bib周圍的溫 度成為使用者等所設定的目標溫度。又，詳細内容有待後 述’控制部CL係當進行預燒試驗之際，在定義出可程式邏 輯裝置的電路結構後，在該可程式邏輯裝置進行預燒試 驗’然後’進行讀取各受測装置之判定結果的預燒試驗實 行順序來作為試驗結果。 第3圖係顯示用以使必要的控制信號或輸出信號在預 燒裝置10與受測裝置之間往返的内部結構之一例的方塊 圖。如該第3圖所示’預燒裝置1〇設有測試控制裝置1〇〇、 緩衝板110、驅動板12〇、延伸板(extensi〇n board)130。該等 測試控制裝置1〇〇與緩衝板11〇係設在例如控制部CL的内 部’驅動板120與延伸板130係設在箱室40内。 測試控制裝置1〇〇係在該預燒裝置1〇所進行的預燒試 驗中’進行整體性控制。本實施形態中，該測試控制裝置 100係由例如設於前述控制部CL的個人電腦等獨立電腦所 構成。預燒試驗係依據該測試控制裝置1〇〇的控制來實行。 實行預燒試驗所需的控制信號會經由輸出緩衝器之緩衝板 110輸出至複數的驅動板120。 驅動板120與延伸板130係對應各插槽50而配設在箱室 40内。即，本實施形態中，對應1片預燒板BIB設有1組驅動 板120與延伸板no。因此，第1圖及第2圖所示之預燒裝置 1〇中’設有60組驅動板120與延伸板130。供給至驅動板120 的控制信號會經由延伸板130，最後供給至預燒板BIB。 相反地’自預燒板BIB輸出的試驗結果相關資料等的輸12 201142320 The second heating heater 6〇 or the cooling unit 7〇 causes the temperature around the burn-in board bib to be the target temperature set by the user or the like. In addition, the details of the control unit CL will be described later. When the burn-in test is performed, after defining the circuit configuration of the programmable logic device, the programmable logic device performs a burn-in test and then reads each test. The pre-burning test of the judgment result of the apparatus was carried out in the order of the test results. Fig. 3 is a block diagram showing an example of an internal structure for reciprocating a necessary control signal or output signal between the pre-burning device 10 and the device under test. As shown in Fig. 3, the 'pre-burning device 1' is provided with a test control device 1A, a buffer plate 110, a drive plate 12A, and an extension plate 130. The test control device 1A and the baffle plate 11 are attached to, for example, the inner portion of the control portion CL. The drive plate 120 and the extension plate 130 are disposed in the casing 40. The test control device 1 performs overall control in the burn-in test performed by the burn-in device 1〇. In the present embodiment, the test control device 100 is constituted by, for example, a personal computer such as a personal computer provided in the control unit CL. The burn-in test is carried out in accordance with the control of the test control device 1〇〇. The control signals required to perform the burn-in test are output to the plurality of drive boards 120 via the buffer plate 110 of the output buffer. The drive plate 120 and the extension plate 130 are disposed in the case 40 corresponding to the respective slots 50. That is, in the present embodiment, one set of the drive plate 120 and the extension plate no are provided corresponding to one pre-burning plate BIB. Therefore, in the calcining apparatus 1A shown in Figs. 1 and 2, 60 sets of the driving plate 120 and the extending plate 130 are provided. The control signal supplied to the driving board 120 is supplied to the pre-burning board BIB via the extension board 130. On the contrary, the output of the test results output from the pre-burning plate BIB

S 13 201142320 出信號會經由延伸板130、驅動板120、缓衝板110，輸入至 測試控制裝置100。藉此，測試控制裝置100便可取得各種 的試驗結果相關資料。 第4圖係顯示本實施形態之預燒板BIB的俯視配置之一 例的圖。如該第4圖所示，預燒板BIB的插入方向端部設有 插入端緣140。該第4圖的例子中，於3處配置有插入端緣 140。 預燒板BIB收納於箱室40内後，該插入端緣140便會插 入設置於延伸板130的連接部。插入端緣形成有複數的信號 接點（signal pad)，又，延伸板130側的連接部亦形成有複數 的信號接腳(signal pin)。該等信號接腳與信號接點係配置成 彼此相對應，且信號接腳與信號接點係電性地連接。藉此， 預燒板BIB會電性地連接於延伸板130，令信號可在預燒裝 置10與預燒板BIB之間往返。而且，當預燒試驗結束時，朝 拔除方向拔除該燒板BIB，燒板BIB側的插入端緣140便會 與延伸板130側的連接部分離。 預燒板BIB上設有16個可程式邏輯裝置150。該第4圖的 例子中，係依據8個x2列之配置方式沿著插拔方向排列。 又，依據對1個可程式邏輯裝置150分配8個受測裝置之配置 方式設有插座160’並在該插座SK安裝受測裝置DUT^即， 總計有16個x8個=128個的受測裝置DUT安裝於1片預燒板 BIB 上。 即，1個可程式邏輯裝置150的寬度方向之一側配置有4 個插座SK，又，該可桎式邏輯裝置150的寬度方向之另一側 14 201142320 配置有4個插座SK。而且，從丨個可程式邏輯裝置15〇對安裝 於該等8個插座SK的8個受測裴置!^^提供測試型樣信號 後，各受測裝置DUT會將其動作結果之輸出信號輸出至該1 個可程式邏輯裝置150。 該可程式邏輯裝置15 0係可在事後變更其電路結構的 組癌裝置’可藉由例如FPGA(Field Programmable GateThe signal of S 13 201142320 is input to the test control device 100 via the extension plate 130, the drive plate 120, and the buffer plate 110. Thereby, the test control device 100 can obtain various test result related materials. Fig. 4 is a view showing an example of a plan view of the burn-in panel BIB of the present embodiment. As shown in Fig. 4, the insertion end edge 140 is provided at the end portion of the burn-in board BIB in the insertion direction. In the example of Fig. 4, the insertion edge 140 is disposed at three places. After the burn-in panel BIB is housed in the chamber 40, the insertion end edge 140 is inserted into the joint portion provided in the extension plate 130. The insertion edge is formed with a plurality of signal pads, and the connection portion on the extension plate 130 side is formed with a plurality of signal pins. The signal pins and the signal contacts are configured to correspond to each other, and the signal pins are electrically connected to the signal contacts. Thereby, the burn-in board BIB is electrically connected to the extension board 130 so that the signal can travel back and forth between the burn-in unit 10 and the burn-in board BIB. Further, when the burn-in test is completed, the burnt plate BIB is removed in the removal direction, and the insertion end edge 140 on the side of the burnt plate BIB is separated from the joint portion on the side of the extension plate 130. There are 16 programmable logic devices 150 on the burn-in board BIB. In the example of Fig. 4, the arrangement is performed in the insertion/removal direction in accordance with the arrangement of eight x2 columns. Further, a socket 160' is provided in accordance with a configuration in which eight test devices are allocated to one programmable logic device 150, and a device under test DUT is mounted on the socket SK, and a total of 16 x 8 = 128 tested The device DUT is mounted on a pre-burning plate BIB. That is, one socket SK is disposed on one side in the width direction of one programmable logic device 150, and the other side 14 201142320 of the programmable logic device 150 is disposed with four sockets SK. Moreover, after the test pattern signals are provided to the eight tested devices installed in the eight sockets SK from the programmable logic device 15 , the DUT of each device under test will output the signal of the action result. Output to the one programmable logic device 150. The programmable logic device 150 is a cancer device capable of changing its circuit structure afterwards. The field programmable gate can be used, for example, by an FPGA (Field Programmable Gate).

Array)來構成。本貫施形態中，用以變更該可程式邏輯裝置 15 0之組態的組態資料係從預燒裝置丨〇供給至可程式邏輯 裝置150。而且，可程式邏輯裝置15〇會自律性動作來生成 測試型樣信號，並進行受測裝置DUT的預燒試驗。即，形 成測試信號本身並非係從預燒裝置1〇提供，又，來自受測 裝置DUT的輸出信號亦不會輸出至預燒裝置1〇的構造。 又，該第4圖的例子中，可程式邏輯裝置15〇的接腳、 與受測裝置DUT的接腳之間，係以丨對丨的對應關係加以連 接。即，用以提供測試信號的可程式邏輯裝置15〇的驅動接 腳、與受測裝置DUT的驅動接腳之間，係以丨對丨的對應關 係加以連接，且，用以輸出受測裝置〇1；1[之動作結果的輸 出k號的受測裝置DUT的I/O接腳、與可程式邏輯裝置15〇 的I/O接腳之間，係以丨對〗的對應關係加以連接。 第5圖係用以說明本實施形態之可程式邏輯裝置15〇的 内部結構之一例的方塊圖。 如該弟5圖所示，係構造成具有：組態設定電路2〇〇、 測试器匯流排介面21〇、預燒試驗實行電路22〇、串列平行 轉換電路230、頻率轉換電路240、輸出驅動電路25〇、比較 15 201142320 電路260。 組態設定電路200係用以設定該可程式邏輯裝置150之 組態的電路。即，預燒試驗開始後，預燒裝置1〇便會對該 組態設定電路200傳輸組態資料，來設定該可程式邏輯裝置 150的内部電路結構。本實施形態之可程式邏輯裝置15〇 中，該組態設定電路2〇〇係預先設定成組態設定電路2〇〇而 納入其中’但除此之外的電路結構部分則是藉由變更該組 態設定電路200之設定來決定電路結構。即，從預燒裝置1〇 的測試控制裝置10 0對組態設定電路2 00傳輸組態設定資料 來作為控制信號’藉此設定測試器匯流排介面21〇、預燒試 驗實行電路220、串列平行轉換電路230、頻率轉換電路 240、輸出驅動電路25〇、比較電路260。 又’該第5圖的例子中，係構成驅動接腳27〇、I/O接腳 280來作為與受測裝置dut連接的可程式邏輯裝置150的接 腳。另一方面’可插入受測裝置DUT的插座SK亦對應驅動 接腳270而設有一經由信號配線與該驅動接腳27〇連接的驅 動接腳272 ’且，對應1/0接腳280而設有一經由信號配線與 該I/O接腳280連接的I/O接腳282。即，可程式邏輯裝置15〇 的驅動接腳270、與插座Sk的驅動接腳272之間，係以1對1 的對應關係加以連接，且，可程式邏輯裝置15〇的1/(；)接腳 28〇、與插座SK的I/O接腳282之間，亦係以1對1的對應關係 加以連接。 藉由此種連接關係，測試型樣信號會從可程式邏輯裝 置150輸出，然後經由驅動接腳27〇、272而供給至受測裝置 16Array) to constitute. In the present embodiment, the configuration data for changing the configuration of the programmable logic device 150 is supplied from the burn-in device to the programmable logic device 150. Moreover, the programmable logic device 15 performs an autonomous operation to generate a test pattern signal and performs a burn-in test of the device under test DUT. Namely, the formation of the test signal itself is not provided from the burn-in device 1 and the output signal from the DUT of the device under test is not output to the burn-in device 1〇. Further, in the example of Fig. 4, the pin of the programmable logic device 15A and the pin of the device under test DUT are connected in a corresponding relationship with each other. That is, the driving pin of the programmable logic device 15A for providing the test signal and the driving pin of the DUT of the device under test are connected by the corresponding relationship of the pair and the device for outputting the device under test. 〇1;1[The result of the operation result is the output k of the device DUT I/O pin and the programmable logic device 15〇 I/O pin are connected by the corresponding relationship . Fig. 5 is a block diagram showing an example of the internal structure of the programmable logic device 15A of the present embodiment. As shown in the figure 5, the configuration is configured to have: a configuration setting circuit 2〇〇, a tester bus interface 21〇, a burn-in test execution circuit 22〇, a tandem parallel conversion circuit 230, a frequency conversion circuit 240, Output drive circuit 25A, compare 15 201142320 circuit 260. The configuration setting circuit 200 is a circuit for setting the configuration of the programmable logic device 150. That is, after the start of the burn-in test, the burn-in device 1 transmits the configuration data to the configuration setting circuit 200 to set the internal circuit structure of the programmable logic device 150. In the programmable logic device 15 of the embodiment, the configuration setting circuit 2 is preset to be configured by the configuration setting circuit 2, but the circuit structure portion is changed by The setting of the configuration setting circuit 200 determines the circuit configuration. That is, the configuration control device 100 from the pre-burning device 1 transmits the configuration setting data to the configuration setting circuit 200 as a control signal 'by setting the tester bus interface 21〇, the burn-in test execution circuit 220, and the string. Column parallel conversion circuit 230, frequency conversion circuit 240, output drive circuit 25A, and comparison circuit 260. Further, in the example of Fig. 5, the drive pin 27A and the I/O pin 280 are formed as pins of the programmable logic device 150 connected to the device under test dut. On the other hand, the socket SK that can be inserted into the device under test DUT is also provided with a drive pin 272' connected to the drive pin 27A via a signal wiring corresponding to the drive pin 270, and is provided corresponding to the 1/0 pin 280. There is an I/O pin 282 connected to the I/O pin 280 via signal wiring. That is, the drive pin 270 of the programmable logic device 15A and the drive pin 272 of the socket Sk are connected in a one-to-one correspondence, and the programmable logic device 15 is 1/(;) The pins 28A and the I/O pins 282 of the socket SK are also connected in a one-to-one correspondence. With this connection relationship, the test pattern signal is output from the programmable logic device 150 and then supplied to the device under test via the drive pins 27, 272.

S 201142320 DUT。又，從測裝置DUT輸出的輸出信號，會經由1/〇接腳 282、280被可程式邏輯裝置150接收。 測s式器匯流排介面210係用以進行該可程式邏輯裝置 150與測試控制裝置1〇〇之間的信號往返的介面電路。即， 來自測試控制裝置100的控制信號會經由延伸板13〇輸入至 測試器匯流排介面210，然後再輸入至預燒試驗實行電路 220。又’來自預燒試驗實行電路22〇的輸出信號會經由測 试器匯流排介面210輸出至延伸板13 〇，然後再輸出至測試 控制裝置100。 此外，在該預燒試驗實行電路220的内部，透過前述組 態資料被供給至組態設定電路200,而形成有：型樣記憶體 300、型樣生成電路310、時機信號生成電路32〇、時機記憶 體330、波形整形電路340、通過/未通過判定電路35〇、失 效記憶體（fail memory)360。 藉由型樣記憶體300與型樣生成電路31〇，可生成在預 燒试驗之際供給至受測裝置DUT的測試型樣。即，型樣記 憶體300内，儲存有依據預燒試驗之際的測試型樣順序而生 成的一連串測試型樣，且，型樣生成電路31〇會從該型樣記 憶體300適當的§買取測試型樣，來生成需供給至受測裝置 DUT的測試型樣。業經生成的測試型樣會在波形整形電路 340受到整形，並在串列平行轉換電路23〇從平行信號被轉 換成串列信號。然後，經由輸出驅動電路25〇被輸出至各受 測裝置DUT。 又，藉由時機信號生成電路320與時機記憶體330，可S 201142320 DUT. Further, the output signal output from the DUT is received by the programmable logic device 150 via the 1/〇 pins 282, 280. The s-tube bus interface 210 is a interface circuit for performing a round-trip signal between the programmable logic device 150 and the test control device 1A. That is, the control signal from the test control device 100 is input to the tester bus interface 210 via the extension plate 13 and then input to the burn-in test execution circuit 220. Further, the output signal from the burn-in test execution circuit 22 is output to the extension plate 13 through the tester bus interface 210, and then output to the test control device 100. Further, inside the burn-in test execution circuit 220, the configuration data is supplied to the configuration setting circuit 200 through the configuration data, and the pattern memory 300, the pattern generation circuit 310, and the timing signal generation circuit 32 are formed. The timing memory 330, the waveform shaping circuit 340, the pass/fail determination circuit 35, and the fail memory 360. By the pattern memory 300 and the pattern generating circuit 31, a test pattern supplied to the device under test DUT at the time of the burn-in test can be generated. That is, in the pattern memory 300, a series of test patterns generated in accordance with the test pattern sequence at the time of the burn-in test are stored, and the pattern generating circuit 31〇 is purchased from the appropriate § of the pattern memory 300. Test the pattern to generate a test pattern to be supplied to the DUT of the device under test. The resulting test pattern is shaped in waveform shaping circuit 340 and converted from a parallel signal to a serial signal in tandem parallel conversion circuit 23. Then, it is output to each of the devices DUT via the output drive circuit 25A. Moreover, by the timing signal generating circuit 320 and the timing memory 330,

1717

S 201142320 生成預燒試驗之際所需的時機信號。即，時機記憶體33〇 内，定義且儲存有當實行預燒試驗之際所生成的測試型樣 的時機。時機信號生成電路320會從該時機記憶體33〇取得 與測試型樣的時機有關的資訊’來生成時機信號。型樣生 成電路3 10會根據該時機信號生成電路320所生成的時機信 號來生成測試型樣。又，時機信號生成電路320會將已生成 之時機信號供給至波形整形電路3 4 〇與通過/未通過判定電 路350。在波形整形電路34〇中，會根據該業經提供的時機 信號，將測試型樣信號整形，並輪出至串列平行轉換電路 230。 又，預燒試驗中，將該等測試型樣信號與時機信號供 給至受測裝置DUT後所獲得的來自受測裝置dut的輸出信 唬會經由比較電路260被輸入至_列平行轉換電路230。該 來自受測裝置DUT的輸出信號係屬試驗結果信號，在串列 平订轉換電路230從φ列信號被轉換成平行信號後，會被供 給至通過/未通過判定電路350。 通過/未通過判定電路350中，會將係屬來自受測裝置 DUT之輸出信號的試驗結果㈣、與本來應輸出的邏輯值 作比較，來騎該受測裝置DUT是否有正常動作。並且， 將糊斷結果作為試驗結果儲存於失效記憶體細。如前 述通曰過/未通過判定電路35〇内，亦從時機信號生成電路 被提供有時機化號，通過/未通過判定電路现亦會根據 «亥時機彳。絲控制動作時機。藉此，便可取得通過/未通過 判定電路35G與受測|置DUT之間的同步。 18S 201142320 Generates the timing signal required for the burn-in test. That is, in the timing memory 33, the timing of the test pattern generated when the burn-in test is performed is defined and stored. The timing signal generating circuit 320 obtains information on the timing of the test pattern from the timing memory 33 to generate a timing signal. The pattern generation circuit 3 10 generates a test pattern based on the timing signal generated by the timing signal generating circuit 320. Further, the timing signal generating circuit 320 supplies the generated timing signal to the waveform shaping circuit 34 and the pass/fail determination circuit 350. In the waveform shaping circuit 34, the test pattern signal is shaped and rotated out to the tandem parallel conversion circuit 230 based on the timing signal provided. Further, in the burn-in test, the output signal from the device under test dut obtained by supplying the test pattern signal and the timing signal to the device under test DUT is input to the column parallel conversion circuit 230 via the comparison circuit 260. . The output signal from the device under test DUT is a test result signal, which is supplied to the pass/fail decision circuit 350 after the serial-to-parallel conversion circuit 230 is converted from the φ column signal into a parallel signal. The pass/fail determination circuit 350 compares the test result (4) from the output signal of the device under test DUT with the logical value that should be outputted to ride the device DUT for normal operation. Further, the result of the battering is stored as a test result in the failure memory. As described above, the pass/fail decision circuit 35 is also provided with a time-sharing number from the timing signal generating circuit, and the pass/fail decision circuit is now also based on the «Hour Time Machine. Wire control action timing. Thereby, synchronization between the pass/fail determination circuit 35G and the measured | set DUT can be obtained. 18

S 201142320 可程式邏輯裝置150可在讀取來自受測裝置!；)^^的輸 出信號之際，從連接於該可程式邏輯裝置15〇的所有受測裝 置DUT並行地讀取。即，本實施形態中，係例如有8個受測 裝置D U T連接於1個可程式邏輯裝置丨5 〇，可從該等8個受測 裝置DUT並行地讀取輸出信號來取得其值。即，由於插入 有受測裝置DUT的插座SK的I/O接腳282、與可程式邏輯裝 置150的I/O接腳280係以1對丨的對應關係加以連接，故可並 行地一次讀取來自受測裝置〇1;丁的輸出信號。而且，由於 將該並行地讀取之輸出信號在通過/未通過判定電路35〇與 邏輯值作比較判定，並將其判定結果作為試驗結果儲存於 失效記憶體360，故可大幅縮短從受測裝置DUT讀取輸出信 號並進行判定一事的所需時間。 此外，遠等測試器匯流排介面21〇、預燒試驗實行電路 220、串列平行轉換電路230内，係從頻率轉換電路240被提 供有動作時鐘信號。即，本實施形態中，例如2〇MHz的基 本時鐘信號係從測試控制裝置丨〇 〇被供給至頻率轉換電路 240，並在該頻率轉換電路24〇中，被轉換成5〇〜1〇〇MHz的 動作時鐘信號。然後，該業經轉換頻率而生成的動作時鐘 #唬會被供給至測試器匯流排介面21〇、預燒試驗實行電路 220、申列平行轉換電路23〇，該等構件便會根據動作時鐘 信號來進行動作 又’本實施形態中，設有複數的預燒試驗實行電路 220 ’且採用交插(interleave)構造。即，複數的預燒試驗實 行電路220係並行地動作’將測試型樣與時機信號連續性地 19 201142320 輸出至串列平行轉換電路謂。例如，本實施形態中，形成 有4片以100MHz動作的預燒試驗實行電路22〇，4片預燒試 驗實行電路220並行地動作來生成測試型樣，並輸出至串列 平行轉換電路230，藉此，串列平行轉換電路23()便能夠以 相當於400MHz的週期來求得測試型樣信號的時機。 另外，該等預燒試驗實行電路220係經由電壓調整電路 400被提供驅動電源。即，從測試控制裝置丨⑼提供的驅動 電源之電壓，在電壓調整電路400業經調整後，會被供給至 複數的預燒試驗實行電路220。又，從測試控制裝置1〇〇提 供的驅動電源亦會經由插座SK而供給至受測裝置dut，成 為實行預燒試驗之際的受測裝置DUT的驅動電源。 接著，根據第6圖，針對預燒試驗之際，以測試控制裝 置100貫行的預燒試驗實行順序一事進行說明。該預燒試驗 實行順序係儲存於測試控制裝置1 〇 〇的硬碟驅動器或R 〇 M 的順序程式。藉由令測試控制裝置100的CPU實行該順序裎 式’便可實現第6圖所示之預燒試驗實行順序。 該預燒試驗實行順序開始後，首先，測試控制裝置1〇〇 會開始對預燒板BIB供電（步驟S10)。藉此，對可程式邏輯 裝置150與受測裝置DUT提供驅動用電源。 接著，測试控制裝置100為了設定可程式邏輯裝置1 的組態，而對組態設定電路200傳輸組態資料（步驟S2〇)e藉 此’前述第5圖的電路便會形成在可程式邏輯裝置15〇。 接著，測試控制裝置100會將測試型樣與時機資訊傳輪 給可私式邏輯裝置150(步驟S30)。如前述，測試型樣係儲存 20 201142320 於預燒s式驗貫行電路220的型樣記憶體300，時機資訊係儲 存於預燒試驗實行電路220的時機記憶體33〇。 接著，測試控制裝置100會對可程式邏輯裝置15〇指示 開始提供測試型樣（步驟S4〇h藉此，便會從可程式邏輯裝 置150對連接於該可程式邏輯裝置15〇的受測裝置DUT提供 測試型樣與時機信號，而可進行受測裝置DUT的動作試 驗。在進行該受測裝置DUT的動作試驗的期間，測試控制 裝置100會控制箱室40内的溫度，對受測裝置予溫度 負載(Temperature load)。即，如前述，控制加熱器6〇或冷 卻單元70,使預燒板BIB周圍的溫度成為使用者等所設定的 目標溫度。藉由該動作試驗’失效記憶體36G内便會儲存針 對各受測裝置DUT的通過或未通狀試驗結果的相關資 訊0 當預定的-連串測試型樣之提供結束時，測試控制裝 置100會進彳了試驗結果的讀取(步·0)。具體而言，測試控 制裝置1GG會對可程式邏輯提供肖以讀取試驗結果 的控|項取儲存於失效記憶體鳩的各受測裝置 DUT的<4驗、”口果。该試驗結果中，顯示出各受測裝置 的通過或未通過之資訊。 m k#制裝置⑽會判斷所有的預燒試驗是否已 、、’。束（v驟S60)。所有的預燒試驗尚未結束時（步驟s6〇 : N〇) ’ K控制裝置1GG會回到前述步驟S30 ，將下一個所 需的測試型樣與時機資訊傳輸給預燒板BIB。 另方面’在步驟S60中，判斷所有的預燒試驗已結束 21 201142320 時(步驟S60: YES)，測試控制裝置1〇〇便會結束該預燒試驗 實行噸序。S 201142320 The programmable logic device 150 can read in parallel from all of the device DUTs connected to the programmable logic device 15A while reading the output signals from the device under test. That is, in the present embodiment, for example, eight devices D U T are connected to one programmable logic device 丨5 〇, and the output signals can be read from the eight DUTs in parallel to obtain the values. That is, since the I/O pin 282 of the socket SK in which the device DUT is inserted and the I/O pin 280 of the programmable logic device 150 are connected in a one-to-one correspondence, it is possible to read in parallel. Take the output signal from the device under test 〇1; Further, since the output signal read in parallel is judged by the pass/fail determination circuit 35 and the logical value, and the result of the determination is stored as the test result in the failed memory 360, the test can be greatly shortened. The time required for the device DUT to read the output signal and make a decision. Further, the far-end tester bus interface 21, the burn-in test execution circuit 220, and the serial parallel conversion circuit 230 are provided with an action clock signal from the frequency conversion circuit 240. That is, in the present embodiment, for example, a basic clock signal of 2 〇 MHz is supplied from the test control device 至 to the frequency conversion circuit 240, and is converted into 5 〇 1 to 1 in the frequency conversion circuit 24A. MHz action clock signal. Then, the action clock #唬 generated by the conversion frequency is supplied to the tester bus interface interface 21, the burn-in test execution circuit 220, and the parallel conversion circuit 23, and the components are based on the action clock signal. In the present embodiment, a plurality of burn-in test execution circuits 220' are provided and an interleave structure is employed. That is, the plurality of burn-in test execution circuits 220 operate in parallel to output the test pattern and the timing signal continuously to the tandem parallel conversion circuit. For example, in the present embodiment, four burn-in test execution circuits 22 are operated at 100 MHz, and four burn-in test execution circuits 220 are operated in parallel to generate a test pattern, which is output to the tandem parallel conversion circuit 230. Thereby, the serial parallel conversion circuit 23() can determine the timing of the test pattern signal at a period equivalent to 400 MHz. Further, the burn-in test execution circuit 220 is supplied with a drive power via the voltage adjustment circuit 400. That is, the voltage of the driving power supplied from the test control unit 9 (9) is supplied to the plurality of burn-in test execution circuits 220 after being adjusted by the voltage adjusting circuit 400. Further, the driving power supplied from the test control device 1 is also supplied to the device under test through the socket SK, and becomes the driving power source of the device under test DUT when the burn-in test is performed. Next, according to Fig. 6, in the case of the burn-in test, the execution sequence of the burn-in test by the test control device 100 will be described. The pre-burning test execution sequence is a sequential program stored in the hard disk drive or R 〇 M of the test control device 1 . The execution sequence of the burn-in test shown in Fig. 6 can be realized by causing the CPU of the test control device 100 to execute the sequence ’. After the start of the burn-in test sequence, first, the test control device 1 starts to supply power to the burn-in board BIB (step S10). Thereby, the drive power is supplied to the programmable logic device 150 and the device under test DUT. Next, the test control device 100 transmits the configuration data to the configuration setting circuit 200 (step S2〇) e in order to set the configuration of the programmable logic device 1, whereby the circuit of the aforementioned fifth figure is formed in the programmable Logic device 15〇. Next, the test control device 100 passes the test pattern and the timing information to the private logic device 150 (step S30). As described above, the test pattern stores 20 201142320 in the pattern memory 300 of the pre-burned s-test line circuit 220, and the timing information is stored in the timing memory 33 of the burn-in test execution circuit 220. Next, the test control device 100 instructs the programmable logic device 15 to start providing the test pattern (step S4〇h), and the test device connected to the programmable logic device 15 from the programmable logic device 150 The DUT provides a test pattern and a timing signal, and can perform an operation test of the device under test DUT. During the operation test of the device under test DUT, the test control device 100 controls the temperature in the chamber 40 to the device under test. To the temperature load, that is, as described above, the heater 6 or the cooling unit 70 is controlled so that the temperature around the burn-in board BIB becomes the target temperature set by the user or the like. The relevant information of the pass or fail test results for each DUT of the device under test is stored in the 36G. When the provision of the predetermined-serial test pattern is completed, the test control device 100 will read the test result. (Step·0). Specifically, the test control device 1GG provides a control for the programmable logic to read the test result, and the item is stored in the failed memory device DUT. "The fruit of the test. In the test results, the information of the passing or failing of each device under test is displayed. The mk# device (10) will judge whether all the calcination tests have been, ". bundle (v step S60). All When the burn-in test has not been completed (step s6〇: N〇) 'K control device 1GG will return to the aforementioned step S30 to transmit the next required test pattern and timing information to the burn-in board BIB. In S60, when it is judged that all the burn-in tests have ended 21 201142320 (step S60: YES), the test control device 1 ends the execution of the burn-in test.

如如述’根據本實施形態之預燒系統，在預燒板BIB 上置可程式邏輯裝置丨’當進行預燒試驗之際，該可程 式邏輯裝置150本身會生成測試型樣與時機信號，然後供給 至各X測敦置DUT，並且同時，並行地取得來自各受測裝 置DUT的輸出信號，並與邏輯值作比較。因此，無需如以 在般’令測試控制裝置1〇〇將複數的受測裝置DUT依序切換As described in the 'burning system according to the present embodiment, a programmable logic device is placed on the burn-in board BIB'. When the burn-in test is performed, the programmable logic device 150 itself generates a test pattern and an opportunity signal. Then, it is supplied to each of the X-measured DUTs, and at the same time, the output signals from the respective DUTs are taken in parallel and compared with the logical values. Therefore, it is not necessary to sequentially switch the plurality of DUTs under test as in the case of the test control device 1

成每—群組來讀取輸出信號，而可縮短讀取受測裝置DUT 之輸出信號的所需時間。藉此，便可謀求縮短預燒試驗的 整體時間。 又’作為通過/未通過判定電路350之判定結果的試驗 結果會暫時儲存於失效記憶體36〇,並在步驟S5〇中，一次 δ賣取§亥試驗結果。如此一來，比起測試控制裝置丨從預燒 板ΒIΒ讀取受測裝置D υ τ的輸出信號，更可謀求刪減需讀取 之資訊量，且亦可謀求縮短來自預燒板BIB的讀取時間。由 此觀點來看’本實施形態之預燒系統可謀求縮短預燒試驗 的整體時間。 又’由於可刪減必須從預燒板BIB讀取的資訊量，故即 使構造成將多數受測裝置DUT裝載於1片預燒板BIB上，亦 無需如以往般地增加延伸板13〇的連接部的信號接腳數，或 增加預燒板BIB的插入端緣140的信號接點數，可原封不動 地利用現有的預燒裝置10。 又’由於構造成在預燒板BIB上設置可程式邏輯裝置 22 201142320 150，並使用該可程式邏輯裝置150 ’提供測試型樣與時機 信號，將受測裝置DUT的輸出信號與邏輯值作比較，故藉 由變更在預燒試驗實行順序中的步驟S20所傳輸的組態資 料，便可進行各式各樣的預燒試驗。因此，即使是在受測 裝置DUT的設計變更，或其種類改變的情況下，仍可有效 活用預燒板BIB。 [第2實施形態] 第7圖係將前述第1實施形態中的預燒板bib之變形例 作為第2實施形態來顯示的圖，且係對應前述第1實施形態 的第4圖的圖。該第7圖的變形例中，係對1個可程式邏輯裝 置150連接12個受測裝置DUT來進行預燒試驗。即，可在Γ 片預燒板BIB上裝載12個χ16個= 192個受測褒置dut，同時 進行預燒試驗。 惟，該第7圖的例子中，將來自受測裝置DUT的輸出信 號輸出至可程式邏輯裝置15 0的I / 〇接腳係以！對丨的對應關 係連接在受測裝置DUT與可程式邏輯裴置15〇之間，但是用 以將測試型樣與時機信號從可程式邏輯裝置丨5 〇供給至受 測裝置D U T的驅動接腳則係以丨對2的對應關係加以連接。 即，從可程式邏輯裝置150輸出的測試型樣與時機信號會供 給至2個受測裝置DUT。 惟，連接於可程式邏輯裝置15〇的1根驅動接腳，且可 安裝受測裝置DUT的插座SK的驅動接腳數量不受限於2 根，亦可為3根、4根等複數根。即，供可程式邏輯裝置15〇 輸出測試型樣信號的驅動接腳、與用以對受測裝置DUT輸The output signal is read by each group, and the time required to read the output signal of the DUT of the device under test can be shortened. Thereby, the overall time of the burn-in test can be shortened. Further, the test result as the result of the pass/fail determination circuit 350 is temporarily stored in the fail memory 36, and in step S5, the δ test result is sold once. In this way, the output signal of the device under test D υ τ is read from the burn-in board ΒI 比, and the amount of information to be read can be reduced, and the shortening from the burn-in board BIB can also be shortened. Read time. From this point of view, the calcination system of the present embodiment can shorten the overall time of the calcination test. In addition, since the amount of information that must be read from the burn-in board BIB can be deleted, even if it is configured to mount a plurality of devices DUT to be mounted on one pre-burning plate BIB, it is not necessary to increase the extension plate 13 as in the past. The number of signal pins of the connection portion or the number of signal contacts of the insertion edge 140 of the burn-in board BIB can be used as it is, and the existing burn-in device 10 can be used as it is. In addition, since the programmable logic device 22 201142320 150 is configured on the burn-in board BIB, and the test pattern and the timing signal are provided using the programmable logic device 150', the output signal of the device under test DUT is compared with the logic value. Therefore, various types of burn-in tests can be performed by changing the configuration data transmitted in step S20 in the execution sequence of the burn-in test. Therefore, even in the case where the design of the device under test DUT is changed, or the type thereof is changed, the burn-in board BIB can be effectively utilized. [Second Embodiment] Fig. 7 is a view showing a modification of the burn-in board bib in the first embodiment as a second embodiment, and corresponds to the fourth diagram of the first embodiment. In the modification of Fig. 7, a test device DUT is connected to one programmable logic device 150 to perform a burn-in test. That is, 12 χ 16 = 192 measured dams dut can be loaded on the enamel pre-burning plate BIB, and a burn-in test is performed at the same time. However, in the example of Fig. 7, the output signal from the device under test DUT is output to the I/ 〇 pin of the programmable logic device 150! The corresponding relationship between the device is connected between the device under test DUT and the programmable logic device 15〇, but the test pin and the timing signal are supplied from the programmable logic device 丨5 至 to the driving pin of the device under test DUT. Then, the correspondence between 丨 and 2 is connected. That is, the test pattern and the timing signal output from the programmable logic device 150 are supplied to the two DUTs to be tested. However, the number of drive pins connected to the one of the drive pins of the programmable logic device 15A and the socket SK to which the device DUT can be mounted is not limited to two, and may be three or four. . That is, the programmable logic device 15 outputs a driving pin for the test pattern signal and is used to input the DUT of the device under test.

S 23 201142320S 23 201142320

入測試型樣信號的插座sk的驅動接腳夕B K間’亦可成立對可 程式邏輯裝置⑻根驅動接腳連接複數驅。 這意味著用以傳遞測試型樣與時機信號的信號配線有 分歧…般而言，信號配線若有分歧，傳遞的信號波形便 會失真’因此變得無法使用高頻率的動作時鐘信號，對高 速化造成妨礙。另-方面’可搭載於—片預燒板Bm上的受 測裝置DUT的數量若增加，預燒試驗的整體處理量 (throughput)便有可能提高。而且，該第7圖的例子中，ι/〇 接腳係以1對丨的對應關係加以連接，可程式邏輯裝置15〇可 並行地讀取所有來自受測裝置DUT的輸出信號。因此，讀 取輸出仏號，並在通過/未通過判定電路35〇與邏輯值作比 較，然後將比較結果儲存於失效記憶體36〇一事的所需時 間’與第4圖所示之預燒板BIB相同。 因此，比起採用如第4圖所示之構造的預燒板BIB，採 用如第7圖所示之構造的預燒板BIB，在縮短整體預燒試驗 時間方面’有時亦係屬更佳實例。 [第3實施形態] 前述第1實施形態及第2實施形態之預燒系統中，係舉 例說明進行DRAM等揮發性記憶裝置之預燒試驗的情況， 但是在第3實施形態之預燒系統中，係以將NAND型快閃記 憶體等非揮發性記憶裝置作為受測裝置DUT來進行預燒試 驗的情況為例，來說明本發明之一實施形態。另外，以下 只謂4明與前述第1實施形態及第2實施形態不同的部分。 1亥種非揮發性記憶裝置中，具有不良區塊管理功能， 24 201142320 該功能係將特定出不良區塊的資訊儲存於壞塊記憶體(b ad block mem〇ry) ’並從使用對象排除該不良區塊。因此，預 燒試驗中，在作為受測裝置DUT之非揮發性記憶裝置中檢 測出不良區塊時，必須先將特定出該業經檢測出之不良區 塊的資訊保存於記憶體。 第8圖係部分性地顯示進行該種非揮發性記憶裝置之 預燒試驗的預燒系統中，設於預燒板BIB的可程式邏輯裝置 150的内部結構之一例、與驅動板120的内部結構之一例的 方塊圖。§亥弟8圖中，雖然僅圖示出1個可程式邏輯裝置15〇 的内部結構，但是與設於預燒板BIB上的其他可程式邏輯裝 置150亦係屬相同結構。又，受測裝置DUT可為如第4圖所 示之配置，亦可為如第7圖所示之配置。 如第8圖所示’可程式邏輯裝置15〇與前述第1實施形態 及第2實施形態同樣地設有組態設定電路2〇〇。在第6圖的預 燒試驗實行順序的步驟S20中，藉由從測試控制裝置1〇〇對 該組態設定電路200傳輸組態資料，該可程式邏輯裝置150 便可設定成如第8圖所示之電路結構。 具體而言，本實施形態中，藉由該組態資料所進行之 設定，而在可程式邏輯裝置15〇形成：測試器匯流排介面 500、型樣生成電路510、波形整形電路520 '輸出驅動電路 530、比較電路540、通過/未通過判定電路55〇、判定電路 560、壞塊記憶體570、通用緩衝記憶體58〇、時機信號生成 電路590。 在第ό圖的預燒試驗實行順序的步驟84〇輸入開始提供The drive pin of the socket sk of the test pattern signal can be set to connect the complex drive to the programmable logic device (8). This means that the signal wiring for transmitting the test pattern and the timing signal is different. In general, if the signal wiring is different, the transmitted signal waveform will be distorted. Therefore, it becomes impossible to use the high-frequency operation clock signal for high speed. It is a hindrance. On the other hand, if the number of the measuring devices DUT that can be mounted on the sheet calcining plate Bm increases, the overall throughput of the calcining test may increase. Further, in the example of Fig. 7, the ι/〇 pins are connected in a one-to-one correspondence, and the programmable logic device 15 读取 can read all the output signals from the device under test DUT in parallel. Therefore, the output nickname is read, and the pass/fail decision circuit 35 〇 is compared with the logic value, and then the comparison result is stored in the time required for the failed memory 36 ' and the pre-pattern shown in FIG. 4 Burning board BIB is the same. Therefore, compared with the pre-burning plate BIB having the structure shown in Fig. 4, the pre-burning plate BIB having the structure shown in Fig. 7 is sometimes better in shortening the overall burn-in test time. Example. [Third Embodiment] In the calcination system according to the first embodiment and the second embodiment, a case where a calcination test of a volatile memory device such as a DRAM is performed is exemplified, but in the calcination system of the third embodiment. An embodiment of the present invention will be described by taking a case where a non-volatile memory device such as a NAND flash memory is used as a device under test DUT to perform a burn-in test. In the following description, only the portions different from the first embodiment and the second embodiment will be described. 1H non-volatile memory device has a bad block management function, 24 201142320 This function stores information of specific bad blocks in bad block memory (b ad block mem〇ry) ' and excludes from the use object The bad block. Therefore, in the burn-in test, when a defective block is detected in the non-volatile memory device as the DUT of the device under test, it is necessary to first store information indicating the defective block detected in the memory in the memory. Fig. 8 is a partial view showing an example of the internal structure of the programmable logic device 150 provided in the burn-in board BIB in the burn-in system for performing the burn-in test of the non-volatile memory device, and the inside of the drive board 120. A block diagram of an example of a structure. In the figure of Helmet 8, only the internal structure of one programmable logic device 15A is illustrated, but the other programmable logic devices 150 provided on the burn-in board BIB are also of the same structure. Further, the device under test DUT may be configured as shown in Fig. 4 or may be configured as shown in Fig. 7. As shown in Fig. 8, the programmable logic device 15 is provided with a configuration setting circuit 2A as in the first embodiment and the second embodiment. In the step S20 of the pre-burning test execution sequence of Fig. 6, by transmitting the configuration data from the test control device 1 to the configuration setting circuit 200, the programmable logic device 150 can be set as shown in Fig. 8. The circuit structure shown. Specifically, in the present embodiment, by setting the configuration data, the programmable logic device 15 is formed: the tester bus interface interface 500, the pattern generation circuit 510, and the waveform shaping circuit 520' output drive. The circuit 530, the comparison circuit 540, the pass/fail determination circuit 55, the decision circuit 560, the bad block memory 570, the general purpose buffer memory 58, and the timing signal generation circuit 590. In the first step of the burn-in test in the figure, the sequence of steps 84 is input and the input is provided.

S 25 201142320 '貝】忒型樣的指示後，型樣生成電路510會生成測試型樣，並 輸出至波形整形電路520。波形整形電路52〇會將業經輸入 之測忒型樣的波形整形，然後經由輸出驅動電路530輸出至 受測裝置DUT。 作為根據該測試型樣信號進行動作之結果的來自受測 裝置DUT的輸出信號，會經由比較電路54〇輸入至通過/未 通過判定電路550。即，從以1對1的對應關係加以連接的插 座SK的I/O接腳282對可程式邏輯裝置15〇的1/〇接腳28〇讀 取輪出信號’然後輸入至通過/未通過判定電路550。通過/ 未通過判定電路550内’亦從型樣生成電路510被提供有邏 輯值’在通過/未通過判定電路55〇中，會將該邏輯值與來 自受測裝置DUT的輸出信號作比較，並將該比較結果輸出 至判定電路560。 在判定電路560中，會判定比較結果是未通過還是通 過’ S比較結果為未通過時’便會正向計數(c〇unt up)該區 塊的未通過數《然後，當未通過數超過預定值時，便會將 該區塊判定為不良區境，並將該特定出不良區塊的資訊儲 存於壞塊記憶體570。 來自通過/未通過判定電路550的判定結果亦會輸入至 通用缓衝記憶體580。因此，該通用緩衝記憶體580内’可 連續性地儲存保持其判定結果。又，通用緩衝記憶體580可 將儲存於該通用緩衝記憶體580的各種資訊經由波形整形 電路520供給至受測裝置DUT。 該等預燒試驗中的一連串動作係根據時機信號生成電 26 201142320 路590所生成_作時鐘⑽來達成時機的控制。即，時機 信號生成電路59G所生·動作時鐘信號會被輸出至通過/ 未通過判定電路550與波形整形電路52〇，然後該等通過/未 通過判定電路550與波形整形電路52〇便會根據該動作時鐘 信號來動作。 又’本貫施形態中，驅動板12〇設有可程式邏輯裝置6〇〇 與壞塊記憶體610。可程式邏輯裝置6〇〇的構造與可程式邏 輯裝置150相同，係從測試控制裝置1〇〇被傳輸組態資料來 設定其電路結構。該可程式邏輯裝置6〇〇具有功能如下， 即，從位在連接於該驅動板12〇之預燒板BIB上的可程式邏 輯裝置150之壞塊記憶體570，讀取特定出壞塊的資訊。而 且，該業經讀取之壞塊的相關資訊係被儲存於壞塊記憶體 610。 如此一來’即使在將非揮發性記憶裝置作為受測褒置 DUT的預燒試驗中，設置於預燒板bib上的可程式邏輯梦置 150亦可從受測裝置DUT並行地讀取輸出信號，故可縮短讀 取受測裝置DUT的輸出信號的所需時間。因此，可縮短整 體預燒試驗所需的時間。 另外’本發明不受限於前述實施形態，可進行各種變 形。例如，在前述實施形態中，在可程式邏輯骏置15〇設有 EEPROM等非揮發性記憶裝置，且係屬可事先記憶可程式 邏輯裝置150的組態的類型時，便無需在每次開始預燒試驗 實行順序時，都得從測試控制裝置100對可程式邏輯襄置 150傳輸組態資料。即，如果預燒試驗的内容相同，便可省 27 201142320 略前述預燒試驗實行順序的步驟S20來進行試驗。 I：圖式簡單説明3 第1圖係本發明之一實施形態之預燒系統中的預燒裝 置之整體正視圖。 第2圖係用以說明在第1圖之預燒裝置内收納有預燒板 之狀態下的内部結構之一例的正視配置圖。 第3圖係顯示在第1圖之預燒裝置中，用以使必要的控 制信號或輸出信號在預燒裝置與受測裝置之間往返的内部 結構之一例的方塊圖。 第4圖係本發明之一實施形態之預燒板的俯視配置圖。 第5圖係說明使用組態資料對設置於預燒板上的可程 式邏輯裝置之内部電路進行設定時的電路結構之一例的方 塊圖。 第6圖係說明在第1圖之預燒系統中實行的預燒試驗實 行順序内容之一例的流程圖。 第7圖係作為第2實施形態來說明預燒板之變形例的預 燒板之正視配置圖。 第8圖係作為第3實施形態來說明使用組態資料對設置 於預燒板上的可程式邏輯裝置之内部電路進行設定時的電 路結構之一例的方塊圖。 【主要元件符號說明】 10.. .預燒裝置 40...箱室 20.··門 50··.插槽 30.. .隔熱壁 60...加熱器 28 201142320 70.. .冷卻單元 72.. .冷卻壓縮機 74.. .熱交換器 80…風扇 100.. .測試控制裝置 110.. .緩衝板 120.. .驅動板 130.. .延伸板 140.. .插入端緣 150.. .可程式邏輯裝置 200.. .組態設定電路 210.. .測試器匯流排介面 220…預燒試驗實行電路 230.. .串列平行轉換電路 240.. .頻率轉換電路 250.. .輸出驅動電路 260.. .比較電路 270.. .驅動接腳 272.. .驅動接腳 280.. .1.O 接腳 282.. .1.O 接腳 300.. .型樣記憶體 310.. .型樣生成電路 320.. .時機信號生成電路 330.. .時機記憶體 340.. .波形整形電路 350.. .通過/未通過判定電路 360.. .失效記憶體 400.. .電壓調整電路 500.. .測試器匯流排介面 510.. .型樣生成電路 520.. .波形整形電路 530.. .輸出驅動電路 540.. .比較電路 550.. .通過/未通過判定電路 560.. .判定電路 570.. .壞塊記憶體 580.. .通用缓衝記憶體 590.. .時機信號生成電路 600.. .可程式邏輯裝置 610.. .壞塊記憶體 BIB...預燒板 CL...控制部 CR...載架 DT...空氣循環通道 DUT...受測裝置 SK...插座 510.. .步驟S 25 201142320 After the indication of the 贝 type, the pattern generation circuit 510 generates a test pattern and outputs it to the waveform shaping circuit 520. The waveform shaping circuit 52 整形 shapes the waveform of the input sense pattern and outputs it to the device under test DUT via the output drive circuit 530. The output signal from the device under test DUT as a result of the operation based on the test pattern signal is input to the pass/fail determination circuit 550 via the comparison circuit 54. That is, the I/O pin 282 of the socket SK connected in a one-to-one correspondence is read from the 1/〇 pin 28 of the programmable logic device 15A, and then the input/pass is passed. Decision circuit 550. The pass/fail determination circuit 550 is also provided with a logic value from the pattern generation circuit 510 in the pass/fail determination circuit 55, which is compared with the output signal from the device under test DUT. The comparison result is output to the determination circuit 560. In the decision circuit 560, it is determined whether the comparison result is not passed or if the 'S comparison result is not passed', then the number of the passages of the block is counted up (c〇unt up). Then, when the number of failures exceeds When the predetermined value is obtained, the block is determined to be a bad area, and the information of the specific bad block is stored in the bad block memory 570. The result of the determination from the pass/fail determination circuit 550 is also input to the general purpose buffer memory 580. Therefore, the inside of the general-purpose buffer memory 580 can be continuously stored and maintained as a result of its determination. Further, the general purpose buffer memory 580 can supply various kinds of information stored in the general purpose buffer memory 580 to the device under test DUT via the waveform shaping circuit 520. A series of actions in the burn-in test are based on the timing signal generated by the circuit 610 generated by the clock 590 to achieve timing control. That is, the operation clock signal generated by the timing signal generating circuit 59G is output to the pass/fail determination circuit 550 and the waveform shaping circuit 52, and then the pass/fail determination circuit 550 and the waveform shaping circuit 52 are The action clock signal operates. Further, in the embodiment, the drive board 12 is provided with a programmable logic device 6A and a defective block memory 610. The programmable logic device 6A is constructed in the same manner as the programmable logic device 150, and the configuration is configured from the test control device 1 to set its circuit configuration. The programmable logic device 6 has the function of reading a specific bad block from the bad block memory 570 of the programmable logic device 150 located on the burn-in board BIB connected to the driving board 12B. News. Moreover, the related information of the bad block that has been read is stored in the bad block memory 610. In this way, even when the non-volatile memory device is used as the burn-in test of the DUT under test, the programmable logic device 150 disposed on the burn-in board bib can also read and output in parallel from the device under test DUT. The signal shortens the time required to read the output signal of the device under test DUT. Therefore, the time required for the overall burn-in test can be shortened. Further, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the foregoing embodiment, when the programmable logic device is provided with a non-volatile memory device such as an EEPROM, and the type of the configuration of the programmable logic device 150 can be memorized in advance, it is not necessary to start each time. When the burn-in test is performed in the order, the configuration data is transmitted from the test control device 100 to the programmable logic device 150. That is, if the contents of the calcination test are the same, the test can be carried out by the step S20 of the order of the calcination test described above. I: BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall front view of a burn-in apparatus in a burn-in system according to an embodiment of the present invention. Fig. 2 is a front elevational view showing an example of an internal structure in a state in which a calcining plate is housed in the calcining apparatus of Fig. 1. Fig. 3 is a block diagram showing an example of an internal structure for reciprocating a necessary control signal or output signal between the burn-in device and the device under test in the burn-in device of Fig. 1. Fig. 4 is a plan view showing a plan view of a burn-in board according to an embodiment of the present invention. Fig. 5 is a block diagram showing an example of a circuit configuration when an internal circuit of a programmable logic device provided on a burn-in board is set using a configuration data. Fig. 6 is a flow chart showing an example of the sequence of the pre-firing test performed in the burn-in system of Fig. 1. Fig. 7 is a front elevational view showing a pre-burning plate of a modified example of the burn-in plate as a second embodiment. Fig. 8 is a block diagram showing an example of a circuit configuration when an internal circuit of a programmable logic device provided on a burn-in board is set using a configuration data as a third embodiment. [Description of main component symbols] 10.. Pre-burning device 40...Box room 20.·Door 50··.Slot 30.. Insulation wall 60...Heater 28 201142320 70.. Cooling Unit 72.. Cooling compressor 74.. Heat exchanger 80... Fan 100.. Test control device 110.. Buffer plate 120.. Drive plate 130.. Extension plate 140.. Inserting edge 150.. . programmable logic device 200.. . configuration setting circuit 210.. tester bus interface interface 220... burn-in test implementation circuit 230.. tandem parallel conversion circuit 240.. frequency conversion circuit 250. Output drive circuit 260.. compare circuit 270.. drive pin 272.. drive pin 280.. .1.O pin 282..1.O pin 300.. type memory Body 310.. pattern generation circuit 320.. timing signal generation circuit 330.. timing memory 340.. waveform shaping circuit 350.. pass/fail determination circuit 360.. failed memory 400. Voltage adjustment circuit 500.. tester bus interface 510.. pattern generation circuit 520.. waveform shaping circuit 530.. output driver circuit 540.. comparison circuit 550.. pass/fail Decision circuit 560.. determination circuit 5 70.. . Bad block memory 580.. General buffer memory 590.. Timing signal generation circuit 600.. Programmable logic device 610.. Bad block memory BIB... Burnt board CL. .. control unit CR... carrier DT... air circulation channel DUT... device under test SK... socket 510.. .

S 29 201142320 S20·.·步驟 530.. .步驟 540.. .步驟S 29 201142320 S20·.·Step 530.. .Step 540.. .

Claims (1)

201142320 七、申請專利範圍： L 一種預燒板，其特徵在於包含有： 複數可程式邏輯裝置，係根據組態資料而可變更電 路結構者；及 複數插座，係可安裝受測裝置，且連接於任一前述 複數可程式邏輯裝置者， 各前述複數可程式邏輯裝置均連接有複數的前述 插座， 各前述複數可程式邏輯裝置係根據在預燒試驗前 供給之組態資料，而至少形成有電路及記憶體，該電路 係生成供給至當進行預燒試驗之際已安裝於前述插座 之义測裝置的測试型樣者，該記憶體係從連接於該可程 式邏輯裝置的複數受測裝置，並行地讀取來自當進行預 燒試驗之際已安裝於前述插座之受测裝置的輸出信號 並與邏輯值作比較，然後將其結果作為試驗結果來加以 儲存者。 2·如申凊專利範圍第1項之預燒板，其中前述組態資料係 從設置於插入有該預燒板之預燒裝置的測試控制裝置 供給至前述可程式邏輯裝置。 3. 如申請專利範圍第1或2項之預燒板，其中儲存於前述記 憶體的則述試驗結果係藉由前述測試控制裝置來讀取。 4. 如申請專利範圍第⑴項中任—項之職板其中輸入 來自刚述受測裝置之輪出信號的前述可程式邏輯裝置 的I/O接腳、與供前述受測裝置輸出輸出信號的插座的 31 S 201142320 I/O接腳之間，係以1對1的對應關係連接，且前述受測 裝置輸出的輸出信號係並行地同時由可程式邏輯裝置 讀取。 5. 如申請專利範圍第4項之預燒板，其中供前述可程式邏 輯裝置輸出前述測試型樣信號的驅動接腳、與用以對前 述受測裝置輸入前述測試型樣信號的插座的驅動接腳 之間，亦係以1對1的對應關係連接。 6. 如申請專利範圍第4項之預燒板，其中供前述可程式邏 輯裝置輸出前述測試型樣信號的驅動接腳、與用以對前 述受測裝置輸入前述測試型樣信號的插座的驅動接腳 之間，係屬對前述可程式邏輯裝置之1根驅動接腳連接 有複數驅動接腳的關係。 7. 如申請專利範圍第1至6項中任一項之預燒板，其中前述 記憶體内可儲存作為前述試驗結果之資訊，該資訊係顯 示出受測裝置是否通過預燒試驗者。 8. 如申請專利範圍第1至6項中任一項之預燒板，其中前述 記憶體内可儲存作為前述試驗結果之資訊，該資訊係特 定出受測裝置的不良區塊者。 9. 一種預燒裝置，係可插入1或複數預燒板者，其特徵在 於： 前述預燒板包含有： 複數可程式邏輯裝置，係根據組態資料而可變更電 路結構者；及 複數插座，係可安裝受測裝置，且連接於任一前述201142320 VII. Patent application scope: L A pre-burning board, which is characterized by: a plurality of programmable logic devices, which can change the circuit structure according to the configuration data; and a plurality of sockets, which can be installed with the device under test, and connected In any of the foregoing plurality of programmable logic devices, each of the plurality of programmable logic devices is connected to a plurality of the sockets, and each of the plurality of programmable logic devices is formed according to at least configuration data supplied before the burn-in test. a circuit and a memory for generating a test pattern supplied to a sensing device mounted on the socket when performing a burn-in test, the memory system being connected to a plurality of devices under test capable of the programmable logic device The output signal from the device under test installed in the socket at the time of performing the burn-in test is read in parallel and compared with the logical value, and the result is stored as a test result. 2. The burn-in board of claim 1, wherein the configuration data is supplied from the test control device provided in the burn-in device in which the burn-in board is inserted to the programmable logic device. 3. The pre-burning plate according to claim 1 or 2, wherein the test results stored in the aforementioned memory are read by the aforementioned test control device. 4. If the job board of any one of the scopes of the patent application (1) is input, the I/O pin of the aforementioned programmable logic device from the rotation signal of the device under test is input, and the output signal is outputted by the device under test. The 31 S 201142320 I/O pins of the socket are connected in a one-to-one correspondence, and the output signals output by the device under test are simultaneously read by the programmable logic device in parallel. 5. The pre-burning plate according to claim 4, wherein the driving pin for outputting the test pattern signal by the programmable logic device and the driving of the socket for inputting the test pattern signal to the device under test are provided. The pins are also connected in a one-to-one correspondence. 6. The pre-burning plate according to claim 4, wherein the driving pin for outputting the test pattern signal by the programmable logic device and the driving of the socket for inputting the test pattern signal to the device under test are provided. Between the pins, the relationship between the plurality of driving pins is connected to one of the driving pins of the programmable logic device. 7. The burn-in board according to any one of claims 1 to 6, wherein the memory can store information as a result of the foregoing test, the information indicating whether the device under test passes the burn-in tester. 8. The burn-in board according to any one of claims 1 to 6, wherein the memory can store information as a result of the foregoing test, the information being specific to a defective block of the device under test. 9. A pre-burning device, which is capable of inserting 1 or a plurality of pre-burning plates, wherein: the pre-burning plate comprises: a plurality of programmable logic devices, wherein the circuit structure can be changed according to the configuration data; and the plurality of sockets , can be installed with the device under test, and connected to any of the foregoing 32 201142320 複數可程式邏輯裝置者， 前述預燒板的各前述複數可程式邏輯裝置均連接 有複數的前述插座，並且同時， 該預燒裝置會在預燒試驗前對前述複數可程式邏 輯裝置供給組態資料， 而在各前述複數可程式邏輯裝置形成電路及記憶 體，該電路係生成供給至當進行預燒試驗之際已安裝於 前述插座之受測裝置的測試型樣者，該記憶體係從連接 於該可程式邏輯裝置的複數受測裝置，並行地讀取來自 當進行預燒試驗之際已安裝於前述插座之受測裝置的 輸出信號並與邏輯值作比較，然後將其結果作為試驗結 果來加以儲存者。 10. —種預燒系統，係包含有：1或複數預燒板、及可插入 前述預燒板的預燒裝置者，其特徵在於： 前述預燒板包含有： 複數可程式邏輯裝置，係根據組態資料而可變更電 路結構者；及 複數插座，係可安裝受測装置，且連接於任一前述 複數可程式邏輯裝置者， 刖述預燒板的各前述複數可程式邏輯震置均連接 有複數的前述插座，並且同時， 前述預燒裝置會在預燒試驗前對前述複數可程式 邏輯裝置供給組態資料， 而在各前述複數可程式邏輯裝置形成電路及記憶 S 33 201142320 體，該電路係生成供給至當進行預燒試驗之際已安裝於 如述插座之叉測裝置的測試型樣者，該記憶體係從連接 於該可程式邏輯裝置的複數受測裝置，並行地讀取來自 當進行預燒S式驗之際已安裝於前述插座之受測装置的 輸出信號並與邏輯值作比較，然後將其結果作為試驗結 果來加以儲存者。 11. -種預齡置之控㈣法，該雜裝置储人丨或複數 預燒板者， 刖述預燒板包含有： 複數可程式邏輯裝置，係根據組態資料而可變更電 路結構者；及 複數插座，係可安裝受測裝置，且連接於任一前述 複數可程式邏輯裝置者， 且前述預燒板的各前述複數可程式邏輯裝置均連 接有複數的前述插座， 5玄控制方法之特徵在於： 在預燒試驗前，從前述預燒裝置對前述複數可程式 邏輯裝置供給組態資料， 在各前述複數可程式邏輯裝置形成電路及記憶 體》亥電路係生成供給至當進行預燒試驗之際已安裝於 前述插座之受測裝置的測試型樣者，該記憶體係從連接 於該可程式邏輯裝置的複數受職置，並行地讀取來自 當進仃預燒試驗之際已安裝於前述插座之受測裝置的 輸出信號並與邏輯值作比較，然後將其結果作為試驗結32 201142320 A plurality of programmable logic devices, each of said plurality of programmable logic devices of said burn-in board is connected to a plurality of said sockets, and at the same time, said burn-in device supplies said plurality of programmable logic devices before said burn-in test Configuring the data, and forming a circuit and a memory in each of the plurality of programmable logic devices, the circuit generating a test pattern supplied to the device under test installed in the socket when the burn-in test is performed, the memory system Reading, from a plurality of devices under test connected to the programmable logic device, output signals from the device under test installed in the socket at the time of performing the burn-in test, and comparing with the logic values, and then using the result as a result The test results are to be stored. 10. A pre-burning system comprising: 1 or a plurality of pre-burning plates, and a pre-burning device insertable into the pre-burning plate, wherein: the pre-burning plate comprises: a plurality of programmable logic devices, The circuit structure can be changed according to the configuration data; and the plurality of sockets can be installed with the device under test, and are connected to any of the plurality of programmable logic devices, and the foregoing plurality of programmable logic oscillators of the burn-in board are described. A plurality of the aforementioned sockets are connected, and at the same time, the pre-burning device supplies the configuration data to the plurality of programmable logic devices before the burn-in test, and the circuit and the memory are formed in each of the plurality of programmable logic devices. The circuit generates a test pattern supplied to a fork measuring device mounted on a socket as described in the pre-burning test, the memory system being read in parallel from a plurality of devices under test connected to the programmable logic device From the output signal of the device under test installed in the socket when the pre-burning S test is performed, and compared with the logic value, and then the result is tested Results are to be stored. 11. - Pre-aged control (four) method, the miscellaneous device storage or multiple pre-burning board, the description of the pre-burning board includes: a plurality of programmable logic devices, which can change the circuit structure according to the configuration data And a plurality of sockets, wherein the device to be tested is connected to any of the plurality of programmable logic devices, and each of the plurality of programmable logic devices of the pre-burning plate is connected to a plurality of the sockets, and the method of controlling the plurality of The utility model is characterized in that: before the pre-burning test, the configuration data is supplied to the plurality of programmable logic devices from the pre-burning device, and the circuit and the memory are formed in each of the plurality of programmable logic devices to generate a supply. At the time of the burning test, the test type of the device under test of the socket is installed. The memory system is read from the plurality of devices connected to the programmable logic device, and is read in parallel from the time when the pre-burning test is performed. The output signal of the device under test installed in the aforementioned socket is compared with the logic value, and the result is used as a test knot. 34 201142320 果來加以儲存者。 12. —種預燒系統之控制方法，該預燒系統係包含有1或複 數預燒板、及可插入前述預燒板的預燒裝置者， 前述預燒板包含有： 複數可程式邏輯裝置，係根據組態資料而可變更電 路結構者；及 複數插座，係可安裝受測裝置，且連接於任一前述 複數可程式邏輯裝置者， 且前述預燒板的各前述複數可程式邏輯裝置均連 接有複數的前述插座， 該控制方法之特徵在於： 在預燒試驗前，從前述預燒裝置對前述複數可程式 邏輯裝置供給組態資料， 在各前述複數可程式邏輯裝置形成電路及記憶 體，該電路係生成供給至當進行預燒試驗之際已安裝於 前述插座之受測裝置的測試型樣者，該記憶體係從連接 於該可程式邏輯裝置的複數受測裝置，並行地讀取來自 當進行預燒試驗之際已安裝於前述插座之受測裝置的 輸出信號並與邏輯值作比較，然後將其結果作為試驗結 果來加以儲存者。 S 3534 201142320 If you want to store it. 12. A control method for a pre-burning system, comprising: one or a plurality of pre-burning plates, and a pre-burning device insertable into the pre-burning plate, wherein the pre-burning plate comprises: a plurality of programmable logic devices , the circuit structure can be changed according to the configuration data; and the plurality of sockets can be installed with the device under test, and connected to any of the plurality of programmable logic devices, and each of the plurality of programmable logic devices of the pre-burning plate Each of the foregoing sockets is connected, and the control method is characterized in that: before the burn-in test, the configuration data is supplied to the plurality of programmable logic devices from the pre-burning device, and circuits and memories are formed in each of the plurality of programmable logic devices. The circuit generates a test pattern that is supplied to the device under test that has been installed in the socket when the burn-in test is performed, and the memory system reads in parallel from a plurality of devices under test connected to the programmable logic device. Taking the output signal from the device under test installed in the aforementioned socket at the time of performing the burn-in test and comparing it with the logical value, and then the result is obtained Test results for the person to be stored. S 35
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