201122883 六、發明說明： 【發明所屬之技術領域】 本發明為一種積體電路設計的漏電流分佈的模擬方 法’尤指一種應用於積體電路設計過程中的積體電路設計 . 的漏電流分佈的模擬方法。 【先前技術】 通常，一積體電路裝置是由一個積體電路設計公司（jc design company，or IC design house)所設計之。積體電路設 φ 計公司提供積體電路裝置的設計圖(layout)給一個半導體製 造廠(semiconductor fabrication plant，or fab)，然後半導體製 造廠依據此設計圖來生產、製作此積體電路裝置。 在製作的過程中，主動區域的臨界尺寸(activecritical dimension)、多晶矽的臨界尺寸（p〇ly critical dimensi〇n)、 閘極介電層的厚度(thickness 〇f gate dielectric layer)、組成 物、離子植入狀況等的製程變異都會影響積體電路裝置的 驅動電流(drivingCurrent)。同時，積體電路裝置的漏電流 φ (leakage CUrrent)也會被該些製程變異影響，所以製造出來的 積體電路裂置的漏電流會有一分佈範圍，而不是一個定 值。假如產品的漏電流的分佈超過積體電路設計公司所定 彡的規要求’麟產^會被認為有漏電流錯誤(leakage failure)。 然而，除非設計公司收到從半導體製造廠送來的包含 ，們的積體電路裝置的晶圓，然:後測試該晶圓 ’設計公司 j法預先知道他們_體電路I置是否有漏電流錯誤。 曰"又计公司知道時’往往是他們完成設計圖後幾個月後的 事換句居3兒，设计公司無法馬上知道他們的設計圖是否 3/14 201122883 會有漏電流錯誤，更不用說針對漏電流錯誤而修改設計圖。 緣是，本發明人有感上述缺失可以改善，因此提出一 種a又计合理且有效改善上述缺失之本發明。 【發明内容】 本發明之主要目的在於提供一種積體電路設計的漏電 流分佈的模擬方法，其能夠在積體電路設計實際地被半導 體製造廠製造前，預先模擬積體電路設計的漏電流分佈。 為達上述目的，本發明提供一種積體電路設計的漏電 流分佈的模擬方法，包括步驟如下：⑻、取得一個包含多 數個電晶體及錄個電容的積體電路設計_電路描述槽 (netlist) ’（b)、分析該電路描述檔，以取得多數個電晶體的 尺寸及多數個電容的尺寸，以及取得每一個該電晶體的尺 寸所對應的-電晶體的數目，與每—個該電容的尺寸所對 應的電谷的數目，（c)、取得一個用以製造該些電晶體及 該些電容的製簡乡數健程變賊^ wind〇w); (d)、根據該些製程變異範圍’來將該些電晶體的尺寸與該 些電谷的尺寸變化；（e)、模擬出每—個變化後的該電晶體 的尺寸的-漏電流值’模擬出每—個變化後的該電容的尺 寸的-漏f流值，其巾·漏電流值是由—特別為積體電 路的模擬程式(SPICE)所模擬出；（f)、將每一個該電晶體的 尺寸的漏電流值分別與該尺寸所對應的電晶體的數目相 乘;以及將每-健電容的尺相漏電流值分難該尺寸 所對應的電谷的數目相乘；（g)、將該些相乘後的漏電流值 做運算’以制-總漏電流值；（h)、重複步驟⑷至步驟(g)， =得到其他❹數個總漏電流值；以及(i)、從該些總漏電 流值產生出一漏電流分佑。 4/14 201122883 藉此’本發明的積體電路設計的漏電流分佈的模擬方 法具有以下有益效果：在積體電路設計實際被製造前，由 製程變異所造成的漏電流分佈可預先被知道。因此如果漏 電流分佈超過規範要求，積體電路設計圖可以立即修改而 減少或改善漏電流錯誤。也就是說，漏電流錯誤可以在設 計公司内的設計階段就被檢視之，早於半導體製造廠内的 製造階段。 為使能更進一步了解本發明之特徵及技術内容，請參 镰 閱以下有關本發明之詳細說明及圖式，然而所附圖式僅供 參考與說明用，並非用來對本發明加以限制者。 【實施方式】 凊餐閱第-®所示’本發明提出—個積體電路設計的 漏電流分佈的模擬方法。該模擬方法可應用在一積體電路 的設計流程中，藉此幫助工程師設計一個有較少漏電流錯 誤的積體電路設計圖(layout ofintegrated circuit device)。該 模擬方^可藉由軟體的形式來實施，或是軟體結合硬體的 Φ 开，式來實施。該模擬方法可以在單獨-台電腦上執行，或 是在多台互相交互作用的電腦上執行。藉由本實施例的模 . 财法，—個積體電路設計圖可能的職流錯誤可以在設 計階段時，就被有效地估計出。 請繼續參考第-圖所示，本發明的積體電路設計的漏 電流分佈的模擬方法的詳細流程如下。 步驟S101 :首先，設計公司的設計者（或工程師）選 擇一個積體電路設計圖，欲藉由後續的步驟來評估並漏電 流分佈的情況。該積體電路設計圖顯示出組成積體電路的 電晶體、電容及内通道(int⑽nnecti〇ns)等元件的尺寸、形 5/14 201122883 狀、方向、形纽位置等。崎體電路設計圖通常會被轉 換成-電路描述檀(netlist)，然後儲存至—資料庫(database) 中。電路描賴以文字格式來記賴频電路設計圖，所 以電路描述檔可較輕易地被電腦分析。當工程師選擇完一 個積體電路設計®後’相對應的電路描賴將會從資料庫 中取出，以進一步使用之。 步驟S103 :接著’被取得的電路描述檔進一步地被分 析，以分別地將積體電路設計圖的電晶體及電容依據他們 的尺寸而分類多數個群組。擁有相同尺寸的電晶體會被分 配至同一個群組中，而擁有相同尺寸的電容會被分配至同 一個群組中。用來分類的電晶體及電容的尺寸包括：通道 見度(channel width)、通道長度(channei iength)以及閘極介 電層厚度(thickness of gate dielectric layer)等，該些尺寸可決 定電晶體及電容的特性及表現。請參閱第二圖所示，一表 格顯示出一部分的電晶體群組。每一個群組都包含資訊如 下：電晶體的數目及電晶體的尺寸。 換句話說’在分析完電路描述檔後，多數個電晶體的 尺寸（寬度、長度及厚度）及多數個電容的尺寸將被取得。 而該些電晶體的尺寸對應的電晶體的數目，以及該些電容 的尺寸對應的電容的數目也會同時被取得。也就是，電晶 體及電容的尺寸相對於數目（dimensions versus count)的分 佈可被瞭解。 步驟S105 :然後，從設計公司的資料庫中，取得一個 用以製造所選擇的積體電路設計圖的製造流程的多數個製 造參數(pr〇cess parameters)。該些製造參數原先是儲存在— 個半導體製造廠中’然後半導體製造廠提供給設計公司使 6/14 201122883 用。該些製造參數包括：主動區域的臨界尺寸、多晶石夕的 臨界尺寸、間極介電層的厚度等會影響電晶體及電容尺寸 $參數。由於該些製造參數在製造流程中，會在一範圍内 艾化所以每-個製造參數都具有一製程變異範圍⑦職π wmdow)’或稱為公差，也就是說製造參數具有—目標值及 ' 一相對目標值的偏差值。 步驟S107 :取得該些製程參數的製程變異範圍後，依 據該些製程變異範圍及該些電晶體的尺寸及電容的尺寸來 • 建立一製程裝置統計模型(pr〇CeSS-devicestatistics)。該製程 裝置統計模型包含多數個電晶體的尺寸及電容的尺寸的變 異情況。也就是說，電晶體的尺寸及電容的尺寸依據製程 變異範圍隨機地變化多次。請參閱第三圖所示，一表格顯 示出一個製程裝置統計模型之中，部分的尺寸變異情況。 每-個變異情況代表-個被所製作出的晶圓可能具有的電 晶體及電容的實際尺寸，所以電晶體的尺寸及電容的尺寸 變化越多次，製程裝置統計模型包含越多的尺寸變異情 • 況，則越多個可能被製作出的晶圓可被考量到，進而讓漏 電流分佈的模擬越準確。 步驟S109 :之後，製程裝置統計模型中的每一個變化 後的尺寸將被模擬出一個對應的漏電流值，同時多數個電 性參數也會被模擬出，該些電性參數為驅動電流(saturati〇n driving current)、臨界電壓(threshold voltage)及電阻值等。 漏電流值及電性參數可使用一些商用軟體來模擬出，例如 一特別為積體電路的模擬程式（simulation program with integrated circuit emphasis，SPICE)，或是利用一些方程式模 擬出。 7/14 201122883 步驟Sill :繼續’每一個變化後的尺寸的漏電流值將 與該尺寸所對應的數目相乘，變化後的尺寸的電性參數也 會與該尺寸所對應的數目相乘。然後將相乘後的尺寸的漏 電流值做運算’以得到此變異情況所對應的一全晶片漏電 流值（full-chip leakage value)，或稱為總漏電流值(t〇tal leakage value))。其他相乘後的電性參數也會做運算，以得 到此變異情況所對應的總電性參數。 步驟S111會為了製程裝置統計模型的全部變異情況， 重複地執行多次’以得全部變異情況的總漏電流值。步驟 S113 :之後從製程裝置統計模型的全部總漏電流值之中， 產生出一個相對應的漏電流分佈。 步驟S115 :該漏電流分佈將會被確認其是否合乎一規 範要求(spec requirement)。如果漏電流分佈超過規範要求， 漏電流分佈可能會導致一漏電流失誤。代表積體電路設計 圖或是該積體電路設計圖所對應的製造流程需要被修改， 主要是修改積體電路設計圖中電晶體及電容的尺寸。 另外在步驟S109之中，製程裝置統計模型可以藉由一 裝置測試資料(device test data)來校正。該裝置測試資料是 由一個已經製造出的積體電路中取得，所以裝置測試資料 包括實際的電性參數。每一個變異情況中的模擬電性參數 將與該些實際的電性參數比較，如果某一個變異情況的模 擬電性參數與實際的電性參數差異太大，則步驟S111將不 會對此變異情況執行之。 通常，積體電路設計圖可以讓多個不同的半導體製造 廠製造，而每一個半導體製造廠都有他們自身的製造參數 及製程變異範圍。所以漏電流分佈在不同的半導體製造薇 8/14 201122883 都會有所變化。而本模擬方法可以應用於不同半導髏製造 廠中，以得到一個該些半導體製造廠的漏電流比棘資訊 (leakage comparison)。之後，設計者或工程師可從漏電流比 較資訊中得知，哪一個半導體製造廠有較佳的漏電流分 佈。請參考第四圖所示，並配合參考第一圖所示，详細的 流程說明如下。 步驟S401 ··首先’選擇一個積體電路設計圖，然後從 資料庫中取得對應該積體電路設計圖的電路描述檀，並且 分析該電路描述檔以產生電晶體及電容的尺寸與數目的分 佈。步驟S401類似於前述的步驟S1〇i至si〇3。步驟S403: 從多數個半導體製造廠中分別地取得一個製造流程（其用 以製造該積體電路設計圖）中的多數個製造參數。本實施 例中，以三個半導體製造廠為例。每一個半導體製造廠的 製程參數都不盡相同’所以製程參數有他們本身的製程變 異情況’也就是製程變異範圍。步驟S403類似於前述的步 驟S105應用在多個半導體製造廠中。 步驟S405 :依據製程變異範圍，每一個半導體製造廠 的一製程裝置統計模型將分別地被建立出，此步驟類似前 述的步驟S107。步驟S407 :接著，依據前述的步驟S109 至S113 ’產生出每一個製程裝置統計模型的漏電流分佈， 也就是產生出每一個半導體製造廠的漏電流分佈。 步驟S409 :在每一個半導體製造廠的漏電流分佈都產 生後，一個關於該些漏電流分佈的漏電流比較資訊也隨之 被建立出。由該漏電流比較資訊，工程師即可瞭解哪一個 半導體製造廠能對於他們的積體電路設計圖，提供較佳的 漏電流分佈’藉此選擇一個適合的半導體製造廠。 9/14 201122883 請參考第五圖所示，並配合第一圖所示，本發明的積 體電路設計的漏電流分佈的模擬方法更包括下列步驟，說 明如下。 ° .步驟S50H GDS巾’取得一個監控裝置㈣趣 device)。監控裝置為一個設計中的電晶體群組，代表在光 罩或製造流程中，一些對製程變異較敏感的典型特徵。該 監控裝置疋依循一監控裝置規範而取得，該監控裝置規範 包括：特徵密度(pattern density)、方位、間距及電晶體的^ 寸等。被取出的監控裝置的積體電路設計圖與步驟 選擇的積體電路設計圖相似。 步驟S503 :接著，取得該監控裳置的一光罩量測資料 (mask measurement data)，以進一步得到該監控裝置的光罩 尺寸變異。因為製程有公差存在，所以該監控裝置的積體 電路設計_尺指會與監控裝置的光罩的財不同。從 該光罩量測資料即可知道光罩的尺寸變異為何。 欠 步驟S5〇5 4後，取得該監控裝置的一製造量測資料 (fabrication measurement data)，以進—步得到該監控裝置的 製程參數變異。該製造量測資料包括：光微影量測資料 (lithographic measurement data)及蝕刻量測資料（etch measurement data)等0 步驟S’ ：最後，計算因為尺寸變異及製程變異所導 致的漏電流分佈，以瞭解該監控裝置的漏電流分佈。如果 該漏電流分佈超過錢要求的話，卫程師<進—步地改善 所選擇的積體電路設計圖，或是改善製程參數。 ° 綜合上述’該積豸電路設計的漏電流分怖的模擬方法 具有特點如下。該模擬方法可以在積體電路設計實際被半 10/14 201122883 造前’模擬出積體電路設計的漏電流分佈。 = 求，工程師可修™ 應用在多 I因此4師可以知道哪— a “ 積體電]千導祖衣k廠對於他們的 能提供較㈣—佈。總結地說， 、、法可以郎省積體電路設計的成本及時間。201122883 VI. Description of the Invention: [Technical Field] The present invention is a simulation method for leakage current distribution of an integrated circuit design, especially a leakage current distribution applied to an integrated circuit design in an integrated circuit design process. The simulation method. [Prior Art] Generally, an integrated circuit device is designed by a jc design company, or IC design house. The integrated circuit is provided by φ. The company provides a layout of the integrated circuit device to a semiconductor fabrication plant (or fab), and the semiconductor manufacturer then manufactures and fabricates the integrated circuit device according to the design. In the process of fabrication, the active critical dimension of the active region, the critical dimension of the polycrystalline germanium (p〇ly critical dimensi〇n), the thickness of the gate dielectric layer (thickness 〇f gate dielectric layer), the composition, the ions Process variations such as implant conditions can affect the driving current (drivingCurrent) of the integrated circuit device. At the same time, the leakage current φ (leakage CUrrent) of the integrated circuit device is also affected by the process variations, so the leakage current of the fabricated integrated circuit will have a distribution range instead of a fixed value. If the leakage current distribution of the product exceeds the specifications set by the integrated circuit design company, the product will be considered to have a leakage failure. However, unless the design company receives the wafers from the semiconductor manufacturing plant that contain the integrated circuit devices, then: after testing the wafers, the design company knows in advance whether they have leakage current. error.曰"And the company knows that it is often a matter of months after they complete the design drawing, and the design company can’t immediately know if their design is 3/14 201122883. There will be leakage current error, not to mention Said to modify the design for the leakage current error. On the contrary, the present inventors have felt that the above-mentioned deletion can be improved, and therefore, the present invention which provides a reasonable and effective improvement of the above-mentioned deficiency is proposed. SUMMARY OF THE INVENTION The main object of the present invention is to provide a simulation method for leakage current distribution of an integrated circuit design, which can pre-simulate the leakage current distribution of an integrated circuit design before the integrated circuit design is actually manufactured by a semiconductor manufacturing factory. . To achieve the above object, the present invention provides a method for simulating a leakage current distribution of an integrated circuit design, including the following steps: (8) Obtaining an integrated circuit design including a plurality of transistors and recording a capacitor _ circuit description slot (netlist) '(b), analyze the circuit description file to obtain the size of a plurality of transistors and the size of a plurality of capacitors, and obtain the number of transistors corresponding to the size of each of the transistors, and each of the capacitors The number of electric valleys corresponding to the size, (c), obtaining a manufacturing method for manufacturing the transistors and the capacitors; (d) according to the processes The variation range 'to change the size of the transistors and the size of the electric valleys; (e) to simulate the - leakage current value of each transistor after the change - to simulate each change The size of the capacitor - the leakage current value, the value of the towel leakage current is simulated by - in particular, the analog circuit (SPICE) of the integrated circuit; (f) the leakage of the size of each of the transistors The electric crystal whose current value corresponds to the size respectively The number of times is multiplied; and the magnitude of the leakage current of each of the capacitances is divided by the number of electric valleys corresponding to the size; (g), the multiplied leakage current values are calculated as ' - total leakage current value; (h), repeating steps (4) to (g), = obtaining other total leakage current values; and (i) generating a leakage current from the total leakage current values. 4/14 201122883 The simulation method of the leakage current distribution of the integrated circuit design of the present invention has the following advantageous effects: the leakage current distribution caused by the process variation can be known in advance before the integrated circuit design is actually manufactured. Therefore, if the leakage current distribution exceeds the specification, the integrated circuit design diagram can be modified immediately to reduce or improve the leakage current error. That is, leakage current errors can be viewed at the design stage within the design company, prior to the manufacturing phase within the semiconductor manufacturing facility. The detailed description and drawings of the present invention are intended to provide a further understanding of the invention. [Embodiment] The present invention proposes a simulation method of leakage current distribution of an integrated circuit design. This simulation method can be applied to the design flow of an integrated circuit to help engineers design a layout of integrated circuit device with fewer leakage current errors. The simulation can be implemented by a software form, or by a soft body combined with a hardware Φ. The simulation method can be performed on a separate computer or on multiple computers that interact with each other. With the simulation method of the present embodiment, a possible job flow error of an integrated circuit design diagram can be effectively estimated at the design stage. Referring to Fig. 3, the detailed flow of the simulation method of the leakage current distribution of the integrated circuit design of the present invention is as follows. Step S101: First, the design company (or engineer) selects an integrated circuit design diagram to evaluate and leak current distribution by subsequent steps. The integrated circuit design diagram shows the dimensions, shape, shape, shape, and the like of the transistors, capacitors, and internal channels (int(10)nnecti〇ns) that make up the integrated circuit. The Sakae circuit design diagram is usually converted to a circuit description netlist and then stored in a database. The circuit delineates the design of the frequency circuit in a text format, so the circuit description file can be easily analyzed by the computer. When the engineer selects an integrated circuit design®, the corresponding circuit description will be taken from the database for further use. Step S103: The circuit description file that is subsequently taken is further analyzed to separately classify the transistors and capacitors of the integrated circuit layout into a plurality of groups according to their sizes. Cells with the same size are assigned to the same group, and capacitors of the same size are assigned to the same group. Dimensions of the transistors and capacitors used for classification include: channel width, channel length (channei iength), and thickness of gate dielectric layer, etc., which determine the transistor and The characteristics and performance of the capacitor. Referring to the second figure, a table shows a portion of the transistor group. Each group contains information such as the number of transistors and the size of the transistor. In other words, after analyzing the circuit description file, the size (width, length and thickness) of most transistors and the size of most capacitors will be obtained. The number of transistors corresponding to the size of the transistors, and the number of capacitors corresponding to the sizes of the capacitors, are also simultaneously obtained. That is, the distribution of dimensions and capacitance of the crystal and capacitor can be understood. Step S105: Then, from the design company's database, a plurality of manufacturing parameters for manufacturing the selected integrated circuit design drawing are obtained. These manufacturing parameters were originally stored in a semiconductor manufacturing facility and then supplied by the semiconductor manufacturer to the design company for use on 6/14 201122883. The manufacturing parameters include: the critical dimension of the active region, the critical dimension of the polycrystalline stone, the thickness of the inter-electrode layer, etc., which affect the transistor and capacitor size $ parameters. Since the manufacturing parameters are in the manufacturing process, they will be in a range, so each manufacturing parameter has a process variation range of 7 π wmdow) or a tolerance, that is, the manufacturing parameters have a target value and ' A deviation from the target value. Step S107: After obtaining the process variation range of the process parameters, according to the process variation range and the size of the transistors and the size of the capacitor, a statistical model (pr〇CeSS-devicestatistics) of the process device is established. The statistical model of the process unit includes variations in the size of a plurality of transistors and the size of the capacitors. That is to say, the size of the transistor and the size of the capacitor vary randomly depending on the range of process variation. Referring to the third figure, a table shows some of the dimensional variations in a statistical model of a process unit. Each variation represents the actual size of the transistors and capacitors that may be produced by the fabricated wafer. Therefore, the more the size of the transistor and the size of the capacitor change, the more the size variation of the statistical model of the process device is included. In the case of a situation, the more wafers that may be produced can be considered, and the more accurate the simulation of the leakage current distribution is. Step S109: After that, each changed size in the statistical model of the process device will be simulated with a corresponding leakage current value, and at the same time, a plurality of electrical parameters are also simulated, and the electrical parameters are driving currents (saturati Drivingn driving current), threshold voltage and resistance value. Leakage current values and electrical parameters can be simulated using some commercial software, such as a simulation program with integrated circuit emphasis (SPICE), or simulated using some equations. 7/14 201122883 Step Sill: Continue 'The leakage current value of each changed size will be multiplied by the number corresponding to the size, and the electrical parameter of the changed size will also be multiplied by the number corresponding to the size. Then, the leakage current value of the multiplied size is calculated as 'to obtain a full-chip leakage value corresponding to the variation, or a total leakage current value (t〇tal leakage value) ). The other multiplied electrical parameters are also calculated to obtain the total electrical parameters corresponding to the variation. In step S111, the total leakage current value of all the variations is repeatedly performed for the entire variation of the statistical model of the process device. Step S113: A corresponding leakage current distribution is generated from all the total leakage current values of the statistical model of the process device. Step S115: The leakage current distribution will be confirmed whether it meets a spec requirement. If the leakage current distribution exceeds the specification, the leakage current distribution may cause a leakage current error. The manufacturing process corresponding to the integrated circuit design diagram or the integrated circuit design diagram needs to be modified, mainly to modify the size of the transistors and capacitors in the integrated circuit design drawing. Further, in step S109, the process device statistical model can be corrected by a device test data. The device test data is obtained from an integrated circuit that has been manufactured, so the device test data includes actual electrical parameters. The simulated electrical parameters in each variation will be compared with the actual electrical parameters. If the simulated electrical parameters of a certain variation are too different from the actual electrical parameters, then the variation will not be performed in step S111. The situation is implemented. In general, integrated circuit designs can be made by many different semiconductor manufacturers, and each semiconductor manufacturer has its own manufacturing parameters and process variation range. Therefore, the leakage current distribution will vary in different semiconductor manufacturing systems, 8/14 201122883. This simulation method can be applied to different semi-conducting manufacturers to obtain a leakage comparison of these semiconductor manufacturing plants. Designers or engineers can then learn from the leakage current comparison information which semiconductor manufacturer has a better leakage current distribution. Please refer to the fourth figure, and refer to the first figure, the detailed process is explained as follows. Step S401 · First, 'select an integrated circuit design diagram, and then obtain a circuit description corresponding to the integrated circuit design diagram from the database, and analyze the circuit description file to generate the size and number distribution of the transistor and the capacitor. . Step S401 is similar to the aforementioned steps S1〇i to si〇3. Step S403: A plurality of manufacturing parameters in a manufacturing process (which is used to manufacture the integrated circuit design drawing) are separately obtained from a plurality of semiconductor manufacturing plants. In this embodiment, three semiconductor manufacturing plants are taken as an example. The process parameters of each semiconductor manufacturing plant are different, so the process parameters have their own process variations, which is the process variation range. Step S403 is applied to a plurality of semiconductor manufacturing plants similarly to the aforementioned step S105. Step S405: According to the process variation range, a statistical model of a process unit of each semiconductor manufacturing factory will be separately established, and this step is similar to the above-mentioned step S107. Step S407: Next, the leakage current distribution of the statistical model of each of the process devices is generated according to the foregoing steps S109 to S113', that is, the leakage current distribution of each semiconductor manufacturing plant is generated. Step S409: After the leakage current distribution of each of the semiconductor manufacturing plants is generated, a leakage current comparison information about the distribution of the leakage currents is also established. From this leakage current comparison information, engineers can understand which semiconductor manufacturers can provide a better leakage current distribution for their integrated circuit design, thereby choosing a suitable semiconductor manufacturing plant. 9/14 201122883 Please refer to the fifth figure, and in conjunction with the first figure, the simulation method of the leakage current distribution of the integrated circuit design of the present invention further includes the following steps, which are explained below. ° Step S50H GDS towel 'Get a monitoring device (4) interesting device). The monitoring device is a group of transistors in the design that represents some of the typical features that are sensitive to process variations in the reticle or manufacturing process. The monitoring device is obtained in accordance with a monitoring device specification including: pattern density, orientation, spacing, and transistor size. The integrated circuit design of the taken-out monitoring device is similar to the selected integrated circuit design. Step S503: Next, a mask measurement data of the monitoring skirt is obtained to further obtain a mask size variation of the monitoring device. Because the process has tolerances, the integrated circuit design of the monitoring device is different from that of the monitoring device. From the reticle measurement data, you can know the variation in the size of the reticle. After the step S5〇5 4 is owed, a manufacturing measurement data of the monitoring device is obtained to further obtain the process parameter variation of the monitoring device. The manufacturing measurement data includes: lithographic measurement data and etch measurement data, etc. Step S': Finally, calculate the leakage current distribution due to dimensional variation and process variation, To understand the leakage current distribution of the monitoring device. If the leakage current distribution exceeds the cost requirement, the Guardian will step forward to improve the selected integrated circuit design or improve the process parameters. ° The simulation method of integrating the leakage current distribution of the above-mentioned accumulation circuit design has the following characteristics. This simulation method can simulate the leakage current distribution of the integrated circuit design before the integrated circuit design is actually fabricated by the half of the 10/14 201122883. = Seeking, Engineers can repair TM application in multiple I, so the 4 divisions can know which one - a "integrated body" thousand guide ancestor k factory for their ability to provide (four) - cloth. In summary, ,,,,,,,, The cost and time of integrated circuit design.
發明所難為本發日狀健實關，非意欲偏限本 容所ΐ ·15，故舉凡利本發明·書及圖式内 斤為=效變化，均_皆包含於本㈣之權利保護範 固内，合予陳明。 【圖式簡單說明】 笛 、 一圖為本發明的積體電路設計的漏電流分佈的模擬方法 ★ 第一個方法流程圖。 圖為本發明的電晶體尺寸及數目的表格示意圖。 ^〜圖為本發明的電晶體尺寸的變異情況的表格示意圖。 四圖為本發_賴電路設計的漏冑齡佈祕擬方法 咖 第一個方法流程圖。 第五圖為本發明的積體電路設計的漏電流分佈的模擬方法 第二個方法流程圖。 【主要元件符號說明】 步驟 S101SS115 步驟S401至S409 步驟S501至S507 11/14It is difficult for the invention to be healthy and stable, and it is not intended to limit the content of the original. ·15, therefore, the law of the invention, the book and the figure are the effect changes, all of which are included in the protection of this (4) Solid, combined with Chen Ming. [Simple description of the diagram] Flute, a picture is the simulation method of the leakage current distribution of the integrated circuit design of the present invention ★ The first method flow chart. The figure is a tabular representation of the size and number of transistors of the present invention. ^~ Figure is a tabular representation of the variation of the transistor size of the present invention. The four figures are the secret method of the leaking age design of the hair _ Lai circuit. The fifth figure is a simulation method of the leakage current distribution of the integrated circuit design of the present invention. The second method flow chart. [Main component symbol description] Step S101SS115 Steps S401 to S409 Steps S501 to S507 11/14